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Hi - >In article <01bfdc4a$feb79d00$c4f262d1@Dan.i-tech.com>, >Dan Kuechle <dan_kuechle@i-tech.com> wrote: >>Anyone out there using a dual processor PC for Xilinx? A couple of comments on using dual processors: 1) If you're trying to get substantive work done while running place and route, a dual processor is the way to go. If, however, you want to do things that place a relatively light load on the CPU, such as web browsing or editing, you can change the priority of the place and route run by using a UNIX-like utility such as "nice." I scrounged a free version of "nice" (from Cygnus, I think) and have used it when invoking the route tool in batch mode (nice par ...). This lowers the priority of par sufficiently to let you run other things on the machine; with the version of "nice" I have, par run time is increased by only ~5%. 2) I just bought a dual-processor motherboard, and can tell you that this is a particularly treacherous time to buy one. Intel has recently produced not one but two chip sets--the i820 and i840--that are unreliable when used with SDRAM. (Extremely condensed history: Intel produced these chip sets expressly for Rambus RDRAM, then decided to create additional interface chips that would allow them to talk to SDRAM: the MTH for the i820, and the MRH-S for the i840. Both the MTH and MRH-S are unreliable; Intel has recalled its i820/MTH motherboards, and has (very quietly) announced that the MRH-S is unreliable and will no longer be produced--see their PCN #996.) Some retailers are still happily selling i840/MRH-S boards such as the SuperMicro P3DMx series; stay away from these. If you do get a dual-processor motherboard, get one that's based on the old-but-reliable 440BX chip set. Or you can spend major bucks and buy an RDRAM-based i820 or i840 system. Take care, Bob Perlman ----------------------------------------------------- Bob Perlman Cambrian Design Works Digital Design, Signal Integrity http://www.best.com/~bobperl/cdw.htm Send e-mail replies to best<dot>com, username bobperl -----------------------------------------------------Article: 23376
Hi, I search informations about the software lGen from Mentor Graphics. It's a software to generate new synthesis libraries. In fact I try to use it but I have poor informations about the language :( I search to define a LUT and I have not find informations about this. I just find definition of simple gates :(( It's really poor... Thanks a lot if anyone can help me, Regards, SebastienArticle: 23377
Synplicity is the best choice for synthesis. I use both Finsim and VCS for verilog simulation. VCS is expensive but a Finsim license thats good enough for a medium size FPGA can be had for about $2.5K, a full blown Finsim lincense is 10K. Also Cadence has brought out NC Verilog on Linux and I think they are only asking $5K. If you are just picking an HDL, go with Verilog. Verilog simulators are much faster than VHDL, Verilog is much easier to read and write, and it's much more concise. A couple of years ago it seemed like the world was about evenly split between Verilog and VHDL, but these days I don't see VHDL anywhere, everyone seems to be using Verilog. Admitedly my sample is limited, and all the companies that I deal with are in the networking industry. Josh James Kennedy wrote: > > Hi everyone, > > At risk of starting a religious war, I'd like to ask all you people out > there who do _real_ designs with Xilinx FPGA's, what tools do you > currently use, and/or recommend? > > I'm currently in the process (and have been for some time) of trying to > use Xilinx's foundation express but I think it has won the battle :) > > So we're thinking of investing in a less buggy tools suite and I'm > looking for any suggestions. > > Cheers, > James. > > -- > James Kennedy > Electronics/Computer Design Engineer > IntelliDesign > Brisbane, Australia > > james (at) intellidesign dot com dot au > > Tel: (07) 3366 6478 > Fax: (07) 3366 6471Article: 23378
This question comes up periodically in this newsgroup. The limitation in using the asynch reset is the slowness of the distribution. The problem is trying to make sure that all FFs come out of reset at the same time. Using a synch reset does not help the problem since the reset can still happen on different clock edges for the different FFs. Further, you may need to use an asynch reset since your clock may not be present or running slowly and a synch reset will not work in that case. There are a couple of things a design can do to make the end of reset work correctly. 1) If you are running with a sufficiently slow clock, then you can externally synch reset to the clock and you don't have a problem. This is not practical for most designs and the speed of the GSR net is not spec'ed. This also won't work if you have more than one clock domain. 2) Use an additional, separate, synch reset signal that only runs to the critical FFs in the design. By synch, I mean this comes from a FF which is released after the asynch reset and has a two or three clock delay. This should hold in reset any FFs which are in FSMs or other logic which will start changing state as soon as the asynch reset is released. Not all logic needs this signal. For example, only the first two levels of FFs in a one-hot encoded FSM need the synch reset. The rest won't be enabled by the logic until the FSM starts moving through the states. This works well for circuits with mulitple clocks. You can have an independant synch reset for each clock domain. 3) Use the existing logic to hold the circuits in reset. If your circuit depends on external signals to do anything once it is reset, you can make sure that a few clock cycles go by after reset before you start operating the circuit. For example, if the design interfaces to a processor and is idle until the processor sends a command, then you need no additional reset circuit. Anyone else have ideas on this? derekwallace1@my-deja.com wrote: > > Hi All, > Ive started a design of a VirtexE1000. I am looking for advice on how i should > control the taking of the device out of reset after a board reset to the FPGA. > > Here is a summary of my system. 1. a microcontroller delivers an Asynchronous > reset signal to the FPGA. 2. it will be active low for 1 us. 3. the purpose > of the reset is to return the device to the same state as it was just after > configuration. > > Here are some of my questions. 1. it is my understanding that all FFs in > Virtex can be directly Synchronously set or reset i.e. it does not utilise > the LUT. Is this true? 2. should i use the reset signal to reset every FF in > my design? (i think so) 3. should i perform a synchronous reset or an > asynchronous reset of the FFs 4. should i mix it up so that some FFs are rest > Synchronously and some asynchronusly? Is there any real > advantage/disadvantage to this in Virtex if the FFs can be reset > synchronously without using LUT resources. 5. to re-synchronise the > asynchronus input reset i plan to put it through 2 FFs for metastability > purposes. In some case i have seen people only use a single FF. Is it best to > use 1 FF or 2 FFs? 6. how should i drive the reset signal (whether it is > async or sync). Should i use a Bufg (can a Bufg connect to Set reset pins of > FF?) Or should i use the low skew lines? > > Thank you for your time > > Derek > > Sent via Deja.com http://www.deja.com/ > Before you buy. -- Rick Collins rick.collins@XYarius.com Ignore the reply address. To email me use the above address with the XY removed. Arius - A Signal Processing Solutions Company Specializing in DSP and FPGA design Arius 4 King Ave Frederick, MD 21701-3110 301-682-7772 Voice 301-682-7666 FAX Internet URL http://www.arius.comArticle: 23379
On Fri, 23 Jun 2000 05:30:22 GMT, James Kennedy <spam@this.com> wrote: |Hi everyone, | |At risk of starting a religious war, I'd like to ask all you people out |there who do _real_ designs with Xilinx FPGA's, what tools do you |currently use, and/or recommend? | |I'm currently in the process (and have been for some time) of trying to |use Xilinx's foundation express but I think it has won the battle :) | |So we're thinking of investing in a less buggy tools suite and I'm |looking for any suggestions. | |Cheers, |James. James, we use Xilinx Foundation right out of the box, schematic entry. Works fine. JohnArticle: 23380
Peter Alfke wrote: > > Well, nobody is joking or pulling anybody's leg. ...snip... > I don't want to parse Illan's syntax here, but I think he tried to challenge > our assertion that ASIC designers will have more trouble with deep submicron > than FPGA users will. But that is a fact. At the deep submicron level, things > are not as clean and digital as they were in the olden days of Mead-Conway. > Capacitive loading, fan-out issues, on-chip transmission-line effects, > crosstalk, ground bounce, clock-tree balancing, Vcc and ground distribution > etc. are getting really demanding, and every ASIC user will be confronted with > these ugly issues. ...snip... > Technological progress favors FPGAs more than ASICs, and it thus tilts the > playing field. > That's all we wanted to say. We preached this in our seminars more than a year > ago. > If you don't want to believe us now, let's talk again next year, when we're > heading for a billion transistors on a chip. Moore's law has a few more years > to go... > > Peter Alfke, Xilinx Applications > ================================================== That sounds great, but you need to compare apples to apples. There is a BIG difference in the number of gates on the two devices at a given technology level. So if I am using an FPGA at .15 micron, I would only need to use an ASIC at say, .5 micron to get the same number of useful gates on the same size chip. The silicon and the tools at this level have been around for a long time and are not a problem to use. Even when the state of the art is .05 microns, a comparable ASIC will only need to be at .15 microns and the tools will be very mature by that time. I agree that FPGAs will keep eating into ASIC territory. But it is not because deep submicron design is getting tougher. It is because FPGAs will reach price and density points that satisfy more and more designs. It is probably comparable to what is happening in the microprocessor world. The 8 bit chips get faster and have more memory on board. But they have not taken over from the 16 and 32 bit chips. The applications get bigger with the chips and there will always be separate markets for each. But the 8 bit chips do grow faster and eat a bigger share every year. -- Rick Collins rick.collins@XYarius.com Ignore the reply address. To email me use the above address with the XY removed. Arius - A Signal Processing Solutions Company Specializing in DSP and FPGA design Arius 4 King Ave Frederick, MD 21701-3110 301-682-7772 Voice 301-682-7666 FAX Internet URL http://www.arius.comArticle: 23381
Anyone ever download the old Application Briefs from ALTERA BBS back in the early 90's? I have all my old application books and was looking specifically for AB 84 design files. Some of it is on ftp.altera.com but not the original GDF. I know someone must have downloaded these old files, finding them is a pain. Altera will not release them because they want to sell megacores. --Bob Sent via Deja.com http://www.deja.com/ Before you buy.Article: 23382
Hi, While I belive all FPGA vendor will work properly when you connect directly FF to FF inspite of this warning, when it come to asic we simple add buffer between the two FF's. So you might want to do this, as it will not effect the design and will remove this msg. (of course you might need two buffers or on the other hand use a smaller buffer, just choose a one that his time (min) delay is a bit more than what the msg complain). have a nice day Illan In article <39483ea7.0@news.cyberway.com.sg>, "MK Yap" <mkyap@REMOVE.ieee.org> wrote: > Hi!! > > " Error: Delay path from '|bsp_in:73|bytedata_2_.Q' to > '|bsp_in:73|intdata_2_.Q' is 4.2ns, but Clock skew is 2.9ns and hold time > required for '|bsp_in:73|intdata_2_.Q' is 1.4ns - circuit cannot operate > because Clock skew plus hold time of destination register exceeds > register-to-register delay " > > I encounter this problem when i've finished compiling the project & doing > the timing analysis. Most of the time, my design did not give me this error > mesg but it happened ocassionally. I changed other part of the circuit but > did not make any changes on the bsp_in portion. What can I do to ensure this > won't happen again? How can i put any constraint and where i should put it? > Thanks. > > I'm using Maxplus2 9.3 & Synplify 5.3.1 for my VHDL codes, running on PC, > targetted at flex10k30e. > Pls advice > > MK > > Sent via Deja.com http://www.deja.com/ Before you buy.Article: 23383
gordon.haddow@eev.com wrote in message <8iv9lr$l47$1@nnrp1.deja.com>...
>Hi everyone,
>I've been using the Atmel FPGA integrated development system for some
>months, including the Everest VHDL synthesiser. Unfortunately it seems
>to have a bug in the way bidirectional pins are handled. If you look at
>the .edf netlist the input line does not come from the pin, but from
>the output line prior to the output tristate.
>Atmel don't have a fix. Has anyone else come across this? Does anyone
>have a way of working round this in VHDL - perhaps coding at very low
>level? Anyway, here's the code that fails:
>
> gen_data_ram : process(pixel_clock)
> begin
> if pixel_clock = '1'
> then data_ram <= data_in;
> else data_ram <= "ZZZZZZZZZZ";
> end if;
> end process gen_data_ram;
problem!!! your sensitivity list needs to include data_in. This is a
combinatorial process. Or, more succintly, do the following:
data_ram <= data_in when pixel_clock = '1' else (others => 'Z');
> gen_data_out : process(pixel_clock, data_ram)
> begin
> if pixel_clock'event and pixel_clock='1' then
> data_out <= data_ram;
> end if;
> end process gen_data_out;
>
>end behave;
problem!!! If you want to generate flip-flops, the ONLY things that should
be in the sensitivity list are the clock and an async reset. In other
words,
gen_data_out : process (pixel_clock) is
begin
if rising_edge(pixel_clock) then
data_out <= data_ram;
end if;
end process gen_dat_out;
Now, there's another, more subtle issue here: you're using pixel_clock as
both the clock to a bunch of flops, and as an output enable. Depending on
your chip's architecture, you may not be able to do this. Usually, clocks
get put onto global low-skew routing resources which only drive clock
inputs, and if you try to do anything else with it (like drive an output
enable, or use it as an input to a function) the tools will not use the
low-skew resource, which could lead to big trouble.
-andy
--
-----------------------------------------
Andy Peters
Sr Electrical Engineer
National Optical Astronomy Observatories
950 N Cherry Ave
Tucson, AZ 85719
apeters (at) noao \dot\ edu
"A sufficiently advanced technology is indistinguishable from magic"
--Arthur C. Clarke
Article: 23384an XC4000 CLB got 2 4-input-LUTs and 1 3-input-LUT it said it can implements some functions up to 9 variables. I want to ask who knows exactly how many functions up to 9 variables can be implemented.... -- ************************************************************************* * /\ /\ Name : Wu Chi Hang J±êùÚ ( FOX ) ** ª° ¯W ** * * ^ ^ Job : ELEC/CPEG Demonstrator (Rm. 2466, Ext. x7037 ) * * . . Email: eefox@uxmail.ust.hk / eefox@ee.ust.hk * * =o = chwu@usa.net / 97Cwch@alumni.ee.ust.hk * * u Hpage: http://www.ee.ust.hk/~eefox/index.html 4294435 * *************************************************************************Article: 23385
Dan Kuechle wrote in message <01bfdc4a$feb79d00$c4f262d1@Dan.i-tech.com>...
>Anyone out there using a dual processor PC for Xilinx?
>
>My last project takes about 1.5 hours to complie the single
>Xilinx chip if I do nothing else, and upwards of 3 hours if I
>try and do some work while the Xilinx s/w is running. Since
>my PC is only 350mhz (windows 95) its probably time for
>an upgrade. I'm wondering about dual processors, thinking
>one could run Xilinx while I use the other to get some real
>work done while the Xilinx s/w is running. Anyone got
>any insights or recomendations?
Others have tried dual processors and reported their results. Here's what I
did: I told the boss that the old PII/233 wasn't cutting it, so I got a
PIII/550. I pleaded my case: let me use the new machine for design only and
keep the old one for MS Office and crap like that, and he bought the
argument. The new machine only has the FPGA development tools, and some
other stuff, like WinSpice and MathCAD. No MS Office, no mail client, no
extraneous BS. So I do P+R on the new machine and read Usenet on the old
one.
Here's the moral of the story: the new machine is more expensive if you're
buying a dual CPU system. And I'll bet the old one isn't going to just
vanish in a puff of smoke. Dig?
>Dual processors will force me into windows 2000 or NT.
>Any problems with that?
NT is better than 98. No question. In fact, you should probably be doing
the real work on NT. I don't know about Win2K. I think I'll wait until
Service Pack 4 comes out.
-- a
-----------------------------------------
Andy Peters
Sr Electrical Engineer
National Optical Astronomy Observatories
950 N Cherry Ave
Tucson, AZ 85719
apeters (at) noao \dot\ edu
"A sufficiently advanced technology is indistinguishable from magic"
--Arthur C. Clarke
Article: 23386Hi, You can't be serius, This remind all those places who ask you to bring name of people that will be your referance and obviusly you will give only name of people who think you are at the very least the newxt Einstein. the same here the point of showing a site with success story is nothing. who says there design was done quicker than if it was done in asic, who says that they are not poor designer who don't know how to design Asic's, who says that they didn't had a bad experiance in the past and using it now and so on and so on ... I wonder if TSMC will show a site with success story of people who desing Asic's and pass them in the first time and did it very quickly and wrote it so will this mean that Asic are faster easier better can be done on first and so on ? I would expect some thing more concret in which you explain why you said what you said and why you belive it to be right. Of course as one mention you should compare how a certain design whould have been done in FPGA Vs Asic and not that in FPGA it took 500M gate and in Asic same thing will cost ... since in Asic we don't need so many gates. also as one mention we will not need in asic the same technology even tho' I think he gave a bit bigger technology than I would but still his point is right. once you take a "imagenary design" and do the comparision than you are standing on equal ground, and you can claim what ever you claim base on it. I belive in my previus msg I put all the phases needed to get a chip I even put timing you might disagree with so I would love to see a table in which you compare the time etc of each stage asic vs fpga and than the total sum and conclution. I wonder if once you get this table done you will still hold your belive so strongly. Lastly about the clock tree that someone else mention, I must say that while a clock tree is not "fun", it is sometime a GREAT advantage to be able to control, and "play with", and no need to tell me it is risky or dangerous etc etc as thing are risky and dangerous when you do thing you don't understand but if you do understand you can get thing done that in other way you might not been able and had to compremise, or use an extra pll etc. and to give a small exmaple assume a chip with 20 clock domain, one is the "master" which most of the chip work with it and 19 other are only use in small part/logic. to use 20 PLL will be ... the power/noise etc are ... so you will most likely want to use one PLL for the main clock and the other clock will have clock tree but without PLL. now the output signal from those 19 clock domain in the best case will take several ns since there is the clock tree than the clk->Q of the FF and than if you have Jtag there is additional mux and than there is the Output pad itself. now assume you work in 125M clock so the period is 8n, and assume this signal need to go to another chip which is not yours and the trace on the board plus setup is let say 4n than you need to have your signal out in 4n and it is a problem as the clock tree can be (of course depend on the load) let say 3n and the rest is also 3n so you are 2n to much. now if you can "play" with the clock tree and to this particular signal FF give the clock from the root of the tree than you are in good shape. of course this mean that the signal which come to the FF have less time than a whole period as the clock to this FF come sooner but this can be solved in the design or even by adding another FF (or even two as syncronizer and treat it as going from one clock domain to another even tho it is only phase issue). this way you can get it work. This is only one example and even here I could extrem it by taking the frequancy even higher. one small additional point since someone mention that you don't need to do in FPGA clock tree etc, while I don't see it as advantage mostly it is the same in asic as your vendor will do it so for you as a user in mnay cases it is only the desing part and than synthesis place and route etc etc are done not by you. FPGA are great components and my belive is that if you have a new design and you can do it in FPGA than do so, but many design simple can't be done in FPGA and can only be done in Asic, and just as FPGA vendor are keeping moving forward with technology the same is for Asic vendors. and just as FPGA vendor work to make there fpga look digital for the user as we users don't want to take care of the analog effect of sub-micron the same is with Asic's Vendor and Fabs, so I wouldn't jump and say that Asic designer will have to either move to fpga or have to deal with analog problems. have a nice day Illan In article <395277DA.24784027@xilinx.com>, Austin Lesea <austin.lesea@xilinx.com> wrote: > Well, > > Look at our customers' success stories. > > http://www.xilinx.com/company/success/index.htm > > Austin > > iglasner@my-deja.com wrote: > > > Hi, > > > > I might missed something but it seem to me as you belive this huge > > chip when target to FPGA take less time than when target to ASIC. and > > more over they have "have inferior tools" > > > > I wonder how did you come to this conclutions ? > > > > I would think the design might take even longer in FPGA as I might need > > to re-code or write is a bit more messy to get the FPAG work in high- > > performance. > > than the simulation I would think are just about the same (as while you > > might want to save sometime in the FPAG as you can always re-code it > > for a big design if you don't simulate properly you will simple go > > forth and back between the lab and your computer) > > than come the synthesis which is again about the same as well as the > > simulation for the post synthesis gate level > > and than come the place and route and the clock tree which about the > > same with it's simulation of post place and route with the netlist and > > sdf files. (the clock tree might take few extra days) > > and than come some saving which are the vectors which you don't need > > and maybe also bist check and scan insertion that might make timing > > problem if was not taken for the start into considuration > > so I would think that for a design that take let say 10 month (after > > all we do speak about large design so it might be even longer) you > > might save about 2-3 weeks or even a month which is something but I > > wouldn't say it is enough to say "takes too long" > > > > and to the tools what exactly is inferior ? there are very good tools > > for synthesis and place and route as well as scan insertion clock tree > > etc for asic (e.g you might heard about Synopsys) ? > > > > I can undertsand the risk as in many cases a metal fix can take between > > a 1-2 month and a complete spin will take even take a more (depend of > > course on how bad are the bugs). > > > > I will even agree with the more expensive as the NRE for 0.25 or less > > are something to consider. (the price for NRE for 0.35 as well as the > > price for metal spin etc in the overall are not "too expensive" but you > > might want to add them as well) > > > > have a nice day > > > > Illan > > > > In article <3952285C.3DFA8EE7@xilinx.com>, > > Austin Lesea <austin.lesea@xilinx.com> wrote: > > > Wake up & smell the silicon, > > > > > > I couldn't resist responding to this. > > > > > > Steve is in the cube across from me, and we teased him on how > > conservative he > > > was. > > > > > > Like Peter says, we have the time to do what is needed to make this > > scale of > > > technology work: the ASIC/ASSP model is probably limited to less > > than 50 > > > million devices. It is too expensive, too risky, takes too long, > > have inferior > > > tools, and is unable to claim the advantages it once did. > > > > > > http://www.support.xilinx.com/xcell/xl30/xl30_10.pdf was written two > > years > > > ago. It is so satisfying to see the team's vision realized. Thank > > you to all > > > of our customers, and we will continue to provide you with the > > solutions you > > > need to succeed. > > > > > > Austin Lesea, ICDES Group, Xilinx > > > > > > EKC wrote: > > > > > > > I got this quote from eetimes.com. Is this technically feasible? > > > > > > > > <<START QUOTE>> > > > > Panelist Steve Young, an architect of the Virtex FPGA family of > > Xilinx (San > > > > Jose, Calif.), advocated FPGAs in his presentation. But he > > surprised many > > > > when he said he expects the number of transistors on a single FPGA > > to hit > > > > 500 million in 2001, with the Xilinx Virtex-II family. > > > > > > > > Engineers designing FPGA silicon for companies such as Xilinx are > > coping > > > > with some of the most difficult deep-sub-micron devices around, > > Young said. > > > > "We face a number of problems so you don't have to," he said. These > > include > > > > simultaneous switching, deep-submicron parasitics, fault coverage, > > and clock > > > > skew management. > > > > > > > > "Like all chip designers, we are customers of EDA tools," said > > Young. "And > > > > we are challenging them." He said commercial EDA tools just aren't > > designed > > > > for the size of devices Xilinx engineers are building. > > > > > > > > Panel presentations will be available at the DAC Web site > > (www.dac.com) in a > > > > few weeks. > > > > > > > > http://www.eetimes.com/ > > > > > > > > Copyright c 2000 CMP Media Inc. > > > > <<END QUOTE>> > > > > > > > > > > Sent via Deja.com http://www.deja.com/ > > Before you buy. > > Sent via Deja.com http://www.deja.com/ Before you buy.Article: 23387
Let's take the original XC4000 CLB and only look at the basic structure with two 4-input LUTs each feeding the third LUT, with an extra input to that 3rd LUT. Now you have 9 inputs driving 16+16+8=24 bits of ROM inside the LUTs. So it seems to me that you can implement 2exp24 = 16.7 million functions of the 9 variables. Mathematically, there are 2exp512 functions of 9 variables, so the CLB can only implement a tiny subset of that enormous number. But parity check over 9 bits is one interesting application that can be done. And there are many more. Peter Alfke WU Chi Hang FOX wrote: > an XC4000 CLB got 2 4-input-LUTs and 1 3-input-LUT > it said it can implements some functions up to 9 variables. > I want to ask who knows exactly how many functions up to 9 variables > can be implemented.... > -- > ************************************************************************* > * /\ /\ Name : Wu Chi Hang ?J±êùÚ ( FOX ) ** ª° ¯W ** * > * ^ ^ Job : ELEC/CPEG Demonstrator (Rm. 2466, Ext. x7037 ) * > * . . Email: eefox@uxmail.ust.hk / eefox@ee.ust.hk * > * =o = chwu@usa.net / 97Cwch@alumni.ee.ust.hk * > * u Hpage: http://www.ee.ust.hk/~eefox/index.html 4294435 * > *************************************************************************Article: 23388
I'd definitely suggest Synplify from Synplicity. I have tried fpgaexpress and leonardo and bought Synplify. Really fast synthesis, really good output. James Kennedy <spam@this.com> wrote: >Hi everyone, > >At risk of starting a religious war, I'd like to ask all you people out >there who do _real_ designs with Xilinx FPGA's, what tools do you >currently use, and/or recommend? > >I'm currently in the process (and have been for some time) of trying to >use Xilinx's foundation express but I think it has won the battle :) > >So we're thinking of investing in a less buggy tools suite and I'm >looking for any suggestions. > >Cheers, >James.Article: 23389
The XC4000 can do any function of 4 variables in the 4 input LUTs. It can do any function of 3 variables in the 3 input LUT. The combination connected in the default manner does 3_func(4_func(a,b,c,d), 4_func(e,f,g,h), j). A logical combination of N inputs gives 2^(2^N) boolean functions. So a 3 input function can do 256 functions and a 4 input function can do 65536 functions. The above combination is 65536 * 65536 * 256 = 1099511627776 or 2^40. Compare to 9 input functions which are too large to calculate on an 18 digit scientific calculator!!! WU Chi Hang FOX wrote: > > an XC4000 CLB got 2 4-input-LUTs and 1 3-input-LUT > it said it can implements some functions up to 9 variables. > I want to ask who knows exactly how many functions up to 9 variables > can be implemented.... > -- > ************************************************************************* > * /\ /\ Name : Wu Chi Hang J±êùÚ ( FOX ) ** ª° ¯W ** * > * ^ ^ Job : ELEC/CPEG Demonstrator (Rm. 2466, Ext. x7037 ) * > * . . Email: eefox@uxmail.ust.hk / eefox@ee.ust.hk * > * =o = chwu@usa.net / 97Cwch@alumni.ee.ust.hk * > * u Hpage: http://www.ee.ust.hk/~eefox/index.html 4294435 * > ************************************************************************* -- Rick Collins rick.collins@XYarius.com Ignore the reply address. To email me use the above address with the XY removed. Arius - A Signal Processing Solutions Company Specializing in DSP and FPGA design Arius 4 King Ave Frederick, MD 21701-3110 301-682-7772 Voice 301-682-7666 FAX Internet URL http://www.arius.comArticle: 23390
Sorry, I said 16+16+8 = 24, not very smart! Rickman is right, it's 40 ,and thus over a thousand billion functions. So we both agree. Peter Rickman wrote: > The XC4000 can do any function of 4 variables in the 4 input LUTs. It > can do any function of 3 variables in the 3 input LUT. The combination > connected in the default manner does 3_func(4_func(a,b,c,d), > 4_func(e,f,g,h), j). > > A logical combination of N inputs gives 2^(2^N) boolean functions. So a > 3 input function can do 256 functions and a 4 input function can do > 65536 functions. The above combination is 65536 * 65536 * 256 = > 1099511627776 or 2^40. Compare to 9 input functions which are too large > to calculate on an 18 digit scientific calculator!!! > > WU Chi Hang FOX wrote: > > > > an XC4000 CLB got 2 4-input-LUTs and 1 3-input-LUT > > it said it can implements some functions up to 9 variables. > > I want to ask who knows exactly how many functions up to 9 variables > > can be implemented.... > > -- > > ************************************************************************* > > * /\ /\ Name : Wu Chi Hang ?J±êùÚ ( FOX ) ** ª° ¯W ** * > > * ^ ^ Job : ELEC/CPEG Demonstrator (Rm. 2466, Ext. x7037 ) * > > * . . Email: eefox@uxmail.ust.hk / eefox@ee.ust.hk * > > * =o = chwu@usa.net / 97Cwch@alumni.ee.ust.hk * > > * u Hpage: http://www.ee.ust.hk/~eefox/index.html 4294435 * > > ************************************************************************* > > -- > > Rick Collins > > rick.collins@XYarius.com > > Ignore the reply address. To email me use the above address with the XY > removed. > > Arius - A Signal Processing Solutions Company > Specializing in DSP and FPGA design > > Arius > 4 King Ave > Frederick, MD 21701-3110 > 301-682-7772 Voice > 301-682-7666 FAX > > Internet URL http://www.arius.comArticle: 23391
On 23 Jun 2000 16:56:10 GMT, eefox@uxmail.ust.hk ( WU Chi Hang FOX ) wrote: >an XC4000 CLB got 2 4-input-LUTs and 1 3-input-LUT >it said it can implements some functions up to 9 variables. >I want to ask who knows exactly how many functions up to 9 variables >can be implemented.... What happened to the good old days, when students copied their homework answers from fellow classmates? Bob Perlman ----------------------------------------------------- Bob Perlman Cambrian Design Works Digital Design, Signal Integrity http://www.best.com/~bobperl/cdw.htm Send e-mail replies to best<dot>com, username bobperl -----------------------------------------------------Article: 23392
In article <3953AB4A.CA452839@xilinx.com>, Peter Alfke <peter.alfke@xilinx.com> wrote: >Now you have 9 inputs driving 16+16+8=24 bits of ROM inside the LUTs. >Peter Alfke Nice one Peter! New math is hard :-) An answer to the original question is 2^40 possible functions, many of which are not interesting, or are synonyms. PhilipArticle: 23393
I have a lot of questions which I'm sure are asked constantly so let me just go ahead and ask where the FAQ is located or if someone would repost it? Here are the questions anyway if someone doesn't mind answering them. 1) Where do you find FPGA programmers? Are there schematics to build your own? If I wanted to make a system say using a microcontroller with a PLD or FPGA to configure, how would I do it? I know xilinx sells their test boards but those are for one chip use and soldering and desolering would be a pain. 2) PLDs and FPGAs - When you remove them do they keep their data? For instance, I program them with say a simple register and remove it from the programmer would it still be usable on another system? 3) Off-Topic (sorry, no PLD newsgroup or is there?) - In digikey's catalog the Xilinx XC9500 CPLDs have registers but no mention of flip-flops. What's the difference? I know the difference as far as any digital design book will tell me but what does that mean when programming it? 4) What's a good site to learn more about PLDs and/or PGAs? Thanks, EricArticle: 23394
Eric L wrote: > I have a lot of questions which I'm sure are asked constantly so let me just go > ahead and ask where the FAQ is located or if someone would repost it? > > Here are the questions anyway if someone doesn't mind answering them. > > 1) Where do you find FPGA programmers? Are there schematics to build your own? Don't. You really don't need a separate programmer since all "modern" CPLDs can be programmed in the system, and SRAM-based FPGAs never needed a programmer. That leaves only the antifuse parts in need of a programmer. But since they are not even reprogrammable, you might as well let the distributor program them for you. > > If I wanted to make a system say using a microcontroller with a PLD or FPGA to > configure, how would I do it? I know xilinx sells their test boards but those > are for one chip use and soldering and desolering would be a pain. I don't understand what you mean. > > > 2) PLDs and FPGAs - When you remove them do they keep their data? For instance, > I program them with say a simple register and remove it from the programmer > would it still be usable on another system? All CPLDs and all antifuse FPGAs keep their configuration, since they are non-volatile. All other FPGAs lose it, since it is stored in latches. > > > 3) Off-Topic (sorry, no PLD newsgroup or is there?) - In digikey's catalog the > Xilinx XC9500 CPLDs have registers but no mention of flip-flops. What's the > difference? I know the difference as far as any digital design book will tell > me but what does that mean when programming it? "register" and "flip-flop' are synonymous, unless you specifically talk about "byte-wide" register etc. Peter AlfkeArticle: 23395
Dual P-II/400, 512MB SDRAM, 24GB SCSI Disk, DAT tape backup, NT4.0 + SP5 Xilinx Alliance M2.1i / M3.1i + latest SP Viewlogic (Inoveda) Viewdraw Schematic capture Fliptronics FlibGen/Flibtime Automatic schematic module generator Viewlogic (Inoveda) ViewSim gate level simulation Viewlogic (Inoveda) VCS/Fusion Verilog simulation Fliptronics ChipView for post place and route analysis of utilization, placement, timing, worst case paths. Synopsys FPGA Express Verilog and VHDL Synthesis Synplicity Synplify Verilog and VHDL Synthesis All use of Xilinx tools is from the command line. My experience is that all the Automated flow engines (which is the core of the Foundation package) are too restrictive, make assumptions that are incorrect, do not allow flows that the underlying tools are capable of, and create a project directory tree that is crazy. Philip Freidin In article <3952F531.69095D19@this.com>, James Kennedy <spam@this.com> wrote: >At risk of starting a religious war, I'd like to ask all you people out >there who do _real_ designs with Xilinx FPGA's, what tools do you >currently use, and/or recommend? >I'm currently in the process (and have been for some time) of trying to >use Xilinx's foundation express but I think it has won the battle :) >So we're thinking of investing in a less buggy tools suite and I'm >looking for any suggestions. >James.Article: 23396
hey all, I want to install the F2.1i at home. Unfortunately, i can't have internet connection. Will the F2.1i be fully functionnal if i use just a schematic entry Thanks. --Erika Sent via Deja.com http://www.deja.com/ Before you buy.Article: 23397
In article <Pine.OSF.4.21.0006230159320.20030-100000@ece.wpi.edu>, Christof Paar <christof@ece.wpi.edu> wrote: >H. Wu. >Montgomery multiplier and squarer in GF(2^m). What does it mean to do Montgomery multiplication in GF(2^m)!? Also, is the author H.-H. Wu of the University of California, Berkeley? Or a different H. Wu? Thanks.Article: 23398
>Don't. You really don't need a separate programmer since all "modern" CPLDs can >be >programmed in the system, and SRAM-based FPGAs never needed a programmer. That >leaves only the antifuse parts in need of a programmer. But since they are not >even reprogrammable, you might as well let the distributor program them for you. > >> So how would I do it if I bought a Xilinx XC9500? >> If I wanted to make a system say using a microcontroller with a PLD or FPGA to >> configure, how would I do it? I know xilinx sells their test boards but those >> are for one chip use and soldering and desolering would be a pain. > >I don't understand what you mean. > >> >> well let's say I have a robot that has a xilinx FPGA in it and I program it to be an AND-gate (for discussion purposes) and then I suddenly need it to act as an OR-gate. How would I do something like that? Perhaps the previous question and this question are the same.. Thanks ericArticle: 23399
In article <01bfdc4a$feb79d00$c4f262d1@Dan.i-tech.com>, dan_kuechle@i-tech.com (Dan Kuechle) wrote: > Anyone out there using a dual processor PC for Xilinx? > > My last project takes about 1.5 hours to complie the single > Xilinx chip if I do nothing else, and upwards of 3 hours if I > try and do some work while the Xilinx s/w is running. Since > my PC is only 350mhz (windows 95) its probably time for > an upgrade. I'm wondering about dual processors, thinking > one could run Xilinx while I use the other to get some real > work done while the Xilinx s/w is running. Anyone got > any insights or recomendations? > > Dual processors will force me into windows 2000 or NT. > Any problems with that? > > Others where I work are interested from an Altera point of > view also. I've been using dual-processor systems for years, and would be very reluctant to have a uniprocessor as my main work machine. 2 x XXX MHz is slower on benchmarks than 1 x 2XXX, but subjectively /feels/ a lot faster because it doesn't bog down on CPU-intensive tasks. A machine that I can't use for 1.5 hours is costing me more than a machine that lets me get on with other stuff in the meantime. There's a bit of a shortage of decent dual motherboards ATM. After Intel's cockup with the 820/840 chipsets, the only good one around that isn't a fairly ancient design seems to be the Tyan Thunder 2500. It's expensive, but includes a lot of good stuff on-board which you'd probably have to buy anyway. I confess I don't know any specifics wrt Xilinx, but the Altera stuff works without problems. Ditto for ViewLogic, Cypress Warp and everything else I've actually used for CAE. It /is/ sometimes the case that things fail on a dual system because the developer hasn't done their homework properly, but it's getting rarer. -- Steve Rencontre http://www.rsn-tech.demon.co.uk //#include <disclaimer.h>
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