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Hi, I have a project I'm working on in my spare time which would be much easier to implement using an FPGA. Unfortunately the software cost in using this type of device is too high. What I'm looking for is a FPGA where the cost of the software is reasonable (<$100 - preferably free). Any help tracking such a beast down would be appreciated. I would really like to use the SpartanXL, but Xilinx now has this silly yearly licensing fee system which is fine if you use it commercially....but for hobbyists its a little excessive. Any help would be appreciated. Regards Peter ElliotArticle: 23326
In article <961689224.99684@axilla.wwnet.net>, Peter Elliot <elliotpj@henrob.com> wrote: >Hi, > >I have a project I'm working on in my spare time which would be much easier >to implement using an FPGA. Unfortunately the software cost in using this >type of device is too high. > >What I'm looking for is a FPGA where the cost of the software is reasonable >(<$100 - preferably free). Xilinx offers a Student Edition version of their software, for about $100, which is often associated/included in $100 textbooks as well. It is limited in the size of part it can map to, but is otherwise pretty fully functional. I think also that the foundation base is pretty fully functional except for HDL synthesis and a fairly similarly limited part range. I think the reason why Xilinx has shifted to a time base liscencing is that they have MUCH higer support costs for their software then most, and this is a way of essentially making it clear: You aren't buying the software. You are buying 1 year of technical support. -- Nicholas C. Weaver nweaver@cs.berkeley.eduArticle: 23327
Peter Elliot wrote: > Hi, > > I have a project I'm working on in my spare time which would be much easier > to implement using an FPGA. Unfortunately the software cost in using this > type of device is too high. > > What I'm looking for is a FPGA where the cost of the software is reasonable > (<$100 - preferably free). > > Any help tracking such a beast down would be appreciated. I would really > like to use the SpartanXL, but Xilinx now has this silly yearly licensing > fee system which is fine if you use it commercially....but for hobbyists its > a little excessive. > I suggest the Xilinx Student Edition for $105.- ( just at the upper end of your budget) You can order it from amazon: http://www.amazon.com just go to books, and enter Xilinx as the search word. And a year from now, this thing will neither die nor explode. In fact, you can use it later in the century to impress your grandchildren. :-) Peter Alfke, Xilinx ApplicationsArticle: 23328
Hi, I have a project I'm working on in my spare time which would be much easier to implement using an FPGA. Unfortunately the software cost in using this type of device is too high. What I'm looking for is a FPGA where the cost of the software is reasonable (<$100 - preferably free). Any help tracking such a beast down would be appreciated. I would really like to use the SpartanXL, but Xilinx now has this silly yearly licensing fee system which is fine if you use it commercially....but for hobbyists its a little excessive. Any help would be appreciated. Regards Peter Elliot -- +-----------------------------------------+ | email: peter.elliot@ukonline.co.uk | | http://web.ukonline.co.uk/peter.elliot/ | +-----------------------------------------+Article: 23329
Hi, therer are few simple thing to solve this issue of clock skew etc. the first is use an fpga which support more than one clock input and use one of the input clock to source all the area you need to shutdown, this way all the internal routing timing issues are "solved". than treat all the interface between the shutdown area and the non shutdown as an async interface. (you most likely don't need to treat all the interface but it is up to you and your desing). while I can agree that gated clock shouldn't be the prefered option it is sometime a must, just like many times you will hear people say "using latch in asic is wrong" again there are good reason to prefere FF on Latch but sometime you just need to use latch and the importent thing is to understand why/how etc and not just say never and close your eyes. have a nice day Illan In article <39517EC0.B39BF746@yahoo.com>, Rickman <spamgoeshere4@yahoo.com> wrote: > I think we are talking about different things. When I say clock enable > or CE, I am referring to the CE input on the FF. Gating the clock in an > FPGA is not practical since that will add delay to the clock path and > cause problems with skewing. > > I do agree that clock enables (shutting off the clock to a function) > will save power. But my question was very specific. I am asking if there > is a "significant" power savings in an SRAM based FPGA by using the CE > v. using an enable in the LUT. > > At this point I think the answer is not much. It does me no good to save > a mW in a Watt design. I am looking for significant savings. > > But you are right that power can be reduced, sometimes dramatically, by > gating the clocks to the FFs. But we just can't do that reliably in > FPGAs at this point. Maybe they will add that at some other time. > > iglasner@my-deja.com wrote: > > > > hi, > > > > I'm not into the betting arena and even the single night I spend in > > Vegas I prefered to walk arround than do gambling, but you might want > > to know that most cellular phone asic DO close the clock for lot's of > > FF's as well as mem and it DOES make a huge effect on the power > > consumption. > > > > The point that more power might be somewhere else have nothing to do > > with this point, as when you want to save power you save everywhere you > > can. > > > > To your comment that : > > > > "The question is not does the FF use "any" power. But does the FF use > > > less power? I would be willing to bet that most of the power in the > > FPGA" > > > > than the answer is yes the FF will use less power even tho' the > > capacitance look to you a small part, the amount of FF and the > > frequnacy make this small to be not so small. > > > > and yes clock gateing is a "sience" for itself and have big difficult > > of itself but it was done and will be done most likely in the future. > > > > have a nice day > > > > Illan > > > > In article <39505F5F.4A19D624@yahoo.com>, > > Rickman <spamgoeshere4@yahoo.com> wrote: > > > iglasner@my-deja.com wrote: > > > > > > > > Hi, > > > > > > > > A FF even if it "see" the same input level does consume power as > > long > > > > as there is a clock. > > > > > > > > The only way to reduce the power of a group of FF's is by shuting > > down > > > > their clock meaning using clock enable. > > > > > > > > One example for using clock enable is for stand by purpose in > > cellualr > > > > phone, where the power source (battery) is limited. > > > > > > > > have a nice day > > > > > > > > Illan > > > > > > The question is not does the FF use "any" power. But does the FF use > > > less power? I would be willing to bet that most of the power in the > > FPGA > > > is burned in toggling the ouput of a "slice" or CLB or whatever the > > > correct term is for an output from a FF or LUT. I would be willing to > > > bet that much less power is used to toggle a LUT that is only driving > > > the FF in the same CLB. Even less power is likely used by a FF that is > > > clocked, but the output does not change. > > > > > > Certainly internal nodes in a FF are switching anytime the clock > > > switches. But the power used is very small since the capacitance of > > the > > > internal nodes is very small. But to switch the output and the routed > > > trace it connects to is likely the lion's share of where the power > > goes. > > > > > > So I would bet (not heavily since I have most of my money in the stock > > > market and that is the biggest bet I have ever made) that there is > > very > > > little power used by FFs which do not switch their outputs regardless > > of > > > how that is accomplished; D input not changed, CE held low or clock > > > turned off. > > > > > > Anyone care to wager a pint of your faviorite beverage (or Haagen Das > > in > > > my case)? > > > > > > -- > > > > > > Rick Collins > > > > > > rick.collins@XYarius.com > > > > > > Ignore the reply address. To email me use the above address with the > > XY > > > removed. > > > > > > Arius - A Signal Processing Solutions Company > > > Specializing in DSP and FPGA design > > > > > > Arius > > > 4 King Ave > > > Frederick, MD 21701-3110 > > > 301-682-7772 Voice > > > 301-682-7666 FAX > > > > > > Internet URL http://www.arius.com > > > > > > > Sent via Deja.com http://www.deja.com/ > > Before you buy. > > -- > > Rick Collins > > rick.collins@XYarius.com > > Ignore the reply address. To email me use the above address with the XY > removed. > > Arius - A Signal Processing Solutions Company > Specializing in DSP and FPGA design > > Arius > 4 King Ave > Frederick, MD 21701-3110 > 301-682-7772 Voice > 301-682-7666 FAX > > Internet URL http://www.arius.com > Sent via Deja.com http://www.deja.com/ Before you buy.Article: 23330
I was told by prentice hall that the new Xilinx student edition book with Foundation 2.1 base is due out july 17 ISBN# 0130289078 And should support up to all the spartan and spartanXL Devices +the vertex xcv50 On Thu, 22 Jun 2000 13:00:55 -0400, Peter Elliot <peter.elliot@ukonline.co.uk> wrote: >Hi, > >I have a project I'm working on in my spare time which would be much >easier to implement using an FPGA. Unfortunately the software cost in >using this type of device is too high. > >What I'm looking for is a FPGA where the cost of the software is >reasonable (<$100 - preferably free). Any help tracking such a beast >down would be appreciated. > >I would really like to use the SpartanXL, but Xilinx now has this >silly yearly licensing fee system which is fine if you use it >commercially....but for hobbyists its a little excessive. > >Any help would be appreciated. > >Regards > >Peter Elliot > > >-- >+-----------------------------------------+ >| email: peter.elliot@ukonline.co.uk | >| http://web.ukonline.co.uk/peter.elliot/ | >+-----------------------------------------+Article: 23331
I'll second that! It is nice that the Virtex-E datasheet now includes a pin definition for every pin: all IOs, VCCI, VCCO, GND, and special pins, at least for the FG676 package. With the older Virtex datasheets the IOs weren't defined so you needed to use the process of elimination to determine them! But having a separate text file would make life a lot easier, especially for the bigger packages. "Simon" <simonb@tile.demon.co.cuthis.uk> wrote in message news:961679716.5438.0.nnrp-10.9e9832fa@news.demon.co.uk... > Since one of the objectives of copying is to extract the > pinouts, perhaps pinout tables could be provided > on the web site in a plain text format. > > Robert Binkley wrote in message <39511274.41ED1204@hamxilinx.com>... > > > >Good news, Spartan/xl/II datasheets on our website were updated earlier > today > >(pretty quick huh?). You got what you asked for. I just downloaded it, > and you > >can highlight the text. Any other doc suggestions/complaints? :) > > > >Robert Binkley > >Xilinx Applications > > >Article: 23332
Hi, I might missed something but it seem to me as you belive this huge chip when target to FPGA take less time than when target to ASIC. and more over they have "have inferior tools" I wonder how did you come to this conclutions ? I would think the design might take even longer in FPGA as I might need to re-code or write is a bit more messy to get the FPAG work in high- performance. than the simulation I would think are just about the same (as while you might want to save sometime in the FPAG as you can always re-code it for a big design if you don't simulate properly you will simple go forth and back between the lab and your computer) than come the synthesis which is again about the same as well as the simulation for the post synthesis gate level and than come the place and route and the clock tree which about the same with it's simulation of post place and route with the netlist and sdf files. (the clock tree might take few extra days) and than come some saving which are the vectors which you don't need and maybe also bist check and scan insertion that might make timing problem if was not taken for the start into considuration so I would think that for a design that take let say 10 month (after all we do speak about large design so it might be even longer) you might save about 2-3 weeks or even a month which is something but I wouldn't say it is enough to say "takes too long" and to the tools what exactly is inferior ? there are very good tools for synthesis and place and route as well as scan insertion clock tree etc for asic (e.g you might heard about Synopsys) ? I can undertsand the risk as in many cases a metal fix can take between a 1-2 month and a complete spin will take even take a more (depend of course on how bad are the bugs). I will even agree with the more expensive as the NRE for 0.25 or less are something to consider. (the price for NRE for 0.35 as well as the price for metal spin etc in the overall are not "too expensive" but you might want to add them as well) have a nice day Illan In article <3952285C.3DFA8EE7@xilinx.com>, Austin Lesea <austin.lesea@xilinx.com> wrote: > Wake up & smell the silicon, > > I couldn't resist responding to this. > > Steve is in the cube across from me, and we teased him on how conservative he > was. > > Like Peter says, we have the time to do what is needed to make this scale of > technology work: the ASIC/ASSP model is probably limited to less than 50 > million devices. It is too expensive, too risky, takes too long, have inferior > tools, and is unable to claim the advantages it once did. > > http://www.support.xilinx.com/xcell/xl30/xl30_10.pdf was written two years > ago. It is so satisfying to see the team's vision realized. Thank you to all > of our customers, and we will continue to provide you with the solutions you > need to succeed. > > Austin Lesea, ICDES Group, Xilinx > > EKC wrote: > > > I got this quote from eetimes.com. Is this technically feasible? > > > > <<START QUOTE>> > > Panelist Steve Young, an architect of the Virtex FPGA family of Xilinx (San > > Jose, Calif.), advocated FPGAs in his presentation. But he surprised many > > when he said he expects the number of transistors on a single FPGA to hit > > 500 million in 2001, with the Xilinx Virtex-II family. > > > > Engineers designing FPGA silicon for companies such as Xilinx are coping > > with some of the most difficult deep-sub-micron devices around, Young said. > > "We face a number of problems so you don't have to," he said. These include > > simultaneous switching, deep-submicron parasitics, fault coverage, and clock > > skew management. > > > > "Like all chip designers, we are customers of EDA tools," said Young. "And > > we are challenging them." He said commercial EDA tools just aren't designed > > for the size of devices Xilinx engineers are building. > > > > Panel presentations will be available at the DAC Web site (www.dac.com) in a > > few weeks. > > > > http://www.eetimes.com/ > > > > Copyright c 2000 CMP Media Inc. > > <<END QUOTE>> > > Sent via Deja.com http://www.deja.com/ Before you buy.Article: 23333
Hi group I would like to make a 32-bit ripple carry counter in a Xilinx Spartan FPGA - how can I do that in VHDL? KrestenArticle: 23334
Phil Endecott wrote in message <3951E9D1.3DA62015@spamcop.net>...
>Hi Xilinx Experts,
>
>I've just added a second tristate driver to a bus in my design and
>suddenly the "generating PAR statistics" phase of PAR has gone
>from taking a few seconds to taking the best part of an hour :-(.
>
>Xilinx technical support say:
>
> The long PAR time, though a nuisance, does appear to be reasonable.
>
> Tristate delay calculations will always be more complicated as you
>have
> to consider the output capacitance of the drivers as additional
>loading
> on the bus (not just the usual input cap of receivers).
>
>...which I don't like; it sounds to me like their algoirthm has
>gone from O(n) to O(n^2) or something like that. I'm worried that
>when I shortly add a third driver the time to do these delay
>calculations will exceed a week!
>
>So: has anyone else run into this problem? Is anyone using an
>on-chip tristate bus and still getting reasonable PAR times? Another
>consideration is that the bus goes into a synthesized ROM and so has
>lots (hundreds) of loads.
My current board design has two XC4013XLAs, both of which have tristate
busses. My P+R times are reasonable. Perhaps you should consider
registering the tristated busses and have the register outputs drive the
other logic?
for example,
mux <= busa when ena = '1' else (others => 'Z');
mux <= busb when enb = '1' else (others => 'Z');
mux <= busc when enc = '1' else (others => 'Z');
mux <= busd when end = '1' else (others => 'Z');
regmux : process (clk, rst) is
begin
if rst = '1' then
muxr <= (others => '0');
elsif rising_edge (clk) then
muxr <= mux;
end if;
end process regmux;
-a
-----------------------------------------
Andy Peters
Sr Electrical Engineer
National Optical Astronomy Observatories
950 N Cherry Ave
Tucson, AZ 85719
apeters (at) noao \dot\ edu
"A sufficiently advanced technology is indistinguishable from magic"
--Arthur C. Clarke
Article: 23335Are you trying to use a bit of VHDL to transparently blend the distributed and block RAM? Andy Lars <Lotzen@intersci.com> wrote in message news:ee6cd4d.-1@WebX.sUN8CHnE... > Hi everybody! > > Since I need more internal memory on my VIRTEX I have to use the distributed RAM parallel to the block RAM. But I don't know how I can access the block RAM under VHDL. > Can somebody help me - maybe with a sourcecode piece with value pre-initialization ? > > THX in advance, > LarsArticle: 23336
Though I know nothing about DNA, there is a Carnegie Mellon course on reconfigurable computing that was offered. This course talks about DNA sequence matching and a multi-FPGA system called SPLASH and SPLASH 2 that were used to accelerate DNA sequence comparisons. You will have to hunt in the course notes for this information though (as this was not the only course topic) and I think it is a bit old but maybe it will be helpful to you. The link to the course page is http://www.cs.cmu.edu/afs/cs/academic/class/15828-s98/www/index.html Alex :) EKC <NOSPAMalpha3.1@ix.netcom.com> wrote in message news:eoe45.1924$az.221144@dfiatx1-snr1.gtei.net... > Does anyone have any experience in the use of FPGAs for accelerating DNA > sequencing algorithms? I'm particularly interested in the use of FPGAs for > accelerating the BLAST algorithm for DNA sequencing. > Most of these algorithms are like hybrid string-search algorithms which > must parse a large database representing a DNA sequence for various > variations of the search string. Such algorithms look like they could easily > benefit from the use of mulit-processor systems or computer clusters. > However, I think that the cost-performance ratio would be lower if I could > implement the algorithm as a parallel process in some FPGAs (each iteration > of the search would ideally take one clock cycle). > I'm looking at either building my own board (several Xilinx FPGA's > linked to a PCI bus) or buying a board from a vendor. Does anyone have any > favorite FPGA boards with PCI interfaces? > > --- > --- > EKC > > If you would like to e-mail me, remove the string 'NOSPAM' > from my e-mail address. > >Article: 23337
> All modern Xilinx FPGA permanently disable all "vertical" clock branches > that are not used in the design. This saves power, but does not help you in > changing things dynamically. So at the expense of approx. 1781 bits of data transfer to the config memory on an XCV-300, is it possible to disable vertical clock branches with partial dynamic reconfiguration or am I missing something? Alex :)Article: 23338
In article <eoe45.1924$az.221144@dfiatx1-snr1.gtei.net>, EKC <NOSPAMalpha3.1@ix.netcom.com> wrote: > Does anyone have any experience in the use of FPGAs for accelerating DNA >sequencing algorithms? I'm particularly interested in the use of FPGAs for >accelerating the BLAST algorithm for DNA sequencing. > Most of these algorithms are like hybrid string-search algorithms which >must parse a large database representing a DNA sequence for various >variations of the search string. Such algorithms look like they could easily >benefit from the use of mulit-processor systems or computer clusters. >However, I think that the cost-performance ratio would be lower if I could >implement the algorithm as a parallel process in some FPGAs (each iteration >of the search would ideally take one clock cycle). > I'm looking at either building my own board (several Xilinx FPGA's >linked to a PCI bus) or buying a board from a vendor. Does anyone have any >favorite FPGA boards with PCI interfaces? A few years back, I did a paper design of a 2 bit, specialized, systolic cell for sequence matching in a 4000 series. It required 4 CLBs/cell, and could operate at 100 MHz when floorplanned. This was the basic systolic array computation of the edit distance. Changing it to 4 bit matching would probably require a few more cells, but you definatly want to take advantage of specialization. (It should be pretty straightforward to do with virtex and jbits, it's mostly a matter of plugging in the right values into the luts. This is ONLY the cell itself, not the full design, and as I said, it is a paper design that is RATHER old, but is a good place to start. The basic concept could easily be extended to the 4 bit matcher, which would abosuletly SCREAM when done on a virtex. http://www.cs.berkeley.edu/~nweaver/proj1.html -- Nicholas C. Weaver nweaver@cs.berkeley.eduArticle: 23339
Well, Look at our customers' success stories. http://www.xilinx.com/company/success/index.htm Austin iglasner@my-deja.com wrote: > Hi, > > I might missed something but it seem to me as you belive this huge > chip when target to FPGA take less time than when target to ASIC. and > more over they have "have inferior tools" > > I wonder how did you come to this conclutions ? > > I would think the design might take even longer in FPGA as I might need > to re-code or write is a bit more messy to get the FPAG work in high- > performance. > than the simulation I would think are just about the same (as while you > might want to save sometime in the FPAG as you can always re-code it > for a big design if you don't simulate properly you will simple go > forth and back between the lab and your computer) > than come the synthesis which is again about the same as well as the > simulation for the post synthesis gate level > and than come the place and route and the clock tree which about the > same with it's simulation of post place and route with the netlist and > sdf files. (the clock tree might take few extra days) > and than come some saving which are the vectors which you don't need > and maybe also bist check and scan insertion that might make timing > problem if was not taken for the start into considuration > so I would think that for a design that take let say 10 month (after > all we do speak about large design so it might be even longer) you > might save about 2-3 weeks or even a month which is something but I > wouldn't say it is enough to say "takes too long" > > and to the tools what exactly is inferior ? there are very good tools > for synthesis and place and route as well as scan insertion clock tree > etc for asic (e.g you might heard about Synopsys) ? > > I can undertsand the risk as in many cases a metal fix can take between > a 1-2 month and a complete spin will take even take a more (depend of > course on how bad are the bugs). > > I will even agree with the more expensive as the NRE for 0.25 or less > are something to consider. (the price for NRE for 0.35 as well as the > price for metal spin etc in the overall are not "too expensive" but you > might want to add them as well) > > have a nice day > > Illan > > In article <3952285C.3DFA8EE7@xilinx.com>, > Austin Lesea <austin.lesea@xilinx.com> wrote: > > Wake up & smell the silicon, > > > > I couldn't resist responding to this. > > > > Steve is in the cube across from me, and we teased him on how > conservative he > > was. > > > > Like Peter says, we have the time to do what is needed to make this > scale of > > technology work: the ASIC/ASSP model is probably limited to less > than 50 > > million devices. It is too expensive, too risky, takes too long, > have inferior > > tools, and is unable to claim the advantages it once did. > > > > http://www.support.xilinx.com/xcell/xl30/xl30_10.pdf was written two > years > > ago. It is so satisfying to see the team's vision realized. Thank > you to all > > of our customers, and we will continue to provide you with the > solutions you > > need to succeed. > > > > Austin Lesea, ICDES Group, Xilinx > > > > EKC wrote: > > > > > I got this quote from eetimes.com. Is this technically feasible? > > > > > > <<START QUOTE>> > > > Panelist Steve Young, an architect of the Virtex FPGA family of > Xilinx (San > > > Jose, Calif.), advocated FPGAs in his presentation. But he > surprised many > > > when he said he expects the number of transistors on a single FPGA > to hit > > > 500 million in 2001, with the Xilinx Virtex-II family. > > > > > > Engineers designing FPGA silicon for companies such as Xilinx are > coping > > > with some of the most difficult deep-sub-micron devices around, > Young said. > > > "We face a number of problems so you don't have to," he said. These > include > > > simultaneous switching, deep-submicron parasitics, fault coverage, > and clock > > > skew management. > > > > > > "Like all chip designers, we are customers of EDA tools," said > Young. "And > > > we are challenging them." He said commercial EDA tools just aren't > designed > > > for the size of devices Xilinx engineers are building. > > > > > > Panel presentations will be available at the DAC Web site > (www.dac.com) in a > > > few weeks. > > > > > > http://www.eetimes.com/ > > > > > > Copyright c 2000 CMP Media Inc. > > > <<END QUOTE>> > > > > > > Sent via Deja.com http://www.deja.com/ > Before you buy.Article: 23340
"Kresten Nørgaard" wrote: > Hi group > > I would like to make a 32-bit ripple carry counter in a Xilinx Spartan > FPGA - how can I do that in VHDL? > Kresten, here is the best solution, but somebody else has to code it in Verilog: Dont ripple between flip-flops, since that would waste half the chip area ( remember, there is only one clock per CLB=2 flip-flops). So you design a macro consisting of a 2-bit Johnson (Möbius) counter, i.e. a 2-bit shift register with an inversion in the feedback loop. Use one of the Q outputs as the clock to the next macro. Concatenate 16 such macros for a 32-bit counter. This is the simplest design, but the outputs are not real binary. If you want binary outputs, modify the macro to be a proper 2-bit binary counter ( doesn't cost anything extra, the LUTs do that with inputs to spare.) Then you concatenate 16 of these macros, and you have the highest-frequency resolution, lowest-power consumption counter possible. 400 MHz resolution at <100 milliwatt consumption! Just don't ever try to decode addresses from it. The glitches would be horrible. Ripple counters are not as bad as their reputation, as long as you understand their advantages and disadvantages. Peter Alfke, Xilinx ApplicationsArticle: 23341
Greetings, I want to manually configure and read the internal state of my FPGA. To do this I am tryn' to read the CLB data via a boundary scan (IEEE 1149.1 - JTAG) NOTE: I am using Xilinx's Virtex 300E FPGA. The idea here is that I want to read back all the CLB's and then make sense of the data. To do this I need to compare the CLB data with the *PLACEMENT* of my HDL code on the FPGA. I would like to view all the registers, RAM, and just everything in general inside the FPGA *AS IT HAPPENS* in real time (for debugging). Ok... so that is all I want to do... ok fine... maybe not... (wink) To simplify everything here is my basic question... if it is possible how do you do it? but more specifically... QUESTIONS: 1.) How do you associate the CLB data that you read out of the FPGA with the variables in your VHDL code etc? 2.) Can you use the .fnf file that is generated at compile time to tell you where the CLB's are associated with the internal variables that do not go out to IO pins? If you can't is there such a file that tells you what the CLB data means in terms of your HDL code? 3.) Does Xilinx have any software that will read the CLB data back and show you what the states of the internal variables are as your FPGA is running? 4.) Is there any VHDL or Verilog specific instructions that you need to use to read the CLB's via boundary scan? JUST IN CASE: If you are working on something similar you may find the following documents helpful. XAPP138 & XAPP139: Has some info on configuration of the Virtex FPGA via 4 pins (Boundary Scan pins... TCK, TMS, TDI, TDO). The document explains the process of loading a design bit stream into the FPGA internal configuration memory and then doing a read back or reading that data out to verify. XAPP151: Talks about CLBs, IOBs, and how to configure them through a configuration bit stream (very nice... means you don't have to use Xilinx software if you don't want to... just write the CLB's yourself...) ADDRESSES: - http://www.xilinx.com/xapp/xapp138.pdf - http://www.xilinx.com/xapp/xapp139.pdf - http://www.xilinx.com/xapp/xapp151.pdf Anyhow, your help or comments on how to read the internal state of an FPGA would be greatly appreciated. Take care, >Asher< PS: If you have comments on the configuration of FPGA's via boundary scan they would also be helpful. <<=>>=<<=>>=<<=>><<=>>=<<=>>=<<=>><<=>>=<<=>>=<<=>> Asher C. Martin <<=>>=<<=>>=<<=>><<=>>=<<=>>=<<=>><<=>>=<<=>>=<<=>> WORK ADDRESS: 1050 Lowater Road, Room 272 Chippewa Falls, WI 54729 (715) 726-4761 <<=>>=<<=>>=<<=>><<=>>=<<=>>=<<=>><<=>>=<<=>>=<<=>> asherm@cray.com http://www.uiuc.edu/~martin2/ <<=>>=<<=>>=<<=>><<=>>=<<=>>=<<=>><<=>>=<<=>>=<<=>>Article: 23342
Sorry, I goofed. I thought you meant ripple-counter. Ripple-carry is the natural way for all Xilinx FPGAs, since the carry-structure is built-in. For free. Peter Alfke ====================================== "Kresten Nørgaard" wrote: > Hi group > > I would like to make a 32-bit ripple carry counter in a Xilinx Spartan > FPGA - how can I do that in VHDL? > > KrestenArticle: 23343
Hi Peter, "Peter Elliot" <elliotpj@henrob.com> schrieb im Newsbeitrag news:961689224.99684@axilla.wwnet.net... ... > I would really > like to use the SpartanXL, but Xilinx now has this silly yearly licensing > fee system which is fine if you use it commercially....but for hobbyists its > a little excessive. If you aren't fixed on XILINX too much, take a look at Altera's baseline software, which ic completely free and supports their smaller devices and the new APEX devices as well. Greetings, Carlhermann SchlehausArticle: 23344
Asher Martin-CRAY wrote: > > Greetings, > > I want to manually configure and read the internal state of my FPGA. To > do this I am tryn' to read the CLB data via a boundary scan (IEEE 1149.1 > - JTAG) Also if anyone has a bitstream of what some *LIVE* CLB data looks like form a running Virtex FPGA please e-mail it to me so that I can take a look at the binary... and try to make sense of the data... Take care, >Asher< <<=>>=<<=>>=<<=>><<=>>=<<=>>=<<=>><<=>>=<<=>>=<<=>> Asher C. Martin <<=>>=<<=>>=<<=>><<=>>=<<=>>=<<=>><<=>>=<<=>>=<<=>> WORK ADDRESS: 1050 Lowater Road, Room 272 Chippewa Falls, WI 54729 (715) 726-4761 <<=>>=<<=>>=<<=>><<=>>=<<=>>=<<=>><<=>>=<<=>>=<<=>> asherm@cray.com http://www.uiuc.edu/~martin2/ <<=>>=<<=>>=<<=>><<=>>=<<=>>=<<=>><<=>>=<<=>>=<<=>>Article: 23345
hey all, I want to lock the input of the LUT. Is there any constraint to handle such option, or should i use the epic. If so how Thanx -- Erika Sent via Deja.com http://www.deja.com/ Before you buy.Article: 23346
sorry, i forget to precise that i want to create macro with locked inputs... In article <8itv3g$nbd$1@nnrp1.deja.com>, erika_uk@my-deja.com wrote: > hey all, > > I want to lock the input of the LUT. Is there any constraint to handle > such option, or should i use the epic. If so how > > Thanx > > -- Erika > > Sent via Deja.com http://www.deja.com/ > Before you buy. > Sent via Deja.com http://www.deja.com/ Before you buy.Article: 23347
I've been running dual x86 CPU machines for all my CAE work for a few years now, and would not consider going back to a single CPU machine. I have the following environment: Dual Pentium-II CPU, both at either 300MHz or 400MHz 256 or 512 MB of SDRAM SCSI or EIDE Disk Channel PCI or AGP graphics, nothing particularly fancy Windows NT 4.0 with either SP3 or SP5 (NOT SP4) Xilinx M1.5, M2.1i, M3.1i Viewlogic Workview Office 7.31, 7.4x, 7.5x, including Viewdraw and Viewsim and lots of other stuff. Most important: I never run the Xilinx design manager. All Xilinx tools are run in batch mode from a command line in a DOS box. Philip Freidin In article <01bfdc4a$feb79d00$c4f262d1@Dan.i-tech.com>, Dan Kuechle <dan_kuechle@i-tech.com> wrote: >Anyone out there using a dual processor PC for Xilinx? > >My last project takes about 1.5 hours to complie the single >Xilinx chip if I do nothing else, and upwards of 3 hours if I >try and do some work while the Xilinx s/w is running. Since >my PC is only 350mhz (windows 95) its probably time for >an upgrade. I'm wondering about dual processors, thinking >one could run Xilinx while I use the other to get some real >work done while the Xilinx s/w is running. Anyone got >any insights or recomendations? > >Dual processors will force me into windows 2000 or NT. >Any problems with that? > >Others where I work are interested from an Altera point of >view also. > >Thanks > DanArticle: 23348
Without arguing specifically for Xilinx, Altera, Atmel, or any other: The primary consideration should be the silicon performance, availability, and pricing. The secondary consideration should be the software learning curve, and ease of use. And third you look at software price. If you are halfway serious about achieving something meaningful, and learning something valuable, the difference between $100 and zero is "peanuts", i.e. irrelevant. Peter AlfkeArticle: 23349
Hi Peter If you register at the www.atmel.com home page, you can get a complete FPGA design kit for free. There is also a low cost development board (STK40) for about $150 which includes the FPGA design kit. Contains a synthesizer but no simulator. You may be able to get hold of a VEriwell Verilog simulator for free somewhere. Not so good, buggy, but may serve its purpose for small designs. The AT40K family is pin compatible with Xilinx 4000, 5200 and low pincount Spartan. -- Best regards, ulf at atmel dot com The contents of this message is intended to be my private opinion and may or may not be shared by my employer Atmel Sweden "Peter Elliot" <elliotpj@henrob.com> wrote in message news:961689224.99684@axilla.wwnet.net... > Hi, > > I have a project I'm working on in my spare time which would be much easier > to implement using an FPGA. Unfortunately the software cost in using this > type of device is too high. > > What I'm looking for is a FPGA where the cost of the software is reasonable > (<$100 - preferably free). > > Any help tracking such a beast down would be appreciated. I would really > like to use the SpartanXL, but Xilinx now has this silly yearly licensing > fee system which is fine if you use it commercially....but for hobbyists its > a little excessive. > > Any help would be appreciated. > > Regards > > Peter Elliot > >
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