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Hello, This post might be a little bit off-topic, but I know that many people i this group have been beating their head on PCI for a while, so I may get an answer to my question... I'm using Virtex fpga on a PLX9080 based PCI board. My driver uses the PLX SDK. I'm trying to perform Slave DMA transfer to get decent IO performance, however I can't get more than 30Mbytes/sec on my PIII 600 with DMA size of 40kb (PCI->Local Bus). I've been trying to play around with the various DMA configuration registers without success, besides i've implemented a simple spy (counting successive write operation) on my FPGA and it seems that almost no data burst occur during DMA transfer ... Any help or explanation would be greatly appreciated. Thanks StevenArticle: 23101
Most FPGA suppliers (inc. Altera/ Xilinx) have pages with DSP app's notes etc. which should provide some good intro information. "Heinrich Fonfara" <fonfarah@ibmt.fhg.de> wrote in message news:39474395.A68BC205@ibmt.fhg.de... > Could someone please tell me a source for information about filter > design > with FPGAs, especially simple filters that don`t need any multiplication > > (e.g. comb filter, sinc filter)Article: 23102
> I'm using Virtex fpga on a PLX9080 based PCI board. My driver uses the > PLX SDK. If you did not re-write your driver, the PLX driver does double buffering, which is slow. Are you using NT? > I'm trying to perform Slave DMA transfer to get decent IO performance, What is slave DMA? The PLX chip can become a PCI bus Master, which is what you want, I would assume. >... and it seems that > almost no data burst occur during DMA transfer ... It sounds to me like you are doing programmed I/O (Target), not first party DMA (your board is a PCI Master), or your latency timer is not setup correctly...Article: 23103
> I have designed some fast multiipliers > in vhdl. I have synthesized both the pipelined > and the non pipelined (without pipeling) > version of fast multipliers.But What I found out after pipelining > my design and then synthesizing it the delay > had reduced by 6ns, which instead should have > increased because of pipelined registers which > I have added. If I read this correctly I think the 'delay' figure you are quoting refers to the delay between one Register and the next (i.e. the delay through any combinatorial logic). Therefore the pipelined version of the multiplier (or indeed any design) should have a reduced delay, although it will take additional clock cycles to produce any data. This is the reason for introducing pipelining. HTH -- To reply replace NOSPAM with BAESYSTEMS __________________________________ David Gilchrist Developement Engineer BAE SYSTEMSArticle: 23104
Bob Perlman wrote in message <39470fe4.39047497@news.ncal.verio.com>...
>On Tue, 13 Jun 2000 22:32:44 -0400, "Robert L. Metcalf"
><rlm@kauai.mv.com> wrote:
>
>>http://cgi.ebay.com/aw-cgi/eBayISAPI.dll?ViewItem&item=357196271
>>
>
>Golly, bidding starts at $5k...what a bargain!
I would imagine that's why Ray used http://www.fpga-guru.com/
note the hyphen.
eBay is evil. just say no.
--
-----------------------------------------
Andy Peters
Sr Electrical Engineer
National Optical Astronomy Observatories
950 N Cherry Ave
Tucson, AZ 85719
apeters (at) noao \dot\ edu
"A sufficiently advanced technology is indistinguishable from magic"
--Arthur C. Clarke
Article: 23105This is a multi-part message in MIME format. --------------356CEC21F8BB6615EE5A328C Content-Type: text/plain; charset=us-ascii Content-Transfer-Encoding: 7bit As far as I know, it is only availible in HTML at http://toolbox.xilinx.com/docsan/2_1i There is also the brand new 3.1i version at, you guessed it, http://toolbox.xilinx.com/docsan/3_1i Good luck. -- Brian Domagoj wrote: > Hi, > I was looking there for a new library guide pdf, but couldn't find it. > Is it available at all ?? > > -- > > ------------------------------------------- > - Domagoj - > - Domagoj@engineer.com - > ------------------------------------------- > Utku Ozcan <ozcan@netas.com.tr> wrote in message > news:394673E8.8C22A74B@netas.com.tr... > > > [snip] > > > 3. How to use the LUT as shift reg. > > > > Please look at SRL16 and SRL16E element in the Libraries Guide. > > For more info, Alliance or Foundation 2.1i Java-based document > > interface on http://support.xilinx.com and go to Software Manuals. > > > > Utku > > > > -- > > I feel better than James Brown. > > > > > > --------------356CEC21F8BB6615EE5A328C Content-Type: text/x-vcard; charset=us-ascii; name="brian.philofsky.vcf" Content-Transfer-Encoding: 7bit Content-Description: Card for Brian Philofsky Content-Disposition: attachment; filename="brian.philofsky.vcf" begin:vcard n:Philofsky;Brian tel;work:1-800-255-7778 x-mozilla-html:TRUE url:http://www.xilinx.com org:Xilinx, Inc.;Software Marketing adr:;;2100 Logic Dr.;San Jose;CA;95124;USA version:2.1 email;internet:brianp@xilinx.com title:Technical Marketing Engineer fn:Brian Philofsky end:vcard --------------356CEC21F8BB6615EE5A328C--Article: 23106
Austin Franklin wrote: > > I'm using Virtex fpga on a PLX9080 based PCI board. My driver uses the > > PLX SDK. > > If you did not re-write your driver, the PLX driver does double buffering, > which is slow. Are you using NT? I use NT, to perform the DMA, I use the physically contiguous memory buffer provided by the function PlxPciCommonBufferGet Since the physical address for this buffer is given, this is the one I use for programming the plx DMA controler. The "double buffering" is hence handled in my program which copy the appropriate data into this buffer. > > I'm trying to perform Slave DMA transfer to get decent IO performance, > > What is slave DMA? The PLX chip can become a PCI bus Master, which is what > you want, I would assume. Sorry, my explanation were not very clear. In my case, the plx chip is programmed form the PCI/host side (not the FPGA side) to start a DMA transfer as a busmaster to perform PCI to local bus DMA. Strangely, I have 30Mb when doing PCI to Local bus DMA, but I can reach 60Mb when doing Local to PCI (still with PLX as busmaster). > > >... and it seems that > > almost no data burst occur during DMA transfer ... > > It sounds to me like you are doing programmed I/O (Target), not first party > DMA (your board is a PCI Master), or your latency timer is not setup > correctly... I have 0x40 as value in my PCI latency timer register. However, changing its value does not affect performance... Thank you again ... StevenArticle: 23107
Hi, Using Maxplus-II to do output delay timing estimation for a given design gives a value of something like 16ns .... on the actual chip it's more like 7ns ... is the 16ns an absolute maximum and what I'm getting is a typical value? Unfortunately I need more that 7ns delay .. I could clock the outputs with negedge clock, and hope that I always get 7ns ... but if I start getting 16ns then I'm back in trouble ... any ideas? Cheers, Gary Cook.Article: 23108
--------------20B08CD3EBAFC30885C58E93 Content-Type: text/plain; charset=us-ascii Content-Transfer-Encoding: 7bit Actually, neither was taken when I got mine. I put the hyphen in there to make it more readable. Now I'm thinking maybe I should have taken both (it certainly ain't worth $5K) Andy Peters wrote: > Bob Perlman wrote in message <39470fe4.39047497@news.ncal.verio.com>... > >On Tue, 13 Jun 2000 22:32:44 -0400, "Robert L. Metcalf" > ><rlm@kauai.mv.com> wrote: > > > >>http://cgi.ebay.com/aw-cgi/eBayISAPI.dll?ViewItem&item=357196271 > >> > > > >Golly, bidding starts at $5k...what a bargain! > > I would imagine that's why Ray used http://www.fpga-guru.com/ > > note the hyphen. > > eBay is evil. just say no. > > -- > ----------------------------------------- > Andy Peters > Sr Electrical Engineer > National Optical Astronomy Observatories > 950 N Cherry Ave > Tucson, AZ 85719 > apeters (at) noao \dot\ edu > > "A sufficiently advanced technology is indistinguishable from magic" > --Arthur C. Clarke -- -Ray Andraka, P.E. President, the Andraka Consulting Group, Inc. 401/884-7930 Fax 401/884-7950 email ray@andraka.com http://www.andraka.com or http://www.fpga-guru.com --------------20B08CD3EBAFC30885C58E93 Content-Type: text/html; charset=us-ascii Content-Transfer-Encoding: 7bit <!doctype html public "-//w3c//dtd html 4.0 transitional//en"> <html> Actually, neither was taken when I got mine. I put the hyphen in there to make it more readable. Now I'm thinking maybe I should have taken both (it certainly ain't worth $5K) <p>Andy Peters wrote: <blockquote TYPE=CITE>Bob Perlman wrote in message <39470fe4.39047497@news.ncal.verio.com>... <br>>On Tue, 13 Jun 2000 22:32:44 -0400, "Robert L. Metcalf" <br>><rlm@kauai.mv.com> wrote: <br>> <br>>><a href="http://cgi.ebay.com/aw-cgi/eBayISAPI.dll?ViewItem&item=357196271">http://cgi.ebay.com/aw-cgi/eBayISAPI.dll?ViewItem&item=357196271</a> <br>>> <br>> <br>>Golly, bidding starts at $5k...what a bargain! <p>I would imagine that's why Ray used <a href="http://www.fpga-guru.com/">http://www.fpga-guru.com/</a> <p>note the hyphen. <p>eBay is evil. just say no. <p>-- <br>----------------------------------------- <br>Andy Peters <br>Sr Electrical Engineer <br>National Optical Astronomy Observatories <br>950 N Cherry Ave <br>Tucson, AZ 85719 <br>apeters (at) noao \dot\ edu <p>"A sufficiently advanced technology is indistinguishable from magic" <br> --Arthur C. Clarke</blockquote> <p>-- <br>-Ray Andraka, P.E. <br>President, the Andraka Consulting Group, Inc. <br>401/884-7930 Fax 401/884-7950 <br>email ray@andraka.com <br><A HREF="http://www.andraka.com">http://www.andraka.com</A> or <A HREF="http://www.fpga-guru.com">http://www.fpga-guru.com</A> <br> </html> --------------20B08CD3EBAFC30885C58E93--Article: 23109
The old xilinx intro course had a calculator as the lab project. You might contact xilinx to see about getting a copy of that and to determine if there is any licensing issues. As I recall there were versions for the then new 4000 family as well as for the 3000 family. laurent wrote: > Hello, > > I'm looking for a calculator programmed in FPGA to give to my students. > > I don't have time to do it. > Thank u for your help > > Laurent. > > =-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=- > Article poste via Voila News - http://www.news.voila.fr > Le : Wed Jun 14 12:58:06 2000 depuis l'IP : gtr305p3.unice.fr [VIP 3556928] -- -Ray Andraka, P.E. President, the Andraka Consulting Group, Inc. 401/884-7930 Fax 401/884-7950 email ray@andraka.com http://www.andraka.com or http://www.fpga-guru.comArticle: 23110
Hello Everyone,
I am extremely interested in partial
dynamic reconfiguration of FPGAs. If anyone
out there has knowledge of systems (particularly
Virtex based) that reconfigure parts of the FPGA
to accomplish different tasks at different points
in system operation I would be glad to hear
about it. I have seen the XILINX ap notes on
the subject and have read of the CAL and XC6
series parts/projects, so we can skip info on these.
Thank you.
Sincerely,
Alex :)
Article: 23111We have done a considerable amount of work considering these parts and applications (no actual implementations however. We would LIKE to use this functionality on a student board which is slowly being developed), but the big weakness right now is in the tools. There needs to be a mechanism to lock down an interface on a vertical column, with the two halves of the design placed and routed separately. There keeps being talk of the ability to construct a DMZ (Demilitarized zone), a vertical slice, beyond which, the tools will not place or route, so that you can design half a chip, locked into a series of luts for the interface, without having the router or placer place things on the wrong side of the DMZ. Then it is a matter of chopping up the bitfile and only loading the secotions you need from that portion of the design. The problem right now lies in the tools not supporting even this basic functionality to perform partial reconfiguration in a design. -- Nicholas C. Weaver nweaver@cs.berkeley.eduArticle: 23112
I'm trying to program a single Xilinx FPGA 5210 in asynchronous peripheral mode (without using the JTAG pins). I don't completely understand the PROGRAM pin's role in the configuration. Is it toggled low, then brought high before configuration, and stays high throughout configuration? Or is it brought low and stays low throughout configuration? Or do I just leave it high throughout configuration and don't bother toggling it at all?Article: 23113
James Young wrote: > I'm trying to program a single Xilinx FPGA 5210 in asynchronous peripheral > mode (without using the JTAG pins). I don't completely understand the > PROGRAM pin's role in the configuration. <snip> Or do I just leave > it high throughout configuration and don't bother toggling it at all? Yes, this last option. You only need to bother about PROG when you want to reconfigure the FPGA while maintaining Vcc. And PROG is then the only way to achieve reconfigurtion. Peter Alfke, Xilinx ApplicationsArticle: 23114
> Austin Franklin wrote: > > > > I'm using Virtex fpga on a PLX9080 based PCI board. My driver uses the > > > PLX SDK. > > > > If you did not re-write your driver, the PLX driver does double buffering, > > which is slow. Are you using NT? > > I use NT, to perform the DMA, I use the physically contiguous > memory buffer provided by the function PlxPciCommonBufferGet > > Since the physical address for this buffer is given, this is the one > I use for programming the plx DMA controler. The "double buffering" > is hence handled in my program which copy the appropriate data into this > buffer. We found the PLX driver to not come close to providing the performance we needed, so we re-wrote it, to not double buffer (which was not an easy task, BTW)...since we had to stream data, and the double buffering really slowed things down. > > > I'm trying to perform Slave DMA transfer to get decent IO performance, > > > > What is slave DMA? The PLX chip can become a PCI bus Master, which is what > > you want, I would assume. > > Sorry, my explanation were not very clear. > In my case, the plx chip is programmed form the PCI/host side (not the FPGA > side) to > start a DMA transfer as a busmaster to perform PCI to local bus DMA. > > Strangely, I have 30Mb when doing PCI to Local bus DMA, but I can reach 60Mb > when doing Local to PCI (still with PLX as busmaster). That's not untypical, believe it or not. Sounds to me like you need to look at the PCI bus with a logic analyzer to see what is happening. I wish I could give you a one line 'ta da' fix... Do you know that your back end can keep up with the PCI bus? I'll look over our NT driver and see if there is anything obvious that I can come up with that might cause the problem you are having...Article: 23115
I am a new user to the XILINX F1.5, I am currently trying to run a simple project and I am in the implementation phase of the design, when I go to compile my schematic that is targeted for the XILINX 4005XL technology, its gets to the Place and Route stage and just runs and runs, for laughs I let it run for over two hours and it was still running, I have tried everything to minimze PAR times, I am not using the heartbeat indicator either. The program is not hanging up, it is just running to no end. I also went ahead and used the system monitor to see how much CPU is being used, it is using 100% of my pIII733. Is this normal? or am I doing something wrong, or is there something in the configuration that I need to set or unset???????? Please help, I am totally perplexed!!!Article: 23116
I've seen similar effects using the AMCC PCI chips. My best guess is that it is something to do with the bridge controller between the PCI bus and Local bus. I note that performance is much better running under DOS than NT, so I guess that what may be happening is that the bus bridge is giving priority to cache 'refills'. NT has a much bigger 'idle loop' than DOS, so consequently needs much more cache refill activity, which translates into less available bandwidth for everyone else ... If you look at the PCI bus signals with a scope (digital) you will easily get a general picture of what is going on - you don't need a logic analyser at this level. regards Dave Austin Franklin <austin@darkr88oom.com> wrote in message news:01bfd63f$9eb72670$250bf7a5@drt1... > > Austin Franklin wrote: > > > > > > I'm using Virtex fpga on a PLX9080 based PCI board. My driver uses > the > > > > PLX SDK. > > > > > > If you did not re-write your driver, the PLX driver does double > buffering, > > > which is slow. Are you using NT? > > > > I use NT, to perform the DMA, I use the physically contiguous > > memory buffer provided by the function PlxPciCommonBufferGet > > > > Since the physical address for this buffer is given, this is the one > > I use for programming the plx DMA controler. The "double buffering" > > is hence handled in my program which copy the appropriate data into this > > buffer. > > We found the PLX driver to not come close to providing the performance we > needed, so we re-wrote it, to not double buffer (which was not an easy > task, BTW)...since we had to stream data, and the double buffering really > slowed things down. > > > > > I'm trying to perform Slave DMA transfer to get decent IO > performance, > > > > > > What is slave DMA? The PLX chip can become a PCI bus Master, which is > what > > > you want, I would assume. > > > > Sorry, my explanation were not very clear. > > In my case, the plx chip is programmed form the PCI/host side (not the > FPGA > > side) to > > start a DMA transfer as a busmaster to perform PCI to local bus DMA. > > > > Strangely, I have 30Mb when doing PCI to Local bus DMA, but I can reach > 60Mb > > when doing Local to PCI (still with PLX as busmaster). > > That's not untypical, believe it or not. > > Sounds to me like you need to look at the PCI bus with a logic analyzer to > see what is happening. I wish I could give you a one line 'ta da' fix... > Do you know that your back end can keep up with the PCI bus? > > I'll look over our NT driver and see if there is anything obvious that I > can come up with that might cause the problem you are having... > >Article: 23117
In article <3947BC37.7EA12C30@sonyoxford.co.uk>, Gary Cook <gc@sonyoxford.co.uk> wrote: > Hi, > > Using Maxplus-II to do output delay timing estimation for > a given design gives a value of something like 16ns .... on the > actual chip it's more like 7ns ... is the 16ns an absolute > maximum and what I'm getting is a typical value? > > Unfortunately I need more that 7ns delay .. I could clock > the outputs with negedge clock, and hope that I always get > 7ns ... but if I start getting 16ns then I'm back in trouble ... > any ideas? > > Cheers, > > Gary Cook. 2 Questions and then perhaps others and myself can give some ideas: 1) Which family (10K,3K, etc?) is your design in? 2) Why does your system WANT a delay in the clock to out? In general, you always seek to minimize this number. And it sounds like you are seeing the difference between typical and worst case temperature/process. > > Sent via Deja.com http://www.deja.com/ Before you buy.Article: 23118
I don't have any answers for that, I just want to add what I have seen with XSE 1.5 PAR. My xilinx student edition PAR works good on my celeron 300A, with 128 meg of RAM until I decided to put some costraints for the pins, when I got the XSBoard. It tried for over two hours to implement the design, and din't pass the PAR stage. When I removed the pin costraints (like input1 is pin 45 etc) the PAR was fast enough. I 've tried to PAR some student-size projects, and it's working ok, bu without any pin constraints. The only time I tried to put constraints, in terms of pin locations, it didn't succeed. The project was just a full adder (1bit), to test my brand new XSboard! When I removed one of the pin costraints, it placed it where I wanted, and completed PAR in reasonable time! Abdar Kerpal <me@somewhere.com> wrote in message news:nrqfkso00ap5oabn6qqh6rcf8be2lq5gg0@4ax.com... > I am a new user to the XILINX F1.5, I am currently trying to run a > simple project and I am in the implementation phase of the design, > when I go to compile my schematic that is targeted for the XILINX > 4005XL technology, its gets to the Place and Route stage and just runs > and runs, for laughs I let it run for over two hours and it was still > running, I have tried everything to minimze PAR times, I am not using > the heartbeat indicator either. The program is not hanging up, it is > just running to no end. I also went ahead and used the system monitor > to see how much CPU is being used, it is using 100% of my pIII733. Is > this normal? or am I doing something wrong, or is there something in > the configuration that I need to set or unset???????? Please help, I > am totally perplexed!!!Article: 23119
In article <XNG%4.6388$uj6.340332@news1.rdc1.on.wave.home.com>, "John Smith" <jsmith@home.com> wrote: > Hi > > What are the differences (if any) between an fpga and an epld? > Assuming this is a real question I'll go ahead and give a brief answer. I'm sure this is in a FAQ somewhere. In general FPGA's have higher density than EPLD's. ELPDs are good at high speed state machines while FPGA's are better at datapath operations. EPLD's are commonly non-volitile, while FPGA's often are. EPLD's often have high current requirements even with no clock, while FPGA's often have only leakage currents (uA's) with no clock. Cheers! Sent via Deja.com http://www.deja.com/ Before you buy.Article: 23120
I don't have any answers for that, I just want to add what I have seen with XSE 1.5 PAR. My xilinx student edition PAR works good on my celeron 300A, with 128 meg of RAM until I decided to put some costraints for the pins, when I got the XSBoard. It tried for over two hours to implement the design, and din't pass the PAR stage. When I removed the pin costraints (like input1 is pin 45 etc) the PAR was fast enough. I 've tried to PAR some student-size projects, and it's working ok, bu without any pin constraints. The only time I tried to put constraints, in terms of pin locations, it didn't succeed. The project was just a full adder (1bit), to test my brand new XSboard! When I removed one of the pin costraints, it placed it where I wanted, and completed PAR in reasonable time! Abdar Kerpal <me@somewhere.com> wrote in message news:nrqfkso00ap5oabn6qqh6rcf8be2lq5gg0@4ax.com... > I am a new user to the XILINX F1.5, I am currently trying to run a > simple project and I am in the implementation phase of the design, > when I go to compile my schematic that is targeted for the XILINX > 4005XL technology, its gets to the Place and Route stage and just runs > and runs, for laughs I let it run for over two hours and it was still > running, I have tried everything to minimze PAR times, I am not using > the heartbeat indicator either. The program is not hanging up, it is > just running to no end. I also went ahead and used the system monitor > to see how much CPU is being used, it is using 100% of my pIII733. Is > this normal? or am I doing something wrong, or is there something in > the configuration that I need to set or unset???????? Please help, I > am totally perplexed!!!Article: 23121
Hi, Can somebody give me an example of FIFO design with width >1 ? If it is parameterizable, even better. VHDL is preferable, but Verilog is fine too. regards, Dave. Sent via Deja.com http://www.deja.com/ Before you buy.Article: 23122
Dude, thats what is was, I have the Practical Xilinx Designer Lab Book by David Vanden Bout, pretty good book, and I was following the first design project, as soon as I took off those pin constraints the program flew through the PAR stage, I must email Dave and find out why that happens when trying to put pin constraints on a design. I too have the XS board. Thanks for your help, it was very much appreciated! On Thu, 15 Jun 2000 00:16:34 +0300, "Goulas George" <ggoulas@x-treme.gr> wrote: >I don't have any answers for that, I just want to add what I have seen >with XSE 1.5 PAR. > >My xilinx student edition PAR works good on my celeron 300A, >with 128 meg of RAM until I decided to put some costraints for >the pins, when I got the XSBoard. It tried for over two hours to >implement the design, and din't pass the PAR stage. When I removed >the pin costraints (like input1 is pin 45 etc) the PAR was fast enough. >I 've tried to PAR some student-size projects, and it's working ok, >bu without any pin constraints. >The only time I tried to put constraints, in terms of pin locations, it >didn't succeed. The project was just a full adder (1bit), to test my >brand new XSboard! When I removed one of the pin costraints, it >placed it where I wanted, and completed PAR in reasonable time! > >Abdar Kerpal <me@somewhere.com> wrote in message >news:nrqfkso00ap5oabn6qqh6rcf8be2lq5gg0@4ax.com... >> I am a new user to the XILINX F1.5, I am currently trying to run a >> simple project and I am in the implementation phase of the design, >> when I go to compile my schematic that is targeted for the XILINX >> 4005XL technology, its gets to the Place and Route stage and just runs >> and runs, for laughs I let it run for over two hours and it was still >> running, I have tried everything to minimze PAR times, I am not using >> the heartbeat indicator either. The program is not hanging up, it is >> just running to no end. I also went ahead and used the system monitor >> to see how much CPU is being used, it is using 100% of my pIII733. Is >> this normal? or am I doing something wrong, or is there something in >> the configuration that I need to set or unset???????? Please help, I >> am totally perplexed!!! > > > > >Article: 23123
Goulas George wrote: > <snip> > My xilinx student edition PAR works good on my celeron 300A, > with 128 meg of RAM until I decided to put some costraints for > the pins, when I got the XSBoard. It tried for over two hours to > implement the design, and din't pass the PAR stage. When I removed > the pin costraints (like input1 is pin 45 etc) the PAR was fast enough. Do you have a time for 'fast enough' ? Mins, secs ? > I've tried to PAR some student-size projects, and it's working ok, > but without any pin constraints. > The only time I tried to put constraints, in terms of pin locations, it > didn't succeed. The project was just a full adder (1bit), to test my > brand new XSboard! When I removed one of the pin costraints, it > placed it where I wanted, and completed PAR in reasonable time! Do you mean the constraints on just one pin location, or something like a global delay param ? This slowdown with pin-locking would be a concern, as once a PCB design is done, you want to lock the pins for future iterations. Maybe some more numbers are needed ? NomGATES % used of ??Device TimeLocked TimeNotLockedArticle: 23124
In article <8F51E72E1shivawellcom@207.126.101.100>, shiva@well.com (Kenneth Porter) wrote: > [posted and mailed] Mailed? To whom? Oh well, no matter... > I want to deploy a very simple JTAG in-circuit programmer for the > Altera MAX 7128A in my production department. The Windows version > available for free download from Altera's site (Altera Stand-Alone > Programmer, http://www.altera.com/html/tools/asap2.html) looks too > fancy for simple blasting of a fixed file. I'd like my production > people to be able to simply click on a shortcut and have a canned file > pumped into the chips on my board. Is anything available to do this? > Can I customize the Altera program to do this? I don't want to open the > program to allow the user choice of file to blast. The Jam player will do that. I forget the URL, but it's easy to find on Altera's web site. -- Steve Rencontre http://www.rsn-tech.demon.co.uk //#include <disclaimer.h>
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