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Is it normal to have 200 ohms resistance between TCLK and TMS and between TCLK and TDI pins directly on the chip? I saw that those pins influence each other because the programmer's pins can't get enough current on IC's pins (the programmer works well alone) and I didn't see anything special that could make a short on the board. anybody knows why thanks in advance Simon "G. Hobson Frater" <hobson.frater@xilinx.com> wrote in message news:395D4D14.B5958F6C@xilinx.com... > Simon, > > If you haven't already, you might want to check the Xilinx Answers database at > http://support.xilinx.com. In the Answers Search Field try typing something > like " bit position '0' ". Answer record #2881 may help. > > -Hobson > Xilinx Applications > > Simon Bilodeau wrote: > > > Hi, > > > > i<m new in ISP with CPLD and i have an error uploading a version in my CPLD. > > Every connection seems do be ok but i always get that error... > > > > Any idea? > > > > Log file : > > > > Loading Boundary-Scan Description Language (BSDL) file > > 'C:/Fndtn/xc9500/data/xc95288.bsd'.....completed successfully. > > Checking boundary-scan chain integrity...ERROR:JTag - Boundary-scan chain > > test failed at bit position '0' on instance 'projet24(Device1)'. > > Check that the cable, system and device JTAG TAP connections are correct, > > that the target system power supply is set to the correct level, > > that the system grounds are connected and that the parts are properly > > decoupled. > > ERROR:JTag - Boundary scan chain has been improperly specified. Please > > check your configuration and re-enter the boundary-scan chain information. > > Boundary-scan chain validated unsuccessfully. > > ERROR:JTag - : The boundary-scan chain has not been declared correctly. > > Verify the syntax and correctness of the device BSDL files, correct the > > files, > > reset the cable and retry this command. >Article: 23726
Hi, I'm working with a XILINX XC40250XV and I have following problem: There is an signal input port and a internal clock should be generated from this signal. How can I push synopsis to create the internal clock buffer for this internal clock automatically. Is there at all a way to say "synopsis do this". KaiArticle: 23727
Try http://www.embeddedsol.com/technology/info_sheets/info_sheet_02.htm Cheers John Frederic Magniette wrote: > Dear gentle persons, > I'm searching for a PCI board to make material accelerators for Linux. > Do you know some of this kind of board? > I thank you by advance > fredericArticle: 23728
Hi! i was wondering if anyone knows the file name, which icludes the IBIS model fot the XCV400E chip... thanx, johnny,Article: 23729
I've been interested in evaluating the free versions of Leonardo and FPGA Express that Alera have been promising for the last few months and so have been keeping an eye on their web site. Initially this was announced early this year as being "available in May". Nothing happened, there was no sign of any software then mid May the text mysteriously changed to "available in June". It's not approaching mid July guess what ..... What's going on Altera? Why the promises and no delivery? Nial Stewart.Article: 23730
Phil, Thanks for the fine treatise on LUT usage for simulation and mapping. I am saving your summary in case I need to explain it to some CAE guy in the future. To be honest I just got lucky on the edifatts.cfg thing but now I really understand how the @INIT and INIT attributes are used. The first for simulation and the second for mapping. Unfortunately I still have some work to do. My viewgen'ed schematics only have the @INIT attribute. If I try to compile them into design, they will be mapped incorrectly. Maybe I can talk Synplicity into putting both attributes into the original edif netlist.Article: 23731
I'm impressed Philip. You have a lot of stamina!!! What would it take to get the EQN to simulate? That is, what would the vendor need to do? Not that I am planning on ringing anyone's phone to ask them to do it. But would this require a Viewlogic change to Viewsim and/or VSM? I take it that VSM outputs a Viewlogic specific netlist? I'll review my Viewlogic 101 notes. Let's see, there are WIR files and SCH files and SYM files. I know that WIR files are generated when you "check" a schematic. Ah... there it is, VSM makes a... .vsm file! So I guess the EQN would need to be supported by VSM (perhaps translated to gates!!?) and maybe also Viewsim. Hmmm... since these are all text files (nice to have an open format, eh?) The EQN to @INIT string could be done by a separate program, no? Let VSM generate the .vsm file and then use another program to translate the EQN parameter in the VSM file, or if it doesn't get there, read it from the WIR file. Philip Freidin wrote: > > Sometimes the issues are complex. > Sometimes the complexity of a CAE problem is exacerbated by multiple vendors. > Sometimes the documentation sucks, or just doesn't exist. > Sometimes the dependencies are undocumented or obscure. > Sometimes the expected results of a workaround are disappointing. > > ... and then there are LUTs in the netlist. > > This long winded post is of interest to you only if you use most of : > > ViewSim > ViewDraw > M2.1i / M3.1i > Virtex (and Spartan II probably) > Synthesis > > Buried in this message is info on simulating Virtex LUTs from > deconstructed synthesis, as well as how to create designs with equations > on your LUTs on your scematics, and how to use LUTs on your schematics > for both simulation and generating a netlist that PAR processes the way > you expect. Unlike my normal posts, this one is almost attitude free. > > The original request for help on the original thread was about the > challenge of simulating with ViewSim, a Virtex design that included some > schematic and synthesis generated logic. > > >Viewlogic schematic from Synplify edif output? > > > >Hello All, I use a mixed design entry style where I do most of the work in > >Viewlogic schematics but through in a few key VHDL behaviors. After I am > >satisfied with my simulation I synthesize those VHDL blocks using Synplify. > >What I would like to do is convert the synthesized netlists into schematics > >for viewing. In the past we used Exemplar for synthesis and we could run the > >net lists through edifneti and viewgen to get a machine generated schematic. > >Now we use Synplicity which puts LUT4, LUT3 and LUT2 primitives into the > >netlist. These components are from the virtex library and do not have > >simulation models. I've found that Xilinx provides two utilities, ngdbuild > >and ngd2edif, that can be used to produce a simulatable edif netlist. The > >resulting netlist from this path contains x_lut4, x_lut3 and x_lut2 cells > >from the SIMPRIMS library. Unfortunately these cells do not show up in the > >SIMPRIMS library so I cannot generate the schematic. Can anyone tell me how > >to generate a Viewlogic schematic from Synplify edifoutput? Thanks for any > >advice. > >Pete Dudley > > There were some off target answers that unfortunately mixed up the LUT > primitives with FMAP primitives. The thread survived anyway. > > >Simon: > >Nope. The LUTs have attributes attached which correspond to the LUT SRAM > >contents and thus define the LUT logic. > > Rick Collins then asked for: > > >That would be useful as a schematic primative. I have always preferred > >to think in terms of LUTs. At one time back when Viewlogic was as DOS > >program, they supported a way of passing parameters into a lower module. > >I had defined a module which was in essense the 4 input LUT complete > >with the programmable configuration bit. The parameter defined the bit > >pattern and I had a 4 input LUT that would place and simulate. But for > >some reason when they converted to Windows, these modules ceased to > >function. > > The problem was that the netlister for Viewdraw was changed, and the > developer for the replacement was uninterested in supporting parameter > substitution, given how few users were using it. Also, the developer > "just didn't get it". (it is also quite hard to get it right. It took > several years to get WIR2XNF to do this correctly) > > >If they don't have a schematic symbol for the simulation primatives, can > >you add them to the library? Or are the libraries uneditable? > > The libraries are editable, but you can't make simulation primitives out > of thin air. Only Viewlogic can do that. A bunch of people petitioned > Xilinx and Viewlogic to fix this problem with the basic simulation of > Virtex schematics about 2 years ago, and the result is that new libraries > were created, and updates were made to ViewSim and the EDIF netlister. See > below for details of where to get it. As a side effect of this begging > procedure, we also got them to add suport for simulating ROMs without > having to use the LOADM command. The new library includes support for > simulation of ROMs and initialized RAMs. And the initialization (which are > attributes on the symbols on your schematics) also are (almost) passed > through to PAR, and generate the right stuff too. Could life be any better > you might ask. > > >This is the type of problem that make people want open source tools. > >They get tired of being told how to design and what tools to use. > > Oh so true, but then we wouldn't get any work done at all, and we'd be > the CAE vendors everyone would be complaining about. > > So let's get back to the original problem. > > The problem is that Viewsim is a gate level simulator, and so can't > simulate the synthesis section of a design. (Innoveda does have a product > called Digital Fusion, that allows simulation of any mix and nesting of > schematics, Verilog, and VHDL, but this article is for those who only > have ViewSim.) > > I then tried a brief, on topic answer but strayed into schematic-only stuff: > > >Philip Freidin > >The latest version of ViewSim, and the latest version of the Virtex > >libraries are supposed to be able to simulate ROMs with init=xxxx > >attributes attached. This was fixed about 6 months ago. No announcement > >was made, so you just needed to trip over the updates. > > > >If you go into the most current Viewlogic Viewdraw Virtex library, > >and look at the LUT4 symbol, you will see a default @init="0000" > > > >Push down and you will find a simulation model to match. > > > >There is probably a way to get from where you are to where you want to be, > >given the above info. I haven't done it, and I suspect it will take a bit > >of screwing around to get it right. For instance, I had a play with this > >stuff a few months ago, and to get the init to work, and set the value to > >8000, I had to overide the default to @init=8000 and attach another > >attribute init=8000 to both get it to simulate and to generate the chip I > >wanted. > > More on this soon. > > >I believe this is a bug in the library definition, but I am burntout > >with trying to get Xilinx to care about the quality of this stuff. > > Obviously not burnt out enough. 5 hours of screwing around and now I feel > like posting again. The library definition is sort of OK, what is missing > is sufficient documentation to make it work. I believe this can't have > been tested at Xilinx, because the problem is obvious. If you use the LUT > symbol as supplied, you can't get through the ngdbuild without an error. > This is relevant for a schematic-only design, that uses LUTs. > > >At least they eventually added support for Virtex for Viewdraw/Viewsim > >users. (this init stuff also should work with the SRL16 > >and block RAMS too) > > plus a followup: > > >http://support.xilinx.com/techdocs/5968.htm > > Rick Collins showed appreciation: > > >Thanks a lot. This can save a lot of trouble when you want to closely > >control the mapping and placement of a function. The old way of using > >gates and a FMAP was just so clunky. I will never understand why Xilinx > >always wants to tell its users how they should do design. > > Well, actually, I rather liked it, since I still got to specify my logic > exactly the way I wanted it (with gates), and the FMAPs lets me directly > control the clustering. > > >Now if I can just get them to let me enter a single equation for the LUT > >instead of having to calculate the hex contents myself. > > Oooooh, just you wait ..... > > Simon steps up to the plate: > > >You could add the equation as an attribute, then write a small > >program to scan the EDIF and convert the equation to an INIT. > >This would still leave the simulation to be dealt with... > > Which in fact is what Don Husby (Our token Lucent user) did back > in November 1994, and made it available . Written in awk. > > Rick Collins: > > >Or am I missing something. Does the simulation work on something other > >than the EDIF file? > > In the schematic only flow there are several issues: > 1) Can I just run VSM on my design and then run ViewSim on the result, > without running any Xilinx tools. > 2) Can I take the same schematic database and generate a netlist for the > Xilinx tool chain, that will build the same design > > Don's program post processed a netlist that had EQN and ROM symbols in it > and created a new netlist that had the EQN/ROMs replaced with gates. This > was then acceptable to the P&R tools of the time (pre Mx.1i stuff). So it > sort of supported issue 2, but not issue 1. > > If we then look at the original problem from Pete, we can add: > 3) If all I have is ViewSim, and I am also doing VHDL/Verilog, how do > I simulate it. I can get a netlist out of the xilinx tools that has > merged the HDL and schematic together, but it has these darn LUT symbols > in it. How do I get ViewSim to do something with this. > > Well it looks like I almost gave Pete an answer, by pointing him at the > new update for ViewSim, and the updated libraries from Xilinx, and the > super secret clue about there being both the @INIT and the INIT > attribute. Clearly he had to do some more work, but it would seem at > least his problem is now solved. The EDIF netlist that comes out of the > Xilinx tools has LUTs in it, and these LUTs have INIT attributes on them. > The last piece of the puzzle from him was discovering the EDIFATTS.CFG > file that can translate the INIT=xxxx into @INIT=xxxx that VSM/ViewSim > are going to need. > > Here is his praise, and additional info. > > Pete Dudley <padudle@sandia.gov> wrote: > >Phil, > > > >As usual, you hit the nail right on the head. Maybe I'm oldfashioned but I > >like to see the results of each synthesized block. Now I can get my post > >synthesis schematic into simulatable form. To do it I had to use the updated > >Virtex library from Xilinx and update the Viewlogic Fusion simulator and > >Viewlogic edif reader. I did the Viewlogic updates through the Webupdate > >utility but it was ten's of megabytes. > > > >In addition to all that, I had to add the line below to my edifatts.cfg > >file. > > > >INIT\=@INIT > > > > So why you might ask have I wasted your time with this ~340 line posting. > Well I thought it would be neat to explain exactly what was needed to get > Pete's simulation to run. And then there are the side effects of me > understanding how this all works, and the further work I did today. > > You see, I thought I should go back and understand why there was the > kludge of needing both @INIT and INIT on a schematic only design. And the > good news is I now know, and I also figured out how to get the EQN to > work too. > > So here is the info: > > In the new Virtex library, the LUTs, SRL16s, BRAMS, and ROMs all have > @INIT type attributes on them (some have it visible, some don't). Dozens > of symbols that have been carefully worked on by someone at Xilinx to > make this work. Pity they didn't document this hard work. > > The @ character is needed because that is the ONLY way to pass a value > through the hierarchy, to the lower level where the simulation primitives > live. Down at the lower level are the simulation primitives. These have > assignment statements on them like INIT_00=@INIT, which is how the > instance level attributes that you attach to the symbols get propagated > to the simulation primitive, that ViewSim actually simulates. > > The VSM program knows how to pass and assign these values. > > Although the default attribute on a symbol like LUT4 is @INIT="0000", > you can over ride it with your own. Here is how it is interpreted: > > @INIT="1234" 1234 > @INIT=1234 1234 > @INIT=FF00 FF00 > @INIT=FF FF00 > @INIT=F F000 > > Only hex specifcations. The MSB of the values is selected when all 4 > inputs to the LUT are '1' > > But here's a little problem. When you netlist this out to M2.1i/M3.1i, > with the EDIF netlist writer, what goes out to the netlist is the @INIT > attribute, just the way you wrote it. Unfortunately, this is not a valid > attribute for the Mx.1i tools. (By the way, the lowest level that goes > out to the netlist is the LUT4, not the simulation schematic below it, > since it is made up of primitives that are unknown to Xilinx P&R tools. > That's why you must set the 'Level=Xilinx M1' in the graphic user > interface, or if you are using the command line, the '-L Xilinx' option.) > > What Xilinx P&R needs are attributes that read 'INIT=1234' > > So I thought that since Pete solved his problem with the EDIFATTS.CFG file > and got it to rename the attributes ( his path is starting with EDIF (and > the EDIF netlist reader), and going back to Viewsim via WIR files and VSM) > I would try the same thing with the EDIF netlist writer. It turns out that > there is no equivalent capability that I can find. > > SO ... > > If you want to use LUTs or other initialized memory primitive, you need > to set both an attribute such as @INIT to the required value for > simulation to work, and an attribute named INIT for the netlister to > create an EDIF netlist that will be processed correctly by Mx.1i . > > For example , a LUT4 might have the following two attributes attached to it: > > @INIT=AA55 > and > INIT=AA55 > > You can also set these to differing values, and you will get what you > deserve. While this isn't ideal, it is not to much of a hardship. > > As promised, here is the bonus info: EQN > > While not documented in either M2.1i or M3.1i systems, you can also place > an attribute with a name of EQN on a LUT, instead of the INIT (but not > instead of the @INIT). This will be passed on to Mx.1i tools, and will > build the logic you want (assuming you were reasonable). > > Unfortunately what it wont do is simulate, because the @INIT can only be > set to a hexadecimal value. > > For example , a LUT4 might have the following two attributes attached to it: > > @INIT=8000 > and > EQN=I0*I1*I2*I3 > > Which would work for both. Unfortunately, figuring out the @INIT value > gets harder for more complex EQN values. The EQN can include I0 thru I3, > and the following operators: > > ~ NOT > * AND > @ XOR > + OR > (,) grouping / precedence > > So in summary: LUT4 can be simulated, and allows loading a LUT with a hex > value. > > Netlists that resulted from hybrid SCH/HDL can be simulated, > > EQN can be used to specify functionality, but simulation is a pain. > Either figure out the magic hex number, or go through the hybrid path, to > get the P&R software to give you the translated EQN to Hex conversion. > > Philip Freidin -- Rick Collins rick.collins@XYarius.com Ignore the reply address. To email me use the above address with the XY removed. Arius - A Signal Processing Solutions Company Specializing in DSP and FPGA design Arius 4 King Ave Frederick, MD 21701-3110 301-682-7772 Voice 301-682-7666 FAX Internet URL http://www.arius.comArticle: 23732
I am not as into this stuff as most of you guys, but I think we are talking about the same thing. I have never heard the name Innoveda before or forgotten it if I did. It seems like Viewlogic is sold off again every time I look. But Viewdraw/Viewsim/Viewotherstuff is what Lucent gives out as part of their starter kit. I think they charge about $100 for it, but they will give it away if you ask your FAE nicely and promise to do a design or two with it. Although I know one consultant who has three copies sitting on his shelf unopened. I guess they thought he might be a big account. BTW, I have not tried it yet, but I was told that the starter kit even includes VHDL. Philip Freidin wrote: > > Rickman <spamgoeshere4@yahoo.com> wrote: > > > >Yes, I think the Xilinx software is more mature. But then, Lucent is not > >trying to wean anyone off of schematics either! I like my Viewlogic!!! > > > > They support Viewlogic (Innoveda) !?!?!?! Wow, I'm changing now. > > Philip -- Rick Collins rick.collins@XYarius.com Ignore the reply address. To email me use the above address with the XY removed. Arius - A Signal Processing Solutions Company Specializing in DSP and FPGA design Arius 4 King Ave Frederick, MD 21701-3110 301-682-7772 Voice 301-682-7666 FAX Internet URL http://www.arius.comArticle: 23733
> QUESTIONS: > > 1.) How do you associate the CLB data that you read out of the FPGA with > the variables in your VHDL code etc? The .ll file that is generated has this info... Take care, >Asher< <<=>>=<<=>>=<<=>><<=>>=<<=>>=<<=>><<=>>=<<=>>=<<=>> Asher C. Martin <<=>>=<<=>>=<<=>><<=>>=<<=>>=<<=>><<=>>=<<=>>=<<=>> WORK ADDRESS: 1050 Lowater Road, Room 272 Chippewa Falls, WI 54729 (715) 726-4761 <<=>>=<<=>>=<<=>><<=>>=<<=>>=<<=>><<=>>=<<=>>=<<=>> asherm@cray.com http://www.uiuc.edu/~martin2/ <<=>>=<<=>>=<<=>><<=>>=<<=>>=<<=>><<=>>=<<=>>=<<=>>Article: 23734
http://www.xilinx.com/support/sw_ibis.htm unzip and enjoy. Check back often, as there are frequent updates on new products to improve the models from their original ultra conservative origins from simulation models Austin Johnny wrote: > Hi! > > i was wondering if anyone knows the file name, which icludes the IBIS model fot the XCV400E chip... > > thanx, > johnny,Article: 23735
Hello, Does anyone understand what the <offset>, <frame number>, <frame offset> means in .ll files? I do know that the offset should tell you where the variable is located in the readback bitstream but is this the BIT offset or what? If you have a frame number of say 10 and a frame offset of say 20 what would be the bit number? Should that equal the offset? Where is the documentation on .ll files? Take care, >Asher< <<=>>=<<=>>=<<=>><<=>>=<<=>>=<<=>><<=>>=<<=>>=<<=>> Asher C. Martin <<=>>=<<=>>=<<=>><<=>>=<<=>>=<<=>><<=>>=<<=>>=<<=>> WORK ADDRESS: 1050 Lowater Road, Room 272 Chippewa Falls, WI 54729 (715) 726-4761 <<=>>=<<=>>=<<=>><<=>>=<<=>>=<<=>><<=>>=<<=>>=<<=>> asherm@cray.com http://www.uiuc.edu/~martin2/ <<=>>=<<=>>=<<=>><<=>>=<<=>>=<<=>><<=>>=<<=>>=<<=>>Article: 23736
John McCluskey <john_mccluskey@hotmail.com> wrote: > Don, > Please don't give up on us just yet! :-) You'll be happy to know that when I came in this morning, my chip had routed and met the 100Mhz constraints. Unfortunately, to do this I had to spend 2 weeks beating it into submission. Only half of the problem was due to my delusion that I could implement a real design with generic VHDL. What I ended up with is a mess of structural VHDL which instantiates individual gates, flip-flops, and PFUs in order to get a sensible mapping and placement. The rest is due to problems with the Orca software. I think the biggest problem is with the large size of the PFU. From a hardware standpoint, I like the ability to pack 8 LUTS and 8 registers into a single PFU. But, it doesn't work well with the software which does mapping independently from the Place-and-Route. By packing so many functions into a single PFU, there is a much higher chance that the mapper will group signals that should be placed on opposite sides of the chip. The result will almost always be non-optimal until PAR can place individual LUTS and FFs independent of PFUs. And that doesn't seem likely, since the current software (9.4a) can't even swap signals within a PFU or SLIC. The chip has these nice wide metal busses. 20 long lines per row and 20 per column. Unfortunately, PAR can really only use 4 of them efficiently. This is because the mapper assigns signals to FFs and Tbufs by number (i.e. Dat[N] gets assigned to Tbuf T[N mod 8]) and PAR can't change this. So if you have two 4-bit tristate busses in the same column, only one of those busses can use the metal lines. If PAR could swap Tbufs within a SLIC, then it could route all 8 tristate signals on metal lines. Likewise, the chip has a well optimized path that can get an 8-bit bus from the longlines into 8 registers of a PFU. Oddly enough, PAR can't use that path because of the default mapping. Four of the bits can use that path, but the other 4 must use different paths that add 1-2 ns routing delay. The ability to swap FFs would fix this problem. Even changing the default mapping would be a simple fix. This would only be mildly annoying if there was a way to control mapping from VHDL. I did discover that if you put a COMP attribute on an ENTITY, that all of the logic (even behavioral asynchronous logic) in that Entity will get mapped to the same PFU. So in the extreme case, I could write separate VHDL entities for each PFU that I want to map. This still provides no control over TBUF, LUT, or FF assignment (which wouldn't really be a problem if PAR could swap these). But enough whining. Having finished this chip, I'm going to try porting the design to a Virtex. Hopefully this won't dispel my delusion that Xilinx software is much better. > The beta version of Foundry 2000 (Foundry 9.5) is due out in mid-July. > Ask for your copy... OK. I could also use an Orca4 data sheet. -- Don Husby <husby@fnal.gov> http://www-ese.fnal.gov/people/husby Fermi National Accelerator Lab Phone: 630-840-3668 Batavia, IL 60510 Fax: 630-840-5406Article: 23737
Hi, till now we run our lab (3rd & 4th semester) with the xilinx design flow from cadence. Unfortunately Europractice does not longer support this design flow. So I'm searching for a new design environment. I've tested Xilinx Foundation and found it quite good, but only aviable for Windows. The Solaris version (Alliance) hasn't the required features. Does anybody know a similar design environment for Sun Solaris? We need a schematic editor and a Verilog Compiler as well as tools for behavioral and functional tests (with verilog stimuli files). A graphical FSM-Editor would also be fine. Or does anybody has experience with Xilinx Foundation in Win-Networks? The pools are used by many students and I don't want to install the software every semester on every PC anew. Is it possible to make a server installation of Foundation, where setting are stored only local in the home dir's of the students? Thanks in advance -- Jens Popp Institut fuer Rechnerstrukturen Universitaet Siegen Hoelderlinstr.3 D-57068 Siegen Germany mailto:popp@rs.uni-siegen.deArticle: 23738
Nial Stewart <nials@sqf.hp.com> wrote in message news:39648C8B.B92714AE@sqf.hp.com... > I've been interested in evaluating the free versions of Leonardo > and FPGA Express that Alera have been promising for the > last few months and so have been keeping an eye on their > web site. > > Initially this was announced early this year as being > "available in May". Nothing happened, there was no sign > of any software then mid May the text mysteriously changed > to "available in June". It's not approaching mid July > guess what ..... We received our Leonardo/FPGA Express software from Altera about a month ago. Seems to work OK. You should have a word with your local Altera rep. MHArticle: 23739
Kai Schulze wrote in message <3964734C.D088118F@ee.nec.de>...
>Hi,
>
>I'm working with a XILINX XC40250XV and I have following problem:
>
>There is an signal input port and a internal clock should be generated
>from this signal.
>How can I push synopsis to create the internal clock buffer for this
>internal clock automatically.
>Is there at all a way to say "synopsis do this".
If that signal is connected to only flip-flop clocks, the tool should infer
the proper global buffer.
-- a
-----------------------------------------
Andy Peters
Sr Electrical Engineer
National Optical Astronomy Observatories
950 N Cherry Ave
Tucson, AZ 85719
apeters (at) noao \dot\ edu
"A sufficiently advanced technology is indistinguishable from magic"
--Arthur C. Clarke
Article: 23740
Colin Marquardt wrote in message ...
>* Srinivasan Venkataramanan writes:
>
>>> process. The variable "feedback" is assigned a value inside the if
>>> clock'EVENT statement which seems to me will generate an additional,
>>> unwanted FF. The only FFs in the design should be LFSR(0:3). Am I right
>>> or is this code fine?
>>>
>
>> I think the code is JUST FINE :-) Since the "feedback" is a VARIABLE
and
>> not a SIGNAL
>> it shouldn't give you extra FF.
>
>And to make it clear for newbies: the variable does not give a
>register in this case because it is assigned a value before it
>is read. The other way round (read before it is assigned), it
>would have to become a FF because it will have to remember the
>old value so that you can read it.
>
>In short, variables are only *candidates* for FFs, signals always
>*are* FFs.
And to make it clearer, the signals must be in a clocked process to become a
flop.
-- a
-----------------------------------------
Andy Peters
Sr Electrical Engineer
National Optical Astronomy Observatories
950 N Cherry Ave
Tucson, AZ 85719
apeters (at) noao \dot\ edu
"A sufficiently advanced technology is indistinguishable from magic"
--Arthur C. Clarke
Article: 23741Please check your PC configuration. First, I found if bus frequency of the motherboard of the desktop computer is over 66MHz, it will cause a fail while you program the CPLD/FPGA using HW-JTAG-PC cable, but the notebook won't. So maybe you have to choose an "old" pentium desktop computer or a notebook. Secondary, check your Parallel Port type in your PC's BIOS config, it cannot to be set to "EPP" mode, if so, change it to SPP(Normal) mode. The third, are there enough decoulpe capacitor arround the CPLD chip? Hope it can solve your problem. Good luck. Regards, Channing Wen In article <%Qs85.665$i_.9720@wagner.videotron.net>, "Simon Bilodeau" <sbilodo@videotron.ca> wrote: > Is it normal to have 200 ohms resistance between TCLK and TMS and between > TCLK and TDI pins directly on the chip? > > I saw that those pins influence each other because the programmer's pins > can't get enough current on IC's pins (the programmer works well alone) and > I didn't see anything special that could make a short on the board. > > anybody knows why > > thanks in advance > > Simon > > "G. Hobson Frater" <hobson.frater@xilinx.com> wrote in message > news:395D4D14.B5958F6C@xilinx.com... > > Simon, > > > > If you haven't already, you might want to check the Xilinx Answers > database at > > http://support.xilinx.com. In the Answers Search Field try typing > something > > like " bit position '0' ". Answer record #2881 may help. > > > > -Hobson > > Xilinx Applications > > > > Simon Bilodeau wrote: > > > > > Hi, > > > > > > i<m new in ISP with CPLD and i have an error uploading a version in my > CPLD. > > > Every connection seems do be ok but i always get that error... > > > > > > Any idea? > > > > > > Log file : > > > > > > Loading Boundary-Scan Description Language (BSDL) file > > > 'C:/Fndtn/xc9500/data/xc95288.bsd'.....completed successfully. > > > Checking boundary-scan chain integrity...ERROR:JTag - Boundary- scan > chain > > > test failed at bit position '0' on instance 'projet24(Device1)'. > > > Check that the cable, system and device JTAG TAP connections are > correct, > > > that the target system power supply is set to the correct level, > > > that the system grounds are connected and that the parts are properly > > > decoupled. > > > ERROR:JTag - Boundary scan chain has been improperly specified. Please > > > check your configuration and re-enter the boundary-scan chain > information. > > > Boundary-scan chain validated unsuccessfully. > > > ERROR:JTag - : The boundary-scan chain has not been declared correctly. > > > Verify the syntax and correctness of the device BSDL files, correct the > > > files, > > > reset the cable and retry this command. > > > > Sent via Deja.com http://www.deja.com/ Before you buy.Article: 23742
I seek advice on the following.... I would like to generate 56 PN streams (using LFSRs) that exhibit as little cross-correlation between each other as possible. Each LFSR will be clocked at 100kHz and each LFSR shall have a maximal count of at least 30 seconds. (>= 22 taps). Is there a way to select the polynomials to minimize the cross correlation? Can this be done with 11 PN streams and then use gold codes to generate an additional 45 streams? Any advice, pointers to papers, web sites etc. would be much appreciated. I plan on taking advantage of SRL16's of the Virtex devices but am struggling with the proper polynomials for the LFSRs. Many thanks in advance! JeffArticle: 23743
fliptron@netcom.com (Philip Freidin) wrote: > Which in fact is what Don Husby (Our token Lucent user) did back > in November 1994, and made it available . Written in awk. This is still available. Since I now have an AWK compiler, I can generate a standalone executable. I have extended the syntax considerably (for example to handle buses) mostly in the direction of developing Lucent chips, but it still uses the Xilinx unified library so it probably wouldn't take much effort to update it to use the latest Xilinx libraries. It can also do netlist flattening and allows you to put mapping directives on a schematic sheet that access heirarchical signal names from other sheets. I dream of taking a year off to re-write this in C++ as a standalone design-entry tool. Ideally, it would compile to an EDIF netlist for synthesis, but also compile to a VHDL netlist for simulation. -- Don Husby <husby@fnal.gov> http://www-ese.fnal.gov/people/husby Fermi National Accelerator Lab Phone: 630-840-3668 Batavia, IL 60510 Fax: 630-840-5406Article: 23744
Don Husby wrote: ...much whining and complaining snipped... ;) > But enough whining. Having finished this chip, I'm going to try porting > the design to a Virtex. Hopefully this won't dispel my delusion that Xilinx > software is much better. If your experience turns out to be anything like mine, you are in for another whole boat load of work. I had to rewrite my VHDL for three compiliers on the one VHDL project I did. Each time I got the code to produce decent logic, I would have to change compiliers and start all over. It seems that they don't work well with the same syntax. Each one likes to see state machines, etc. written differently. The real trick is figuring out what that style is. Once you learn it, it is not hard to write to that style. But then you might be using the same tools for the different targets. If so, you likely won't have any real problems. But keep us posted. -- Rick Collins rick.collins@XYarius.com Ignore the reply address. To email me use the above address with the XY removed. Arius - A Signal Processing Solutions Company Specializing in DSP and FPGA design Arius 4 King Ave Frederick, MD 21701-3110 301-682-7772 Voice 301-682-7666 FAX Internet URL http://www.arius.comArticle: 23745
There is a LFSR tool that you can download from
http://www.jps.net/kyunghi/LFSR/. It is a nice program that lets you
design LFSRs with every parameter tunable. It is very interactive and
will give you the taps for a maximal LFSR or let you design your own
taps and see what the sequences are.
The only limitation is the length of the register, 16 bits. But that
should not be an issue in your case since you can use two sequences of
less than 22 bits and XOR them to get a new sequence. This may be an
easier way to get the 56 independant bit streams you want.
18 x 17
18 x 16 14 combinations
18 x 14...
18 x 4
17 x 16
17 x 15 12 combinations
17 x 14...
17 x 5
.
.
.
13 x 12
13 x 11 4 combinations
13 x 10
13 x 9
12 x 11 2 combinations
12 x 10
Total = 56 combinations
5 + 6 + 7 ... 17 + 18 + 56 = 388 bits of LFSR
vs.
22 * 56 = 1232 bits of LFSR
You can use the individual LFSRs as common sources and use 56 XOR gates
to combine them. This will save you a LOT of logic. You might want to do
some testing to verify that the resultant bit streams are not
correlated.
Jeff Reeve wrote:
>
> I seek advice on the following....
>
> I would like to generate 56 PN streams (using LFSRs) that exhibit as little
> cross-correlation between each other as possible. Each LFSR will be clocked
> at 100kHz and each LFSR shall have a maximal count of at least 30 seconds.
> (>= 22 taps). Is there a way to select the polynomials to minimize the cross
> correlation? Can this be done with 11 PN streams and then use gold codes to
> generate an additional 45 streams? Any advice, pointers to papers, web sites
> etc. would be much appreciated. I plan on taking advantage of SRL16's of the
> Virtex devices but am struggling with the proper polynomials for the LFSRs.
>
> Many thanks in advance!
> Jeff
--
Rick Collins
rick.collins@XYarius.com
Ignore the reply address. To email me use the above address with the XY
removed.
Arius - A Signal Processing Solutions Company
Specializing in DSP and FPGA design
Arius
4 King Ave
Frederick, MD 21701-3110
301-682-7772 Voice
301-682-7666 FAX
Internet URL http://www.arius.com
Article: 23746I think I made a mistake in the math. The number of bits needed should read 5 + 6 + 7 ... 17 + 18 + 56 = 217 bits of LFSR So it is more like a 6:1 reduction in logic. Sorry, Rickman wrote: > 5 + 6 + 7 ... 17 + 18 + 56 = 388 bits of LFSR > vs. > 22 * 56 = 1232 bits of LFSR -- Rick Collins rick.collins@XYarius.com Ignore the reply address. To email me use the above address with the XY removed. Arius - A Signal Processing Solutions Company Specializing in DSP and FPGA design Arius 4 King Ave Frederick, MD 21701-3110 301-682-7772 Voice 301-682-7666 FAX Internet URL http://www.arius.comArticle: 23747
Hi, I've got some high fanout signals for which I would like to create a buffer tree. I am using synplify and I can't get the compiler to leave the buffers where I want them. I am sure some of you have dealt with this before and I hope you'll let me know how to do this. Thanks, Ties.Article: 23748
Just for grins, I looked for the minimal set of logic to implement this. I think we can limit the number of base LFSRs to combinations of four so that they can be combined in a 4 input LUT. We can't quite get enough usable combinations from a maximum length of 9 LFSRs, so I bumped it up to 10 and took off the short sequence of 2 since it contributes to few useful combinations. So we are left with LFSRs length 3 through 10 = 52 + 56 = 108 FFs (some with one LUT). Then the trick is verifying that the sequences do not correlate. 4 LFSRs of 22 or more total bits 4,5,6,7 3,5,6,8 4,5,6,8 3,4,7,8 3,5,7,8 4,5,7,8 3,6,7,8 4,6,7,8 5,6,7,8 3,4,6,9 3,5,6,9 4,5,6,9 3,4,7,9 3,5,7,9 4,5,7,9 3,6,7,9 4,6,7,9 5,6,7,9 3,4,8,9 3,5,8,9 4,5,8,9 3,6,8,9 4,6,8,9 5,6,8,9 3,7,8,9 4,7,8,9 5,7,8,9 6,7,8,9 3,4,6,10 3,5,6,10 4,5,6,10 3,4,7,10 3,5,7,10 4,5,7,10 3,6,7,10 4,6,7,10 5,6,7,10 3,4,8,10 3,5,8,10 4,5,8,10 3,6,8,10 4,6,8,10 5,6,8,10 3,7,8,10 4,7,8,10 5,7,8,10 6,7,8,10 3,4,9,10 3,5,9,10 4,5,9,10 3,6,9,10 4,6,9,10 5,6,9,10 3,7,9,10 4,7,9,10 5,7,9,10 6,7,9,10 3,8,9,10 4,8,9,10 5,8,9,10 6,8,9,10 7,8,9,10 -- Rick Collins rick.collins@XYarius.com Ignore the reply address. To email me use the above address with the XY removed. Arius - A Signal Processing Solutions Company Specializing in DSP and FPGA design Arius 4 King Ave Frederick, MD 21701-3110 301-682-7772 Voice 301-682-7666 FAX Internet URL http://www.arius.comArticle: 23749
In article <8k0p4h$g1b$1@seagoon.newcastle.edu.au>, mwojko@hartley.newcastle.edu.au (Mathew Wojko) wrote: > Has anyone successfully implemented carry ripple adders (using the > fast carry logic) on the XC4000 series of devices? I know that you have > to be very specific with the code that you write - by specifying and > mapping the carry functions and signals to specific parts of the CLB. > At the moment, I just cannot get it work and have spent a fair > amount of time on it. Look at the intrperf sample in the Samples of the PamDC distribution (which you can download from Compaq). /pam/src/Samples/intrperf/design/src/Design.cxx template<int N> class LdCounter I'm not posting anything because the code is subject to the license agreement. Go to http://www.research.digital.com/SRC/pamette/Software.html to download the PamDC software. Stefan Sent via Deja.com http://www.deja.com/ Before you buy.
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