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"Mike Treseler" <mike.treseler@flukenetworks.com> wrote in message news:396F8385.A368F876@flukenetworks.com... > > When you get down to 1 in 1000, you can use manual methods > to find the problem. I use BDM emulators to walk bits. > BDM is good, but can - IMHO - just test the elements connected to the µP. This can be suited for the boards you need to test, but on our boards BDM would do the job completly (of course: Boundary Scan doesn't either ; in some cases several hours of testing are necessary to check a board who has to interconnect with many other boards) Once you get the hang of programming Boundary Scan, and maybe developping your own tricks, you can do a lot with it, in limited time. As always in business you have to decide in accordance with your own production if detailed testing is worth the cost. Boundary scan isn't the fastest way to test (BDM for example IS faster), and to make a detailed fault description can be a lot of programming work, so mostly engineering work. For good/fault detection better ways can be appropriate, but for what we do (small production lots, but expensive boards), Boundary Scan is a blessing (most of our boards need to be tested 100% before they may be delivered). I can't tell that much success stories, but maybe a small example: if the Boundary Scan test is used on a Board of ca.1100 EUR, and it says that it was trying to test the connection between pin 142 on DSPx and pin 221 on FPGAy, and than you see pin 221 of the FPGA is not soldered, the testing was worth it (visual checks on 240-pins is not that simple...on BGA it's even complettely impossible - without expensive tools like X-Ray etc). Of course, you should be using the information the tests give you to improve your production process, but in some businesses you can't take the risk of not testing... Greetings, AlainArticle: 23926
There is a cracked version of Viewlogic 4 (DOS) with the Xilinx 2k 3k and 4k libraries and cracked XACT6.01 doing the rounds, on a CD, with PDF scanned-in documentation !! for a few years now. A Russian documented the VL dongle back in '92 and the program was cracked soon afterwards. Good solid 100% reliable tools, I paid $10k or so for mine in '91, and narrowly escaped paying $3k "annual maintenance" for XACT6 to the UK disti just 2 months before Xilinx stopped developing it... But I still wouldn't use the XC2k chips now, or 3k for that matter. Unless I had many thousands in stock and wanted to use them up. 4k chips are probably still a good choice, if the price is right. >We know that this is not the question. But it is very unlikely that you >will get anyone to sell you their software. If they still have it, they >will have been keeping it because they need to support an old design. If >they don't need to keep it for this, then it is very unlikely that they >will still have it around since this software has not been distributed >for over two years! > >Can you explain why you want to work with these old chips rather than to >get new ones? Peter. -- Return address is invalid to help stop junk mail. E-mail replies to zX80@digiYserve.com but remove the X and the Y. Please do NOT copy usenet posts to email - it is NOT necessary.Article: 23927
I am no expert on board layout for high speed signals, but 10 ohms sounds awfully low. I would be surprised if the driver chip can drive this to a proper high. To get 2.4 volts you will need to drive 240 mA!!! Not many drivers can supply this much current. This low termination impedance is likely fixing your problem by acting as a voltage divider and reducing the entire signal and the glitch with it. From what I have read, 50 ohms is a good typical termination impedance for fine geometry traces. If you still have reflections with this value it is likely that you need to change the topology of the traces rather than the impedance. I have found that a star arrangement works great if your traces can all be kept under about 4". If you need longer traces, then you should route the clock signal as a line going from one chip pin to the next without stubs. This will have the longest path length, but with a termination resistor at the end, you will get very minmal reflections. Just my 2 cents worth. Remember, this is not my field of expertise. Matt Gavin wrote: > > > Problem solved. > > It was a clock glitch, reflection, etc. Putting the scobe probe (8pF > cap) > on the clock line, solved the problem. (I had probed this clock > previously, > but after it went through some logic. Grr!). We subsequently changed > a termination resistance on the clock line, from 50 ohm to 10 ohm. > This solved the problem on the board (no probe needed). > Apparently our board designer didn't do a very precise job of > choosing the board resistance values (gross estimation, except > for the address and data lines.) > > I have learned a lot about board-level debug this last week. > Thanks for all your help. > > Matt Gavin > Rockwell Collins > > > -- Rick Collins rick.collins@XYarius.com Ignore the reply address. To email me use the above address with the XY removed. Arius - A Signal Processing Solutions Company Specializing in DSP and FPGA design Arius 4 King Ave Frederick, MD 21701-3110 301-682-7772 Voice 301-682-7666 FAX Internet URL http://www.arius.comArticle: 23928
This problem often arises when you gate the clock going to the destination register (obviously, the gating adds delay). For this reason, gated clocks are generally to be avoided. Adding a buffer between source and destination register, as one of your respondents suggested, is not only inelegant but tricky, in that place-and-route software generally removes such added logic as part of its minimization algorithm. Jamie Lokier wrote: > MK Yap writes: > > Hi!! > > " Error: Delay path from '|bsp_in:73|bytedata_2_.Q' to > > '|bsp_in:73|intdata_2_.Q' is 4.2ns, but Clock skew is 2.9ns and hold time > > required for '|bsp_in:73|intdata_2_.Q' is 1.4ns - circuit cannot operate > > because Clock skew plus hold time of destination register exceeds > > register-to-register delay " > > > I encounter this problem when i've finished compiling the project & doing > > the timing analysis. Most of the time, my design did not give me this error > > mesg but it happened ocassionally. I changed other part of the circuit but > > did not make any changes on the bsp_in portion. What can I do to ensure this > > won't happen again? How can i put any constraint and where i should put it? > > Thanks. > > > I'm using Maxplus2 9.3 & Synplify 5.3.1 for my VHDL codes, running on PC, > > targetted at flex10k30e. > > Pls advice > > Use a different version of Maxplus2. 9.24 (older) and 9.6 (newer) seem > to be fine. > > -- JamieArticle: 23929
In article <3970E612.D5D09A52@earthlink.net>, Eric Vannerson <ericvann@earthlink.net> writes: > This problem often arises when you gate the clock going to the destination > register (obviously, the gating adds delay). For this reason, gated clocks are > generally to be avoided. Adding a buffer between source and destination register, > as one of your respondents suggested, is not only inelegant but tricky, in that > place-and-route software generally removes such added logic as part of its > minimization algorithm. "generally to be avoided" is putting it mildly, at least in the FPGA context. I would have said "state of sin" or "not supported". That technique is left over from the old TTL/MSI days when many chips didn't have clock-enable pins. The only reason I can think of to actually put a gate on the clock path today would be to save power when you are really desperate. -- These are my opinions, not necessarily my employers. I hate spam.Article: 23930
hi, how should one connect JTAG pins on a spartan II which is connected to PCI ? If one chains spartanII to PCI TDI/TDO, can it be programmed using the jtag header ? (I think the answer to this is no). Also are there any problems with chaining a spartanII part to other jtag chips on the same pci board ? I'd appreciate any suggestions on how to connect jtag pins on a pci board with spartanII and other jtag chips. thanksArticle: 23931
The schematic fof the download cable for their ISP XC9500 CPLD's is available on the Xilinx website, along with the software to do the download. Design/Configuration software is also available there at no cost. Dick On Tue, 04 Jul 2000 11:08:48 +0200, Bernard Bertrand <bertrand@olfac.univ-lyon1.fr> wrote: >Hello, > >I start working in VHDL and >i purchase a free PCB programmer for FPGA or CPLD chip >(Altera, xillinx, Cypress...) > >Thank you for you answer >bertrand@olfac.univ-lyon1.fr >Article: 23932
MOVE SO TO ZIMBABWE!!! In article <8kj11h$9fp$1@info3.fnal.gov>, husby@fnal.gov (Don Husby) wrote: > This is way off topic. > > I'm thinking it's time to leave my cushy science job in Chicago > and move to the West Coast. The scariest aspect of this is the > nightmare stories I've heard about the difficulties of finding > a place to live in Silicon Valley and the Bay area. > Is it really that bad? > Are there areas that are better/worse than others? > Will I be spending hours per day in my car trying to get to work? > > -- > Don Husby <husby@fnal.gov> http://www- ese.fnal.gov/people/husby > Fermi National Accelerator Lab Phone: 630- 840-3668 > Batavia, IL 60510 Fax: 630- 840-5406 > Sent via Deja.com http://www.deja.com/ Before you buy.Article: 23933
try to visit my site you will find some good links for FPGA http://www.geocities.com/SiliconValley/Pines/6639/fpga and visit also www.opencores.org they are designing open cores that you can learn from Regards jamil khatib Nick Young wrote: > Hi, > > I am new to FPGA's and want to learn how to use them. This includes > designing, simulation and implementation. Can anyone tell me of a good > introduction/tutorial on the topic, (on-line if possible). > > Cheers, > NickArticle: 23934
> Hi,
> I have been using the free Atmel IDS system and
> produced real designs for real products. It
works
> well provided you know VHDL. You need to make
> sure you download the latest patches from the
> Atmel website. Unfortunately the synthesiser
> still has a few bugs (notably in implementing
> bidirectional pins - if anyone has any solutions
> I'd like to hear - perhaps I'll make it the
> subject of a new post).
>
> You can get a free text based VHDL simulator
from
> www.symphonyeda.com. You'll need to write your
> output to the screen or to a file every clock
> pulse - but it does work well and it is free.
>
> Hope this helps
>
> Gordon Haddow
>
> Sent via Deja.com http://www.deja.com/
> Before you buy.
>
Hi Ulf, Gordon,
I have been using F1.3 for about half a year now,
but now want to learn about Atmel FPGAs and VHDL
as well.
Q1: Do you know some step by step tutorial for
using IDS 6.0 including information, how to
download the design to the FPGA?
Q2: I build my own development board for a
XC4005XL (well, it is much like the XESS
board;-). Do you think I can use it for
an Atmel chip as well?
Unfortunately there are no much discussions about
Atmel are going on on this forum. Any Idea why
Atmel is banned?
Regards,
Thomas
Sent via Deja.com http://www.deja.com/
Before you buy.
Article: 23935Hi Ulf, Hi Gordon, About half a year ago I started to experiment with FPGAs. I bought the Xilinx Student Edition and build my own prototyping board from the lab book. But I am interestet in the Atmel parts too and therefore ordered IDS 6.0. Now, since the Atmel parts are pincompatible to the Xilinx ones (XC4005XL <--> AT40K05), it should be possible to use my prototyping board. The question will be, how to download the Atmel .bst file to the FPGA or to the configuration EEPROM (AT17C256). Thanks for any reply, Thomas Sent via Deja.com http://www.deja.com/ Before you buy.Article: 23936
theidel@my-deja.com wrote: > I have been using F1.3 for about half a year now, > but now want to learn about Atmel FPGAs and VHDL > as well. > > Q1: Do you know some step by step tutorial for > using IDS 6.0 including information, how to > download the design to the FPGA? > > Q2: I build my own development board for a > XC4005XL (well, it is much like the XESS > board;-). Do you think I can use it for > an Atmel chip as well? > > Unfortunately there are no much discussions about > Atmel are going on on this forum. Any Idea why > Atmel is banned? I can't say for sure if you can use the Atmel parts on a board made for Xilinx. As to the issue of "banning" Atmel discussion from this newsgroup, I think this is just a matter of discussing what we use. I have worked with the 6K Atmel parts and in the end I did not find them very flexible. The AT40K parts are a bit more flexible, but they are not nearly as good as the Xilinx parts and these days the Atmel parts are getting very obsolete. For example, Xilinx is bringing out a new product line, the Spartan II, which will have several chips offered below $10 each and have much more capability than any of the Atmel devices. How long has it been since Atmel has offered a new FPGA? What is it that you like about the Atmel FPGA chips? -- Rick Collins rick.collins@XYarius.com Ignore the reply address. To email me use the above address with the XY removed. Arius - A Signal Processing Solutions Company Specializing in DSP and FPGA design Arius 4 King Ave Frederick, MD 21701-3110 301-682-7772 Voice 301-682-7666 FAX Internet URL http://www.arius.comArticle: 23937
Hal Murray wrote: > > In article <3970E612.D5D09A52@earthlink.net>, > Eric Vannerson <ericvann@earthlink.net> writes: > > This problem often arises when you gate the clock going to the destination > > register (obviously, the gating adds delay). For this reason, gated clocks are > > generally to be avoided. > > "generally to be avoided" is putting it mildly, at least in the FPGA > context. I would have said "state of sin" or "not supported". actually it's 'state of the art' for serious power savings, and the tools are slowlt catching up - another reason for more closely integrated synthesis and P&R tools .... I think I read somewhere transmeta have something like 10k gated clocks - and broke some timing tool they were using as a result (take my numbers with a grain of salt - it's a dim recollection) Paul CampbellArticle: 23938
http://www.jps.net/kyunghi/LFSR/ <est0@lehigh.edu> wrote in message news:45n2ms8ipqkskqrp374tkh846oiroqqpbb@4ax.com... > I need to implement a pn generator. I have been through all of the > Xilinx ap notes, and other materials that I can find, and I have been > able to generate the verilog code to generate a shift register that > almost does what I want. However, it, like all lsfr's, puts out 2^n-1 > states before it repeats. I need to augment or stall that output so > that I add a 0 to the end of every sequence, so as to create sequences > with a length of 2^n. I see all sorts of mention of how easy that is > to do, but I can't figure it out, and nowhere is it explained. Does > anyone know how to do what I want to do? > > TIA, > Ed >Article: 23939
2000 MAPLD International Conference
Kossiakoff Conference Center
The Johns Hopkins Univerisity- Applied Physics Laboratory
Laurel, Maryland 20723-6099
September 26-28, 2000
The 3rd annual Military and Aerospace Applications of Programmable
Devices and Technologies International Conference will address devices,
technologies, usage, reliability, fault tolerance, radiation
susceptibility, encryption, and applications of programmable devices
and adaptive computing systems in military and aerospace systems. The
program will consist of oral and poster technical presentations and
industrial exhibits. This conference is open to US and foreign
participation and is unclassified.
http://rk.gsfc.nasa.gov/richcontent/MAPLDCon00/MAPLDCon00.html
The Technical Program has been published and is available on-line:
http://rk.gsfc.nasa.gov/richcontent/MAPLDCon00/Technical_Program.html
Registration is open and information is available at:
http://rk.gsfc.nasa.gov/richcontent/MAPLDCon00/Reg/Registration.html
Invited Speakers:
Keynote Address: Henry Spencer - SP Systems
"Faster, Better, but Most Important, Much Much Cheaper"
History Invited Talk: Eldon Hall, MIT Instrumentation Lab
"The Apollo Guidance Computer - A Designer's View"
Dinner Speaker: Dr. Thomas Jones, NASA Astronaut Office
"ISS: The Exploration Proving Ground"
Lloyd Massengill, Vanderbilt University
"Single Event Modeling on Emerging Commercial Technologies"
Dr. Mark Jones, Virginia Tech
"High-Level Programming Issues for Large Reconfigurable
Computing Systems"
AIAA Invited Talk: James Kinnison, Applied Physics Lab
"System Level Radiation Tolerance"
Sponsored By:
NASA Goddard Space Flight Center
JHU/Applied Physics Laboratory
National Security Agency
NASA Electronics Radiation Characterization Project
Military & Aerospace Programmable Logic Users Group
American Institute of Aeronautics and Astronautics
IEEE Aerospace & Electronic Systems Society (AESS)
Article: 23940Jens Popp wrote: > > Hi, > > when I create new HDL code (File/New/Verilog Module), how can I update > the symbol ports? The standard symbol has no ports. Is there a way to > generate them automatically? Or are they to be generated manualy(add > port) ? > > Regards > -- > > Jens Popp > Institut fuer Rechnerstrukturen > Universitaet Siegen > Hoelderlinstr.3 > D-57068 Siegen > Germany > > mailto:popp@rs.uni-siegen.de AFAIK you should add them manualy. Regards Y EL Kolli. -- ===================================================== EL KOLLI Yacine | e-mail:elkolli@crf.canon.fr Canon C.R.F. | Phone: +33.(0)2.99.87.68.79 http://www.crf.canon.fr | FAX: +33.(0)2.99.84.11.30 ====================================================Article: 23941
In article <3961A99F.CFD63176@olfac.univ-lyon1.fr>, Bernard Bertrand <bertrand@olfac.univ-lyon1.fr> wrote: > Hello, > > I start working in VHDL and > i purchase a free PCB programmer for FPGA or CPLD chip > (Altera, xillinx, Cypress...) > > Thank you for you answer > bertrand@olfac.univ-lyon1.fr I've designed my own PCB for a chinese copy of the Altera ByteBlaster, and had a couple made. You are welcome to the Gerber and Excellon files if you want to get your own made. Leon -- Leon Heller, G1HSM Tel: (Mobile) 079 9098 1221 (Work) +44 1327 357824 Email: leon_heller@hotmail.com Web: http://www.geocities.com/SiliconValley/Code/1835 Sent via Deja.com http://www.deja.com/ Before you buy.Article: 23942
Hi My present XCS40XL design takes about 25 minutes from editing to .bit file generation. I'm using a 200MHz Pentium Pro with 64MB RAM and Windoze 95. What sort of ballpark speed improvement could I get by using a faster PC and/or more RAM? Has anyone run the same design on different machines? I need to balance run time improvements against the hassle of upgrading my PC. Cheers -- Keith WoottenArticle: 23943
I recommend that you take a look at this. It is free software with no gotchas whatsoever. It will give you information about a given LFSR (up to 16 bits) and will even generate verilog, vhdl and ahdl. I posted about this once before and got no responses. If you check it out, please post your opinions here. JEAN NICOLLE wrote: > > http://www.jps.net/kyunghi/LFSR/ > > <est0@lehigh.edu> wrote in message > news:45n2ms8ipqkskqrp374tkh846oiroqqpbb@4ax.com... > > I need to implement a pn generator. I have been through all of the > > Xilinx ap notes, and other materials that I can find, and I have been > > able to generate the verilog code to generate a shift register that > > almost does what I want. However, it, like all lsfr's, puts out 2^n-1 > > states before it repeats. I need to augment or stall that output so > > that I add a 0 to the end of every sequence, so as to create sequences > > with a length of 2^n. I see all sorts of mention of how easy that is > > to do, but I can't figure it out, and nowhere is it explained. Does > > anyone know how to do what I want to do? > > > > TIA, > > Ed > > -- Rick Collins rick.collins@XYarius.com Ignore the reply address. To email me use the above address with the XY removed. Arius - A Signal Processing Solutions Company Specializing in DSP and FPGA design Arius 4 King Ave Frederick, MD 21701-3110 301-682-7772 Voice 301-682-7666 FAX Internet URL http://www.arius.comArticle: 23944
In article <3970B7CA.D605691F@yahoo.com>, rickman <spamgoeshere4@yahoo.com> wrote: > I am no expert on board layout for high speed signals, but 10 ohms > sounds awfully low. (snip) He may be talking about a series (source) termination, in which case a 10 ohm resistance won't hurt. It may be a little on the low side, depending on the trace impedance and the driver output impedance. -- Greg Neff VP Engineering *Microsym* Computers Inc. greg@guesswhichwordgoeshere.com Sent via Deja.com http://www.deja.com/ Before you buy.Article: 23945
In article <3972054D.C5A258E6@yahoo.com>, rickman <spamgoeshere4@yahoo.com> wrote: > theidel@my-deja.com wrote: > > I have been using F1.3 for about half a year now, > > but now want to learn about Atmel FPGAs and VHDL > > as well. > > > > Q1: Do you know some step by step tutorial for > > using IDS 6.0 including information, how to > > download the design to the FPGA? > > > > Q2: I build my own development board for a > > XC4005XL (well, it is much like the XESS > > board;-). Do you think I can use it for > > an Atmel chip as well? > > > > Unfortunately there are no much discussions about > > Atmel are going on on this forum. Any Idea why > > Atmel is banned? > > I can't say for sure if you can use the Atmel parts on a board made for > Xilinx. > > As to the issue of "banning" Atmel discussion from this newsgroup, I > think this is just a matter of discussing what we use. I have worked > with the 6K Atmel parts and in the end I did not find them very > flexible. The AT40K parts are a bit more flexible, but they are not > nearly as good as the Xilinx parts and these days the Atmel parts are > getting very obsolete. > > For example, Xilinx is bringing out a new product line, the Spartan II, > which will have several chips offered below $10 each and have much more > capability than any of the Atmel devices. > > How long has it been since Atmel has offered a new FPGA? > > What is it that you like about the Atmel FPGA chips? - I can download a complete development system for free - I get lots of RAM inside a 84-pin PLCC, which is the only one I am able to use If I would be a professional like you and my company paying for the tools and recources I would like to use, I would be happy with Xilinx. Unfortunatly wether Xilinx nor Atmel care a lot about hobbyists buying 1 or 2 chips a year. So I try to learn more about "obsolete" parts from the professionals here on this board. Sorry about that, Thomas > > -- > > Rick Collins > > rick.collins@XYarius.com > > Ignore the reply address. To email me use the above address with the XY > removed. > > Arius - A Signal Processing Solutions Company > Specializing in DSP and FPGA design > > Arius > 4 King Ave > Frederick, MD 21701-3110 > 301-682-7772 Voice > 301-682-7666 FAX > > Internet URL http://www.arius.com > Sent via Deja.com http://www.deja.com/ Before you buy.Article: 23946
Hi all, What pin's would I need to erase locked devices? I have a few devices of the above with the JTAG port disabled, I made an error in my programmer, and now I need to erase them. I have been told that I'd need a third party programmer to do this, but surely I only need to design a board for myself. Has anyone ever done this, or have any links that I could find usefull, I've done a bit of surfing around but found nothing as of yet. Thanks MikeArticle: 23947
I've been banging my head against the Max+Plus2 fitter all day. I can't get some of my I/O's to meet a 7.5ns tco - which I have specified in the ACF file. It would appear that the routing delay from my mux to my output is too long. No problem I'll stick another DFF on the output of the mux to break the route into two. What does the fitter do? Slap the extra FF right next to the mux output FF in the same LAB. Neatly using the extremely fast local-LAB interconnect, but still having the same long route to the pin that I was trying to avoid! Aaargh! Anyone got any ideas on how to make the fitter do something sensible? The device is a 10KE100EBC356-1, MP2 v 9.6, using the Quartus fitter if it makes any odds... Any help greatly appreciated! Cheers, Martin Martin Thompson martin@gubbins.demon.co.uk http://www.gubbins.demon.co.uk/Article: 23948
You'll need the dongle along with the software, and you'll probably have to run it on a machine with DOS 6 and/or windows 3.1. You'll probably have a hard time finding someone who has both the software and the dongle and doesn't need to keep it for a legacy design. Ottwald Holler wrote: > Ottwald Holler wrote > > > I got some pcs of XC2018-fpga's. I'm hamradio operator and would like to > > realize some ideas with this fpgas. The only one problem is that the > > current versions of xilinx software doesnt support the xc2018. > > I'm therefore hardly looking for a working version of XACT5 (DOS&UNIX) > > or XACT6 (Windows) to buy! > > Anybody on the forum who could help me? > > Thanks a lot for thinkig about! > > > > Well, friends, thanks a lot for Your ideas I should use newer chips. But > that wasn't the question. I'm still looking forward for an announcement from > anyone who could sale me a working version of a development system that can > program the identified IC's, too! I still accepted that present xilinx > software system cannot hold it on duty, but maybe anyone vendor or freak may > have an old version in his archive and he will sale me for a kind price! > > Please let me know Your help. Thank You > Ottwald J.Holler -- -Ray Andraka, P.E. President, the Andraka Consulting Group, Inc. 401/884-7930 Fax 401/884-7950 email ray@andraka.com http://www.andraka.com or http://www.fpga-guru.comArticle: 23949
Hi folks, I've been trying to use Xilinx's implementation of the Java API for Boundary Scan (i.e. JTAG), and having performance (and correctness) problems. Is *anyone* else out there using this? Two of the functions in the API simply aren't implemented, and what is there is very slow (~38KHz, yes that's a K, using Xilinx's parallel cable). Does anyone know of any other implementations of such an API? Thanks, Gordon Stoll
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