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I'd like to thank everybody at Xilinx for paying attention to our comments. Here is my attempt at what I would like on a CD or web site. These are general comments/wishes. Xilinx actually does pretty well on most of these items. 1) I hate blinking/flashing crap. (and noise too) I've never been able to figure out why people put that sort of junk on their web site. It makes sense for banner-ads to do it, but if you own the whole page, why are you distracting me when I'm trying to find things on your page? (I think it's 200ms or so for your eye to move to something that blinked and settle down. Double that to get back to where you were, probably more if you have to find your place in some text.) 2) I don't want to install anything or register or run JaveScript. There are too many spammers/crackers in the world. I can't remember passwords. I don't trust cookies or java/script. Your install stuff probably won't work on my machine anyway. 3) Please don't assume I'm running a WIntel platform. I'm not. I consider xx.ppt and xx.doc files to be semi-useless. I can find a machine to read them, but I won't bother unless I'm really desperate. Same for spread sheets. Please give me raw text. And self decompressing exe files are out. Please just give me the raw file set. I'll take the space/time/bandwidth penalty. Note that search engines can't find stuff in those strange formats. (I like search engines - please cooperate.) 4) Please don't go wild with the graphics and color and fonts and other toys. There are a lot of web pages that make assumptions about the page layout and screen size and pixel size. I find a lot of them very hard to read. (I think the normal problem is that my screen has a lot of tiny pixels so the graphics come out reduced.) Many web pages remind me of a kid with a new toy. They do all sorts of "neat" things. Thanks, but they get tiring fast. And they don't help me to find what I'm looking for. The simple example is a fancy background. The next is colored fonts. Both reduce the contrast which is the main thing your eye uses to find character edges when reading. What I would really prefer is low-tech web pages. Let my browser do the layout. It's normally setup to use a slightly larger font. That breaks an amazing number of pages. Note that frames are evil - I can't easily bookmark the real pages or cut/paste the URL to send to a friend. 5) Please save "everything" on your web site. Please keep the URLs stable so I can bookmark them. I'm primarily thinking of old press releases. But old data sheets and app notes are occasionally very useful. (I have saved many old data books for this reason.) Please put dates on press releases (and everything else) so they make sense a few years from now. Yes, there is a possibility I will get stale information. I don't have a good solution for this. I think I'd be happy if the bookmark took me to a page that told me about the updated version of the info as long as it also gave me a link to the old one. Remember, I could have printed the old stuff or copied it to my disk. I haven't thought much about CDs. I think I'd be happy if they contained a snapshot of the current web site. Or as much as fits. But many of the above comments make sense. As somebody else mentioned, it helps if the directory structure and file names make sense. Document numbers or UIDs don't help much. ------- From Peter's msg: 5. Marketing is a necessary function. You may dislike the style ( as I do I sometimes), but without marketing, there would be no new products. Somebody has to coordinate the introduction, promotion, pricing, production, sales etc. Learn to accept marketing, life without them would be worse. Please don't give up the struggle. We need somebody to carry the message to their doorstep. Marketing has a reputation among geeks for "not getting it". I've seen some marketing that I considerd good, but there is a lot of truth to that reputation. I'm generally happy when marketing is telling me about new products, at least as long as they aren't cramming it down my throat/eyeballs when I'm trying to do something else. I consider your Xcell magazine to be very well done. I would be happy with a new products or new info section on the main web page. Perhaps with a bit of graphics so I can quickly evaluate what it's trying to tell me. But please don't jump up and down and scream in my face. I've come to your web site to get some info. Please help me find with I want rather than annoying me with flashing junk that I have to work to get rid of. Here is a slightly tongue-in-cheek proposal. How about making a geek friendly clone of your web site? I'm thinking of something without any blink/flash and only minimal graphics. I want graphs and logic diagrams. I don't want logos and designer layout. I think it's only a few of the top level pages that I find annoying. I wonder if somebody could make what I have in mind with just a big script. Then I'll bookmark the non-flashy pages and I won't have to go near the flashy/marketing versions. :) -- These are my opinions, not necessarily my employers. I hate spam.Article: 23801
Hi, is it possible to import the Xilinx Libraries for FPGA XC 4000E Series in Renoir as Blocks for the Block Diagrams? Regards -- Jens Popp Institut fuer Rechnerstrukturen Universitaet Siegen Hoelderlinstr.3 D-57068 Siegen Germany TEL +49 271 740 2376 FAX +49 271 740 2473 mailto:popp@rs.uni-siegen.deArticle: 23802
Hi all, Is there anyone using Quartus? I've heard that there are lots of problems with this tool... ChristelleArticle: 23803
Hal Murray wrote: > > I'd like to thank everybody at Xilinx for paying attention > to our comments. > > Here is my attempt at what I would like on a CD or web site. These > are general comments/wishes. Xilinx actually does pretty well on most > of these items. > > 1) I hate blinking/flashing crap. (and noise too) > > I've never been able to figure out why people put that sort of junk > on their web site. It makes sense for banner-ads to do it, but if > you own the whole page, why are you distracting me when I'm trying to > find things on your page? (I think it's 200ms or so for your > eye to move to something that blinked and settle down. Double that > to get back to where you were, probably more if you have to find > your place in some text.) I will second that vote. For an example of one of the very worst possible web sites, Gespac used to have a many K byte animated graphic of a metallic knight watching a flying CD wiz by his head. It had no product related content what so ever and took some 2 to 3 minutes to load via modem. They don't have this anymore, but they are still happy to have flashing graphics and blinking buttons. I don't remember Xilinx having much of this on their web site, but it doesn't hurt to mention it. > 2) I don't want to install anything or register or run JaveScript. > > There are too many spammers/crackers in the world. I can't remember > passwords. I don't trust cookies or java/script. > > Your install stuff probably won't work on my machine anyway. I agree with this 100%. Registration is one of the biggest PITA I know. I NEVER give out my real information to a web site when registering and have several Yahoo! email addresses so that there is no chance of exposing my main email address to more spam email. I also can never remember the account name or password, so I end up reregistering every time I need to access the web site. Needless to say this makes me go to the competitor's web sites first. > 3) Please don't assume I'm running a WIntel platform. I'm not. > > I consider xx.ppt and xx.doc files to be semi-useless. I > can find a machine to read them, but I won't bother unless > I'm really desperate. > > Same for spread sheets. Please give me raw text. > > And self decompressing exe files are out. Please just give me the > raw file set. I'll take the space/time/bandwidth penalty. > > Note that search engines can't find stuff in those strange > formats. (I like search engines - please cooperate.) I partially disagree with this. I think that his points are valid as not everyone runs on a Wintel architechture. But to speed downloads sometimes a zipped (or gz'd) file is better. This is important when accessing patches and software updates. Please keep these as compressed files or better yet, put them on CDs and send them out. I know that it cost you a few bucks, but people are paying for support, why can't you mail them out??? Even the compressed update files can be 40 or 50 MB. With a 5 to 7 hour download time they can be nearly impossible to download (even overnight) if your connection to the web is not reliable to stay connected until the download is done. But in any case, please don't stop zipping these files. > 4) Please don't go wild with the graphics and color and fonts > and other toys. > > There are a lot of web pages that make assumptions about the page > layout and screen size and pixel size. I find a lot of them very > hard to read. (I think the normal problem is that my screen has > a lot of tiny pixels so the graphics come out reduced.) > > Many web pages remind me of a kid with a new toy. They do all > sorts of "neat" things. Thanks, but they get tiring fast. And > they don't help me to find what I'm looking for. > > The simple example is a fancy background. The next is colored > fonts. Both reduce the contrast which is the main thing your > eye uses to find character edges when reading. > > What I would really prefer is low-tech web pages. Let my browser do > the layout. It's normally setup to use a slightly larger font. That > breaks an amazing number of pages. > > Note that frames are evil - I can't easily bookmark the real pages or > cut/paste the URL to send to a friend. I agree with this 1000%. I would also extend this to the PDF files that you provide for download. A very good (bad) example of this is the PDF file "hivolpkg.pdf" at URL http://www.xilinx.com/products/spartan2/hivolpkg.pdf. This file seems to have been intended to provide some valuable technical information, but got channeled through marketing on its way to the web site. Although it has a lot of info that I need and can't find elsewhere, it contains so many high density graphics that I can not view it without 10 second page updates. Every time I flip to another window or even adjust my view of the page it takes some 5 to 10 seconds to repaint the page. God forbid I was trying to view this file online!!! Please try to keep the graphic content of your web pages and PDF files minimal and functional. It is just not useful to "marketize" anything where the primary purpose is to convey information. If you would like to verify this, try making two versions of your web site the way some web sites have a native language and a English version. Let the viewer decide whether they want the streamlined version or the "marketized" version. Then count the page hits on both sides. You will likely see that after trying a couple of pages the viewers of the marketing pages give up and switch to the "clean" pages. Keep in mind that if you don't have the clean pages, they are likely moving on to a different site, possibly a competitor's. > 5) Please save "everything" on your web site. > > Please keep the URLs stable so I can bookmark them. > > I'm primarily thinking of old press releases. But old data sheets > and app notes are occasionally very useful. (I have saved many old > data books for this reason.) > > Please put dates on press releases (and everything else) so they make > sense a few years from now. > > Yes, there is a possibility I will get stale information. I > don't have a good solution for this. I think I'd be happy if the > bookmark took me to a page that told me about the updated version of > the info as long as it also gave me a link to the old one. Remember, > I could have printed the old stuff or copied it to my disk. > > I haven't thought much about CDs. I think I'd be happy if > they contained a snapshot of the current web site. Or as much > as fits. But many of the above comments make sense. > > As somebody else mentioned, it helps if the directory structure > and file names make sense. Document numbers or UIDs don't help > much. I also agree 100% with this. I read a web page on writing web pages where the author said he was opposed to "broken links". At the time I did not understand the implications. He was saying that once you create a web page, you should never delete it without putting something in it's place. It is a bit like product support. You don't just stop making a given part. You give plenty of warning, provide a pin compatible substitute and lots of support to ease the conversion. For web pages, you try to pick a web structure that will fit your needs for a long time. When you want to reorganize you leave something in the place of an old page telling people where the new information is. The search engine could be improved. I have searched on file names before (such as "hivolpkg.pdf") and not been able to find where I got them from. You might think about keeping track of the searches people perform and see the ones that get no hits. Maybe you need to add some more keys to the engine. One other point I would like to make is that links should not be blind. They should always make sense in context. Many, many pages use links without telling you what lies ahead. Every link on a page should let you have some idea of what you will find when you load it. I have seen many links that are just a part number with no supporting text (my pages included). Until I click on it, I don't know if I am going to a page that tells me all about the part, downloads a PDF data sheet or adds the part to an order form! Example "Sparty's Favorite Recipes" on http://www.xilinx.com/products/spartan2/index.htm. I have no idea at all what this is going to give me! I think that Xilinx has improved their web pages over the last couple of years. Some of the things they do right are to put text behind the graphic buttons on the main page (always the worst graphic offender) so that they can be clicked on without waiting for the page to load. This is very nice since it allows you to ignore the graphics if you want. It would be nice to get some feedback on all this so that we know that our comments are not just bits in the ether. -- Rick Collins rick.collins@XYarius.com Ignore the reply address. To email me use the above address with the XY removed. Arius - A Signal Processing Solutions Company Specializing in DSP and FPGA design Arius 4 King Ave Frederick, MD 21701-3110 301-682-7772 Voice 301-682-7666 FAX Internet URL http://www.arius.comArticle: 23804
Since N can take only fixed, positive values, one solution comes
immediately to my mind. Let us store the reciprocals of these values in
q1.16 format. You will need 12 16-bit locations to do that.
48 = 0x0555
64 = 0x0400
212 =0x0135
220 =0x0129
228 =0x011f
424 =0x009a
432 =0x0097
440 =0x0094
848 =0x004d
856 =0x002c
864 =0x004b
752 =0x0057
Say N = recprc(i) selects one of these.
Then, N = N * X - division
N += 0x8000 - normalization
N >>= 16 - quotient
mod = X - N * X
You have two multiplications, one subtraction and one array reference
and a shift to calculate the modulo N. In some DSPs two of the first
three steps can be combined. The normalization step is same as floating
point rounding off and helps to minimize the errors that are inherent
in fixed point arithmatic.
Hope this helps.
Santosh
Christopher Malkin wrote:
>
> Hello,
>
> I was wondering whether anyone had a neat way of calculating a modulo
N.
>
> I am working on implementing an algorithm which requires me to take a
> modulo N of a 15 bit number, where N is a 10 bit number that can take
> the following values : (48, 64, 212, 220, 228, 424, 432, 440, 848,
856,
> 864, 752).
>
> I would obviously like to implement this in the most resource
economic
> way possible and am therefore hoping that there may be a trick that
will
> allow me to avoid using a division.
>
> Thanks for your ideas,
>
> Chris Malkin
Sent via Deja.com http://www.deja.com/
Before you buy.
Article: 23805I read today that Xilinx is buying LavaLogic which makes a Software to Hardware compiler, http://biz.yahoo.com/bw/000710/ca_xilinx_.html. The product seems to take Java as input and produces VHDL or Verilog as output. I don't think I would have much interest in this product, but I am concerned about all of the innovative development guppies being gobbled up by the big fish. I think it can be useful to have third party tools available to keep the main vendors on their toes. Often when a company is bought, the products are not "assimilated into the collective" but rather just end up on the floor as detritus. Anyone have an opinion? -- Rick Collins rick.collins@XYarius.com Ignore the reply address. To email me use the above address with the XY removed. Arius - A Signal Processing Solutions Company Specializing in DSP and FPGA design Arius 4 King Ave Frederick, MD 21701-3110 301-682-7772 Voice 301-682-7666 FAX Internet URL http://www.arius.comArticle: 23806
Hello, I am using AHDL to describe two counters (call them counter x and counter y). I need to trigger counter y after counter x has counted a certain number of cycles. Both counters have the same GLOBAL clock. How can I trigger counter y in AHDL ? The algorithm that I am using right now basically counts a certain number of cycles and then sets an enable output that feeds into counter y. Any help would greatly be appreciated. Thanks MikeArticle: 23807
I got some pcs of XC2018-fpga's. I'm hamradio operator and would like to realize some ideas with this fpgas. The only one problem is that the current versions of xilinx software doesnt support the xc2018. I'm therefore hardly looking for a working version of XACT5 (DOS&UNIX) or XACT6 (Windows) to buy! Anybody on the forum who could help me? Thanks a lot for thinkig about! Ottwald J.Holler Callsign OE2OHA, ex.5B4EC, ex VK4ZOH Liechtensteinklammstrasse 78 A-5600 ST.JOHANN/PG AUSTRIA - EUROPE oe20ha@eunet.at www.members.eunet.at/oe20ha/index.htmlArticle: 23808
--------------2B1C707941056AAF078A8E07 Content-Type: text/plain; charset=us-ascii Content-Transfer-Encoding: 7bit OE2OHA de AB6VU -- FB on all, Ottwald, Guten Tag. The 2018 is now obsolete, and is not being supplied. Last time buy was 2 years ago, and last time ship was last year. Pretty good for a 16 year old product. If possible, I would call your local FAE, and request samples of Spartan, or SpartanXL, or the 5200. In the development of software defined radios (SDR), we are doing work here as well. Here in the USA, the FCC has recommended that ham radio research the topic of SDR. I am confident that amateurs worldwide can lead in the development of a whole new industry. FPGA's are ideally suited to this task. Check out: http://www.xilinx.com/prs_rls/mathworksx.htm Please feel free to copy my recommendation to your local supplier. 73, es gud dx, OE2OHA de AB6VU SK AB6VU (Austin Lesea, IC Design) Your local contact: Metronik Ges.m.b.H * Diefenbachgasse 35 A- 1150 Wien Austria Tel: (43) 1-89-576-260 FAX: (43) 1-89-576-2650 E-mail: kufassmann@metronik.de Ottwald Holler wrote: > I got some pcs of XC2018-fpga's. I'm hamradio operator and would like to > realize some ideas with this fpgas. The only one problem is that the > current versions of xilinx software doesnt support the xc2018. > I'm therefore hardly looking for a working version of XACT5 (DOS&UNIX) > or XACT6 (Windows) to buy! > Anybody on the forum who could help me? > Thanks a lot for thinkig about! > > Ottwald J.Holler > Callsign OE2OHA, ex.5B4EC, ex VK4ZOH > Liechtensteinklammstrasse 78 > A-5600 ST.JOHANN/PG > AUSTRIA - EUROPE > > oe20ha@eunet.at > > www.members.eunet.at/oe20ha/index.html --------------2B1C707941056AAF078A8E07 Content-Type: text/html; charset=us-ascii Content-Transfer-Encoding: 7bit <!doctype html public "-//w3c//dtd html 4.0 transitional//en"> <html> OE2OHA de AB6VU -- FB on all, <p>Ottwald, <p>Guten Tag. <p>The 2018 is now obsolete, and is not being supplied. Last time buy was 2 years ago, and last time ship was last year. Pretty good for a 16 year old product. <p>If possible, I would call your local FAE, and request samples of Spartan, or SpartanXL, or the 5200. <p>In the development of software defined radios (SDR), we are doing work here as well. Here in the USA, the FCC has recommended that ham radio research the topic of SDR. I am confident that amateurs worldwide can lead in the development of a whole new industry. FPGA's are ideally suited to this task. Check out: <a href="http://www.xilinx.com/prs_rls/mathworksx.htm">http://www.xilinx.com/prs_rls/mathworksx.htm</a> <p>Please feel free to copy my recommendation to your local supplier. <p>73, es gud dx, OE2OHA de AB6VU <u>SK</u> <p>AB6VU <br>(Austin Lesea, IC Design) <p>Your local contact: <p>Metronik Ges.m.b.H * <br>Diefenbachgasse 35 <br>A- 1150 Wien <br>Austria <br>Tel: (43) 1-89-576-260 <br>FAX: (43) 1-89-576-2650 <br>E-mail: kufassmann@metronik.de <p>Ottwald Holler wrote: <blockquote TYPE=CITE>I got some pcs of XC2018-fpga's. I'm hamradio operator and would like to <br>realize some ideas with this fpgas. The only one problem is that the <br>current versions of xilinx software doesnt support the xc2018. <br>I'm therefore hardly looking for a working version of XACT5 (DOS&UNIX) <br>or XACT6 (Windows) to buy! <br>Anybody on the forum who could help me? <br>Thanks a lot for thinkig about! <p>Ottwald J.Holler <br>Callsign OE2OHA, ex.5B4EC, ex VK4ZOH <br>Liechtensteinklammstrasse 78 <br>A-5600 ST.JOHANN/PG <br>AUSTRIA - EUROPE <p>oe20ha@eunet.at <p>www.members.eunet.at/oe20ha/index.html</blockquote> </html> --------------2B1C707941056AAF078A8E07--Article: 23809
Bill, If you haven't already, try going to http://support.xilinx.com and typing something like "JTAG cable leads" into the Answers search field. Xilinx Answer #2576 may provide some useful information... Regards, Hobson Frater Xilinx Applications Bill Lenihan wrote: > Does anyone know a good source (& part number) for a 6-pin (power & > ground + 4 JTAG signals) 'header' that can handle the flying leads of > the Xilinx JTAG pod(s)? > > -- > ============================== > William Lenihan > lenihan3weNO@SPAMearthlink.net > ==============================Article: 23810
Hi, I have to design a mind-boggling image processor using a biggish Virtex chip. It will interface to a gang of picosecond time stampers, a big image memory, and a 68332 uP. All that I can do (fingers crossed). But I also need a block of DPM shared between the '332 and the PCI bus (in a separate chip). I can do this with a PLX or AMCC chip and a small Cypress or IDT dual-port ram, with only modest hassle. But there must be, somewhere, just what I need in a single Xilinx FPGA (slave PCI interface to dual-port RAM). Does anybody have such a design, or know where I can find it? This would seem to me to be a fairly common and useful gadget. I would expect to make a reasonable one-time payment for this, given that it will save me a chunk of time and trouble. Thanks, John jjlarkin at highlandtechnology dot comArticle: 23811
rickman wrote: > > I read today that Xilinx is buying LavaLogic which makes a Software to > Hardware compiler, http://biz.yahoo.com/bw/000710/ca_xilinx_.html. The > product seems to take Java as input and produces VHDL or Verilog as > output. > > I don't think I would have much interest in this product, but I am > concerned about all of the innovative development guppies being gobbled > up by the big fish. I think it can be useful to have third party tools > available to keep the main vendors on their toes. Often when a company > is bought, the products are not "assimilated into the collective" but > rather just end up on the floor as detritus. > > Anyone have an opinion? There is this reference, under the heading 'and a Java-to-hardware compiler.' http://www.flex-compiler.lcs.mit.edu/Harpoon/ Lots of Java, but I couldn't see the Hardware or Chip 'output' stuff - can anyone provide more info ? Since Java is a pretty bad call for embedded control, I'd have thought it made little sense as a HDL. There are C, and C++ efforts but all these 'Language to HDL' efforts have a fundamental flaw. They sound great on the surface, but they must by nature diverge from the std language specs significantly in subset/add-on that portability ( and esp. cross vendor ) will be a nightmare. If it's hard enough getting two VHDL compilers to agree, what chance is there for 'XXX arbitary subset/add-on' ? - jgArticle: 23812
I would make two recommendations to you. The first is to forget about using the XC2018 chip. This is not only no longer made, it has very little capability compared to the chips available today. Secondly, I would recommend that you not try to use a chip. Most of the FPGAs from Xilinx are only available in surface mount packages that are hard to work with compared to the other options available to a hobbiest. Instead, use a demo board available from many sources. There is a list available at http://www.optimagic.com/. See what you can find there. I saw this ad in comp.arch.embedded awhile back. I have no idea how good or bad the product is. Just make sure the chip on any board you buy is a recent one (Spartan, XC4000, Virtex, Spartan II). I recommend that you hold out for the new Spartan II which should be shipping in a month or two. ****************************************** Burch Electronic Designs FPGA Prototyping kits are now 25% cheaper. Xilinx kits are now US$66 ! The price rollback is due to the abolition of the crippling "Wholesale Sales Tax" in Australia, plus the recent streamlining of our production process. Xilinx, Altera, Atmel, Lucent and Actel kits are available. For product details, secure online shop and subscription to our free online newsletter please go to www.BurchED.com.au International orders are very welcome. Best regards Tony Burch www.BurchED.com.au ****************************************** Ottwald Holler wrote: > > I got some pcs of XC2018-fpga's. I'm hamradio operator and would like to > realize some ideas with this fpgas. The only one problem is that the > current versions of xilinx software doesnt support the xc2018. > I'm therefore hardly looking for a working version of XACT5 (DOS&UNIX) > or XACT6 (Windows) to buy! > Anybody on the forum who could help me? > Thanks a lot for thinkig about! > > Ottwald J.Holler > Callsign OE2OHA, ex.5B4EC, ex VK4ZOH > Liechtensteinklammstrasse 78 > A-5600 ST.JOHANN/PG > AUSTRIA - EUROPE > > oe20ha@eunet.at > > www.members.eunet.at/oe20ha/index.html -- Rick Collins rick.collins@XYarius.com Ignore the reply address. To email me use the above address with the XY removed. Arius - A Signal Processing Solutions Company Specializing in DSP and FPGA design Arius 4 King Ave Frederick, MD 21701-3110 301-682-7772 Voice 301-682-7666 FAX Internet URL http://www.arius.comArticle: 23813
Hello, Does anyone know how to phase lock an oscillator frequency to an 8khz reference so that an 8Mhz phase-locked clock is output? This circuit must be implemented in an fpga. In my research, I have found many digital pll's that will lock two signals of the *same* frequency. Also thought I might be able to step up the 8khz to 8Mhz, but in doing so would create a phase difference. Any thoughts? tia -sue Sent via Deja.com http://www.deja.com/ Before you buy.Article: 23814
It could be any convenient type of memory. It is usually EPROM, but as the app note describes later, "RAM can be used instead of the EPROM in this design. This would allow the CPLD/FPGA devices to be programmed and tested remotely via modem, using remote control software written by the user." Eric L wrote: > In Xilinkx Appnote XAPP058 it says it requires a "Xilinx Data Memory". Is that > just static RAM? > > Thanks > Eric -- Marc Baker Xilinx Applications (408) 879-5375Article: 23815
I have done designs like this. The solution is to divide the output of VCO by the ratio of input to output to get a clock which you can give to the phase & frequency detector. Of course you need a nice loop filter in a design where the divider is as large as 1000. sriley <sueriley@my-deja.com> wrote: >Hello, > >Does anyone know how to phase lock an oscillator frequency to >an 8khz reference so that an 8Mhz phase-locked clock is output? >This circuit must be implemented in an fpga. > >In my research, I have found many digital pll's that will >lock two signals of the *same* frequency. Also thought I >might be able to step up the 8khz to 8Mhz, but in doing so >would create a phase difference. Any thoughts? > >tia > >-sue > > >Sent via Deja.com http://www.deja.com/ >Before you buy.Article: 23816
In article <8j044c$8d8$1@nnrp1.deja.com>, One thing to do is to ensure that the clock skew is lower by putting it on a global resource ( one of the six available on the 10KEs). -- Vivek iglasner@my-deja.com wrote: > Hi, > > While I belive all FPGA vendor will work properly when you connect > directly FF to FF inspite of this warning, when it come to asic we > simple add buffer between the two FF's. > > So you might want to do this, as it will not effect the design and will > remove this msg. (of course you might need two buffers or on the other > hand use a smaller buffer, just choose a one that his time (min) delay > is a bit more than what the msg complain). > > have a nice day > > Illan > > In article <39483ea7.0@news.cyberway.com.sg>, > "MK Yap" <mkyap@REMOVE.ieee.org> wrote: > > Hi!! > > > > " Error: Delay path from '|bsp_in:73|bytedata_2_.Q' to > > '|bsp_in:73|intdata_2_.Q' is 4.2ns, but Clock skew is 2.9ns and hold > time > > required for '|bsp_in:73|intdata_2_.Q' is 1.4ns - circuit cannot > operate > > because Clock skew plus hold time of destination register exceeds > > register-to-register delay " > > > > I encounter this problem when i've finished compiling the project & > doing > > the timing analysis. Most of the time, my design did not give me this > error > > mesg but it happened ocassionally. I changed other part of the > circuit but > > did not make any changes on the bsp_in portion. What can I do to > ensure this > > won't happen again? How can i put any constraint and where i should > put it? > > Thanks. > > > > I'm using Maxplus2 9.3 & Synplify 5.3.1 for my VHDL codes, running on > PC, > > targetted at flex10k30e. > > Pls advice > > > > MK > > > > > > Sent via Deja.com http://www.deja.com/ > Before you buy. > Sent via Deja.com http://www.deja.com/ Before you buy.Article: 23817
sriley wrote: > > Hello, > > Does anyone know how to phase lock an oscillator frequency to > an 8khz reference so that an 8Mhz phase-locked clock is output? > This circuit must be implemented in an fpga. > > In my research, I have found many digital pll's that will > lock two signals of the *same* frequency. Also thought I > might be able to step up the 8khz to 8Mhz, but in doing so > would create a phase difference. Any thoughts? > > tia > -sue For an example in CMOS logic, look at http://www-us.semiconductors.philips.com/pip/HEC4750VDB From this you can see the elements of a phase lock system ( Freq Synthesizer) are - Voltage Controller Oscillator - Phase Comparitor(s) - Frequency divider(s) In your case, you need to divide 8.000MHz VCO out, by 1000 to give 8.000KHz, to compare with the referance, and control the VCO with the error of this phase-compare. - jgArticle: 23818
"Jim Granville" <jim.granville@designtools.co.nz> wrote in message news:396A31CC.35C2@designtools.co.nz... > There are C, and C++ efforts but all these 'Language to HDL' efforts > have > a fundamental flaw. They sound great on the surface, but they must by > nature > diverge from the std language specs significantly in subset/add-on > that portability ( and esp. cross vendor ) will be a nightmare. I don't think that's necessarily so true of a C++ based "HDL library" (or a Java one for that matter, although I don't know enough about Java to say for certain). C++ is flexible enough that you can model hardware in it pretty darned well, I think, and provides for much better software/hardware co-verification. On the other hand, I have pretty severe reservations about the kind of people who write stuff like FPGA Express trying to write C++ class library to net list converters. Granted, synthesizing hardware is a rather complex task, but so is building a C++ compiler, and the guys at Microsquish sure seem to end up with better quality programmers than Synopsys did. (Or maybe they just have so many more...?) > If it's hard enough getting two VHDL compilers to agree, what chance is > there for 'XXX arbitary subset/add-on' ? That's fair criticism, and as VHDL shows, having an IEEE committee step in and standardize an HDL doesn't always produce the best results either. (Usable, yes. High snoot, no.) ---Joel KolstadArticle: 23819
In article <39697141.1D544F50@earthlink.net>, lenihan3weNO@SPAMearthlink.net wrote: > Does anyone know a good source (& part number) for a 6-pin (power & > ground + 4 JTAG signals) 'header' that can handle the flying leads of > the Xilinx JTAG pod(s)? I use ordinary square pin single-row header strips, and cut off the pins I need. They are available from several suppliers in the UK, like RS Components and Farnell. Leon -- Leon Heller, G1HSM Tel: (Mobile) 079 9098 1221 (Work) +44 1327 357824 Email: leon_heller@hotmail.com Web: http://www.geocities.com/SiliconValley/Code/1835 Sent via Deja.com http://www.deja.com/ Before you buy.Article: 23820
>>>>> "rickman" == rickman <spamgoeshere4@yahoo.com> writes:
rickman> Hal Murray wrote:
Hal> I'd like to thank everybody at Xilinx for paying attention to our
Hal> comments.
Hal> Here is my attempt at what I would like on a CD or web site. These
Hal> are general comments/wishes. Xilinx actually does pretty well on
Hal> most of these items.
Hal> 1) I hate blinking/flashing crap. (and noise too)
rickman> I will second that vote.
rickman> I don't remember Xilinx having much of this on their web site,
rickman> but it doesn't hurt to mention it.
Hal> 2) I don't want to install anything or register or run JaveScript.
Hal> Your install stuff probably won't work on my machine anyway.
rickman> I agree with this 100%.
I do a lot of my surfing in lynx or w3m (text based browsers). Sites that
do follow the rules mentioned in this thread render well in both. Xilinx
would do well to use these programs as benchmarks for "have we glitzed the
site too much" and "have we put in the appropriate ALT tags". I hate it
when I have to launch Netscape/IE for a quick search. Content over glitz,
please!
Hal> 3) Please don't assume I'm running a WIntel platform. I'm not.
Hal> I consider xx.ppt and xx.doc files to be semi-useless. I can find a
Hal> machine to read them, but I won't bother unless I'm really
Hal> desperate.
Hal> Same for spread sheets. Please give me raw text.
Agreed. Stick with text, PDF, or Postscript please! Most docs should have
text equivalent that I can search on/ perl, sed, and awk. The next person
who sends me a .ppt file will probably receive a .fig file from me. ("Oh,
you don't have xfig?! But it's been a standard graphics format for years!"
;-> )
Hal> And self decompressing exe files are out. Please just give me the
Hal> raw file set. I'll take the space/time/bandwidth penalty.
Hal> Note that search engines can't find stuff in those strange formats.
Hal> (I like search engines - please cooperate.)
rickman> I partially disagree with this. I think that his points are
rickman> valid as not everyone runs on a Wintel architechture. But to
rickman> speed downloads sometimes a zipped (or gz'd) file is better.
rickman> This is important when accessing patches and software updates.
rickman> Please keep these as compressed files or better yet, put them
rickman> on CDs and send them out.
rickman> But in any case, please don't stop zipping these files.
Offer them both ways. In some transports mediums, the transfer rate (k/sec)
is the same for a compressed or uncompressed file. (ethernet, ISDN, etc).
But with the auto data compression built into many modems, it _may_ come
out to be a wash.
I knew one ISP who tried to pull the wool over their customers eyes on
their connectivity performance. They had a 1MB raw _text_ file that you
could download for benchmarking. My 56K modem was hitting >12kbytes/second.
Wow! I thought... at first.
Hal> 4) Please don't go wild with the graphics and color and fonts and
Hal> other toys.
rickman> I agree with this 1000%.
rickman> Please try to keep the graphic content of your web pages and
rickman> PDF files minimal and functional. It is just not useful to
rickman> "marketize" anything where the primary purpose is to convey
rickman> information.
Agreed also. Please just lay it out so it pages quickly and I can find what
I want with a quick search, either by eyeball or with the file viewer's
search function. If you _do_ make a big pdf file, use links on the table of
contents entries and perhaps an index.
--
Scott Bilik VAutomation Inc.
http://www.vautomation.com 402 Amherst St #100
(603) 882-2282 x24 Nashua NH 03063
Article: 23821EDA ADMINISTRATOR This is a newly created role which is central to the creation of an EDA group at our client’s Global Centre of Excellence in Birmingham. The successful candidate will assist in building a new EDA team of 4-5 Engineers. This group will sit above the project teams and support large numbers of design projects totalling around 400+ engineers. This support will involve training, assisting complex design work, introducing and developing new tools. This challenging role provides technical support in all areas of ASIC and FPGA development. The job encompasses all aspects of administering and managing a complex electronic design automation infrastructure based on verilog in a distributed Sun-Solaris environment headquartered in Birmingham. The role is hands-on and proactive. In addition to day-to-day support, the successful candidate will be capable of taking the initiative to find and promote solutions related to EDA issues and development policies as they arise. email; jcrump@alphatec.uk.com * Sent from AltaVista http://www.altavista.com Where you can also find related Web Pages, Images, Audios, Videos, News, and Shopping. Smart is BeautifulArticle: 23822
Hi, We have recently started desinging using Verilog and I have a question regarding the timing simulation. Altera FPGAs (10KE series) is used for the most part. The design flow is as follows: 1. Write code in Verilog 2. Functional simulation using VCS (Synopsys Verion 5.1NT running on an NT workstation) 3. Synthesis using Synplify. 5. Place and route using Max+PlusII 9.6 I have not been able to perform the full chip timing simulations very effectively. After synthesis, Synplify changes a _lot_ of internal nodenames and I have not found a way to observe the timing between some of these signals. Is there a way this can be performed with the above set of tools? I would appreciate any help from someone who has used the .vo file generated by Max+Plus II for timing simulation of the whole design. I am running into situations where the functional simulations (with phantom delays in combinational statements) are fine, but the synthesized design doesnot work on the bench. I also need the timing simulation to accurately estimate the top speed of the design. Thanks, -- Vivek Sent via Deja.com http://www.deja.com/ Before you buy.Article: 23823
Hi, We have recently started desinging using Verilog and I have a question regarding the timing simulation. Altera FPGAs (10KE series) is used for the most part. The design flow is as follows: 1. Write code in Verilog 2. Functional simulation using VCS (Synopsys Verion 5.1NT running on an NT workstation) 3. Synthesis using Synplify. 5. Place and route using Max+PlusII 9.6 I have not been able to perform the full chip timing simulations very effectively. After synthesis, Synplify changes a _lot_ of internal nodenames and I have not found a way to observe the timing between some of these signals. Is there a way this can be performed with the above set of tools? I would appreciate any help from someone who has used the .vo file generated by Max+Plus II for timing simulation of the whole design. I am running into situations where the functional simulations (with phantom delays in combinational statements) are fine, but the synthesized design doesnot work on the bench. I also need the timing simulation to accurately estimate the top speed of the design. Thanks, -- Vivek Sent via Deja.com http://www.deja.com/ Before you buy.Article: 23824
I've been using Synplify and max+2 with this methodology very succesfully. The issue is during optimization names get changed, wires get optimized out, inferred registers get suffixes added to their names; this is normal for any synthesis tool. But it is possible to deal with them. If .vo file doesn't work, you have a problem. It could be related to incorrectly designed verilog which doesn't synthesize the way you intended to or it could be one of many potential RTL-gatelevel simulation inconsistencies. You should be able to fix these problems relatively easily. Just look at some waveforms and try to figure out whether a state machine is incorrectly initialized, or an X is propagating etc. These are normal gate-level problems. For speed, I'd suggest running Max+2 timing analyzer. Its output will tell you how fast your system is going to run and what the longest paths are. Usually max+2 static timing analyzer is better then synplicity in predicting timing. hope this helps. khanzode@yahoo.com wrote: >Hi, > >We have recently started desinging using Verilog and I have a question >regarding the timing simulation. Altera FPGAs (10KE series) is used for >the most part. > >The design flow is as follows: > >1. Write code in Verilog > >2. Functional simulation using VCS > (Synopsys Verion 5.1NT running on an NT workstation) > >3. Synthesis using Synplify. > >5. Place and route using Max+PlusII 9.6 > >I have not been able to perform the full chip timing simulations very >effectively. > >After synthesis, Synplify changes a _lot_ of internal nodenames and I >have not found a way to observe the timing between some of these >signals. Is there a way this can be performed with the above set of >tools? I would appreciate any help from someone who has used the .vo >file generated by Max+Plus II for timing simulation of the whole design. > >I am running into situations where the functional simulations (with >phantom delays in combinational statements) are fine, but the >synthesized design doesnot work on the bench. I also need the timing >simulation to accurately estimate the top speed of the design. > >Thanks, > >-- Vivek > > >Sent via Deja.com http://www.deja.com/ >Before you buy.
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