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iddw@hotmail.com (Dave Hansen) writes: > My goodness, this got crossposted far and wide, did it not? I'd > adjust the f'ups, but I don't know where to put it... I'll say alt.dev.null is the most appropriate one. Follow-up set. Bye, Dragan -- Dragan Cvetkovic, To be or not to be is true. G. Boole No it isn't. L. E. J. BrouwerArticle: 55451
Harald wrote: > I will start my first FPGA Design. We have a software named Protel DXP > von Altium. Have anybody experience with this Software? Thanks. Even though I have it, my experience is zero. I explored the FPGA possibilities in the newsgroup though . Protel lets you design a netlist but for the routing the actual FPGA manufacturers tool is required. Protel somehow exports the netlist. I haven't seen it yet, it sounds great, it sounds bold, I doubt it. You should ask this question in the DXP newsgroup for a more reliable answer. Rene -- Ing.Buero R.Tschaggelar - http://www.ibrtses.com & commercial newsgroups - http://www.talkto.netArticle: 55452
Hello Joachim, I cannot talk about SystemC, we have used ANSI-C and Handel-C to design systems. The Handel-C describes the hardware and the results were very good. The conversion of the C was easy and if you want you can output VDHL and Verilog from the C description, or output direct EDIF to the FPGA. This was efficient and easier. http://www.celoxica.com/tech/design_suite/default.asp Good luck. Lina mail@joachim-becker.de (Joachim) wrote in message news:<e2ea7846.0305080153.2775674e@posting.google.com>... > Hello, > > We are using a PCI-Card with Virtex-300E FPGA and have both C and VHDL > Code for the whole system. We fancy switching to systemC but I am not > yet sure that a direct conversion of our VHDL Code to SystemC is > possible. We would do it manually but only if we can be sure that the > whole system of software and hardware is then implemented in systemC. > > > But what about the hardware-part of the system? > Is there a way to compile / synthesize RTL-SystemC Code directly to a > bitstream that can be downloaded to the FPGA just liek we are used to > it with VHDL? Is it possible for Virtex-II only or also the older > FPGAs? > > Thanky you for your help, > JoachimArticle: 55453
Heya, There was a serious flaw in the 1K50 and 10K50 RAM timing models in MaxPlusII 10.12, namely that the data delay was internally expressed in ns instead of ps (i.e. too slow by a factor of 1000). I ran into this when all of a sudden a design had a 300KHz FMAX instead of 17MHz. I suggest you either stick with 10.1 or migrate to 10.2. Haven't had any problems with 10.2, except when intalling the programmer-only version. However, there's a patch for that as well somewhere on the Altera FTP site. As to your installation problems I suggest that you just uninstall the whole thing and start again. Best regards, Ben "FPGA user" <nospam@aol.com> wrote in message news:e2gua.770924$F1.97691@sccrnsc04... > Hi Ian, > > That makes good sense to split it up, from a fitting standpoint. I tried > it, and unfortunately, it did the same thing with 8-bit words. > > I've been corresponding with an Altera cust support person, and when she > compiled my test design, it worked. She sent me her compilation and I > recompiled it with no changes to the settings, and it was still bad. She > told me to upgrade to the latest version (I'm using 10.12; the latest is > 10.22). From what I could tell on their download site, you can't upgrade to > 10.22 from 10.12. But I did anyway, and it trashed the installation :-( I > had to do a complete reinstall... and no, it still didn't work. > > So if I get this figured out, I'll post the results. > > > Thanks, > > Dan Vincent > > > > > "Ian McCrum, MI5AFL" <IJ.McCrum@ulst.ac.uk> wrote in message > news:3eb8c52d.1434342@news.ntlworld.com... > > On Sun, 04 May 2003 18:26:28 GMT, "FPGA user" <nospam@aol.com> wrote: > > > > >Hi, > > > > > >Has anyone used LPM_ROM megafunctions in an EP1K50? They do NOT seem to > > >work in simulation. However, an EP1K30 or an EP1K100 DOES work. > > > > > >I'm using the latest version of MaxPlus II, and created a design with > only > > >that megafunction, unclocked, with addr in/data out ports, and an > > >initialization file. I organized the part as 64 16 bit words. > > > > > >Compilling and changing nothing but the device shows up the problem. > > > > > > > > >Thanks! > > > > > > > > I have used LPM_ROM for a large(wide) microcode design, I recall it > > fitted/worked better if I split the ROMs into 8 bit chunks, so two > > 64x8 roms may be better. I think I retrospectively read something in > > the altera literature to do this ... YMMV > > > > Email me if still having probs as I probably have old code on my > > website www.eej.ulst.ac.uk try IJ.McCrum as my email username and > > ulster.ac.uk ad my email domain. > > > > Regards > > Ian McCrum, MI5AFL > >Article: 55454
You can build interesting stuff with FPGAs with only a few hours a week... "Ray Andraka" <ray@andraka.com> wrote in message news:3EB9A1CA.FF70A83C@andraka.com... > So why are you worried about getting an FPGA in a Dip40 package then anyway??? > > Torquemada wrote: > > > > It shouldn't take you more than a week or so worth of nights and weekends > > to > > > get a netlist and layout package together for a board house to produce it. > > > > I'm not single any more. I don't get weekends and nights :-) > > -- > > Torque > > -- > --Ray Andraka, P.E. > President, the Andraka Consulting Group, Inc. > 401/884-7930 Fax 401/884-7950 > email ray@andraka.com > http://www.andraka.com > > "They that give up essential liberty to obtain a little > temporary safety deserve neither liberty nor safety." > -Benjamin Franklin, 1759 > >Article: 55455
I checked with the marketing manager: The XCF-series PROMS are available in their 1, 2, and 4 Mb flavor, commercial speed grade, as Engineering Samples (ES). Bigger parts later this year. ES is really a badly misleading name, for these are full-fledged 100% tested parts, but they have not yet passed all their qualification torture tests (bake-in, etc). Distributors tend not to stock ES parts, but they can accept orders. I thought you might be interested. Peter Alfke, Xilinx Applications ============ Lorenzo Lutti wrote: > > I've found these preliminary specifications in the Xilinx site: > > http://direct.xilinx.com/bvdocs/publications/ds123.pdf > > Do you know if these devices are already in production? If not, when > will they be (hopefully :))? > > -- > LorenzoArticle: 55456
Surely, you can put together a netlist for a board in a few hours too, no?
Basically you are looking at what, maybe 50 nets, a 44 pin FPGA, a couple of
capacitors, a serial prom and 2 20 pin sip headers. It is small enough that you
could probably do the netlist by hand
Torquemada wrote:
> You can build interesting stuff with FPGAs with only a few hours a week...
>
> "Ray Andraka" <ray@andraka.com> wrote in message
> news:3EB9A1CA.FF70A83C@andraka.com...
> > So why are you worried about getting an FPGA in a Dip40 package then
> anyway???
> >
> > Torquemada wrote:
> >
> > > > It shouldn't take you more than a week or so worth of nights and
> weekends
> > > to
> > > > get a netlist and layout package together for a board house to produce
> it.
> > >
> > > I'm not single any more. I don't get weekends and nights :-)
> > > --
> > > Torque
> >
> > --
> > --Ray Andraka, P.E.
> > President, the Andraka Consulting Group, Inc.
> > 401/884-7930 Fax 401/884-7950
> > email ray@andraka.com
> > http://www.andraka.com
> >
> > "They that give up essential liberty to obtain a little
> > temporary safety deserve neither liberty nor safety."
> > -Benjamin Franklin, 1759
> >
> >
--
--Ray Andraka, P.E.
President, the Andraka Consulting Group, Inc.
401/884-7930 Fax 401/884-7950
email ray@andraka.com
http://www.andraka.com
"They that give up essential liberty to obtain a little
temporary safety deserve neither liberty nor safety."
-Benjamin Franklin, 1759
Article: 55457I want to measure the instantaneous power consumption of the internal core of an FPGA. Does anybody know of any testboards where one can do this? Like do there exist testboards where I can directly supply this voltage myself and measure the current through the lines. Or maybe there are boards where there are or can be put small resitances in the the supply lines just before the FPGA. Thanks!Article: 55458
The ISI Osiris board has a monitor port in the regulator circuit that could be
used to monitor current I think. You'd have to write an application to use it
though.
kris wrote:
> I want to measure the instantaneous power consumption of the internal core
> of an FPGA. Does anybody know of any testboards where one can do this? Like
> do there exist testboards where I can directly supply this voltage myself
> and measure the current through the lines. Or maybe there are boards where
> there are or can be put small resitances in the the supply lines just before
> the FPGA.
>
> Thanks!
--
--Ray Andraka, P.E.
President, the Andraka Consulting Group, Inc.
401/884-7930 Fax 401/884-7950
email ray@andraka.com
http://www.andraka.com
"They that give up essential liberty to obtain a little
temporary safety deserve neither liberty nor safety."
-Benjamin Franklin, 1759
Article: 55459>I want to measure the instantaneous power consumption of the internal core >of an FPGA. Does anybody know of any testboards where one can do this? Like >do there exist testboards where I can directly supply this voltage myself >and measure the current through the lines. Or maybe there are boards where >there are or can be put small resitances in the the supply lines just before >the FPGA. It's a hard problem. Maybe even very hard. What do you mean by "instantaneous"? Microsecond? Nanosecond? Do you want to measure an existing design, or do you want to write code and try various things? How hard are you willing to work and/or how much are you willing to pay? What sort of tools/equipment do you have? The small resistors you suggested are not common. Where would you put them? Between the FPGA and the bypass caps? Then you get crappy bypassing. If you put them just outisde the caps, then you can't measure the high speed currents because the bypass caps hide it from you. For a low cost project, I'd suggest setting things up so you don't need to measure the "instantaneous" power. Then you can measure it in the obvious way, say with a meter between the power supply and your board. (Doesn't work if the regulators are on the board.) But now you have to write some code to do things that are interesting to measure, and do it for long enough so that you can measure it. -- The suespammers.org mail server is located in California. So are all my other mailboxes. Please do not send unsolicited bulk e-mail or unsolicited commercial e-mail to my suespammers.org address or any of my other addresses. These are my opinions, not necessarily my employer's. I hate spam.Article: 55460
Go to http://www.xilinx.com/xlnx/xil_prodcat_landingpage.jsp?title=Aurora . The Aurora protocol is free and Xilinx has a free VHDL design that implements it. Steve Virtual Computer Corp. "Andreas Wortmann" <wortmann@informatik.hs-bremen.de> wrote in message news:b980gv$sh2$1@hermes1.rz.hs-bremen.de... > hi, > > i start using the rocket-io transceiver macro on the xilinx virtex-II pro > device. does anybody have > - or know of - some simple sample vhdl-code to start out with ? at this > stage i do not aim at a specific > transmission protocol, but i want to prove the device working. are there > other important things i have > to account for ? > > thanks, > andreas > >Article: 55461
Hi, I am just wondering why the following App-notes are missing on the Xilinx web page: Using the XC4000 RAM Capability (XAPP 031) and High-Speed RAM design in XC4000 (XAPP 042) Can someone point me to those ANs? Thank you, JDSArticle: 55462
[TQFP/BGA to DIP adapter cards] >It shouldn't take you more than a week or so worth of nights and weekends to >get a netlist and layout package together for a board house to produce it. You >might talk to a few board houses first to get pricing as well as options for >input format. Some only work with specific board layout packages, others are >far more flexible. Some will even do the netlist capture for an additional >fee. I have some data that might help... I recently built a small 2 layer board. I used Eagle and PCBExpress. Friends had suggested that combination and reported happiness. (And Eagle runs on Linux.) PCBExpress is $80 (plus shipping/tax) for 2 boards. $11 each for a batch of 20. That's for up to 9 sq inches, so you could get several per board if you are willing to cut them up yourself. It took me a week or so. Half of that was learning Eagle. The other half was finding/selecting the parts I needed. If I had a good sketch for specs, I could probably do an adapter board in a short day. (Mumble about Hoffsteader.) The low cost board shops typically don't go down to tiny lines. PCBExpress is 7/7 mils. That seems fine for TQFP but it would be tough for BGAs. Their 4 layer package is 6/6. I'm a nut about solid power/bypassing. I don't quite have a picture of how to get that with a 2 layer board, especially if there is a separate core supply needed. I think I'd try something like put all the signals on the top. On the bottom, put a ground ring around under the pads. Two more rings around inside/outside that for power. Caps go between the rings. That would need vias to connect power/gnd pins to the rings. The signals for the ring on the inside would route through the pads they connected to. I can't picture how to do a BGA in two layers. Might be possible if the power pins work out right and/or you only need to connect to the two outside rows of signal pins. Again, I'm thinking of power and caps on the bottom. XAPP157 doesn't cover this case. :) I'd have to check which pins are core power and which are IO power. I have a list of low cost PCB vendors. I'll fish it out if anybody is interested. (I didn't save the ones that required a MS box to run their software.) Anybody know any good low volume, low cost assembly houses? I'm looking for a place that will install BGAs or PQFP/TQFPs. I can do the rest by hand but would be willing to pay for a professional job if it's not too expensive. (Preferably in Silicon Valley.) Googling for <BGA rework> gets lots of hits, including a whole column of ads on the right. I'm sure I can find something but I haven't investigated yet. PCBExpress offers solder masks and a toaster oven recipe. -- The suespammers.org mail server is located in California. So are all my other mailboxes. Please do not send unsolicited bulk e-mail or unsolicited commercial e-mail to my suespammers.org address or any of my other addresses. These are my opinions, not necessarily my employer's. I hate spam.Article: 55463
With instantaneous current I mean sampled at e.g. 250-500MHz, (4-2 ns) which would result, depending on the clock speed at 10 to 20 samples per clock cycle. I'm not interested in the mean or average power consumption. In our lab, we have some oscilloscopes available that can handle this and higher sampling frequencies. The boards that we have available now (insight virtex 2, xc2v1000 and the avnet virtex 2 development kit) both have the voltage regulators on the board itself. Can you recommend a board where I can provide vcc_int from outside the board? (I would prefer with virtex 2 devices as the design is completely finished). The hw-afx boards from xilinx seem to offer this possibility. But I cannot find the datasheets in order to confirm this and in order to see if the decoupling capacitances are already on the board or not. But by using such a board this current doesn't correspond with the current that flows into the fpga. Do only the decoupling capacitances have their influence or also the line inductances of the traces on the board? Thanks!Article: 55464
I am looking at the larger CPLDs and there seems to be a price wall between the 256 and 384 macrocell parts. Both the Xilinx and Lattice parts have about the same features and functionality and the same significant price jump. The XCR3256XL in the 256 BGA package is about $15 in moderate quantity. But the XCR3384XL in the same package is over $60!!! The same disparity (although not quite as large) exists in the Lattice LC4 line. Anyone getting the 384 parts at a price that is more in line with the size and IO count, like under $30? I can use the 256 parts if I don't mind cutting the IO and cell count down to the exact number I estimate. I just don't like the idea of not leaving room for errors or future design changes. But there is no way I can justify a 4X price differential on a part that is 50% larger and 20% more IO. If I get really tight, I might just consider the Lattice 384 cell part since it is much cheaper than the Xilinx part. But it will bug the heck out of me to pay the price. -- Rick "rickman" Collins rick.collins@XYarius.com Ignore the reply address. To email me use the above address with the XY removed. Arius - A Signal Processing Solutions Company Specializing in DSP and FPGA design URL http://www.arius.com 4 King Ave 301-682-7772 Voice Frederick, MD 21701-3110 301-682-7666 FAXArticle: 55465
rickman wrote: > > I am looking at the larger CPLDs and there seems to be a price wall > between the 256 and 384 macrocell parts. Both the Xilinx and Lattice > parts have about the same features and functionality and the same > significant price jump. The XCR3256XL in the 256 BGA package is about > $15 in moderate quantity. But the XCR3384XL in the same package is over > $60!!! The same disparity (although not quite as large) exists in the > Lattice LC4 line. > > Anyone getting the 384 parts at a price that is more in line with the > size and IO count, like under $30? I can use the 256 parts if I don't > mind cutting the IO and cell count down to the exact number I estimate. > I just don't like the idea of not leaving room for errors or future > design changes. But there is no way I can justify a 4X price > differential on a part that is 50% larger and 20% more IO. > > If I get really tight, I might just consider the Lattice 384 cell part > since it is much cheaper than the Xilinx part. But it will bug the heck > out of me to pay the price. You could use two smaller parts ? - We've done that in the past. Or, maybe move away from the bleeding-edge of a family. Lattice made this claim in July 2002, you could check into : ( this family goes 256/512/768/1024, so 256/512 is at the small end of the ruler :) > Price and Availability > The ispXPLD 5512MX in the 1.0mm ball pitch, 484 fpBGA package will sample later this quarter >with initial production scheduled for Q4. Pricing for the ispXPLD 5512MC in volumes of >1000 >pieces starts at $17.75. Additional members of the ispXPLD 5000MX family are expected to be >released over the coming year. -jgArticle: 55466
Have you looked at XAPP623 and similar documents? Are you familiar with Johnson and Graham's Black Magic book? (If you want to do this sort of measurement, you need to sleep with it under your pillow.) >With instantaneous current I mean sampled at e.g. 250-500MHz, (4-2 ns) which >would result, depending on the clock speed at 10 to 20 samples per clock >cycle. I'm not interested in the mean or average power consumption. I think that's going to be hard to measure at that time scale. >In our lab, we have some oscilloscopes available that can handle this and >higher sampling frequencies. > >The boards that we have available now (insight virtex 2, xc2v1000 and the >avnet virtex 2 development kit) both have the voltage regulators on the >board itself. Can you recommend a board where I can provide vcc_int from >outside the board? (I would prefer with virtex 2 devices as the design is >completely finished). The hw-afx boards from xilinx seem to offer this >possibility. But I cannot find the datasheets in order to confirm this and >in order to see if the decoupling capacitances are already on the board or >not. What good is a board without bypass caps? (Why would anybody build or ship one?) You can unsolder the regulator chip and provide your own core power, perhaps including a small sense resistor. I'd probably put a big cap with low ESR on the non-FPGA side of the sense resistor to make sure the wires over to the power supply don't confuse things. This gets you closer to the chip. Or perhaps you can just lift the leg on the regulator chip and insert a sense resistor between leg and board. Can you single step your design? (Or patch it so you can?) You might get some info by watching the voltage as you kick the clock. You would get a bigger signal if you let it run for 10 cycles. You can also make the signal bigger by removing some of the bypass caps. If you can measure a step change on a single clock, then you can compute the charge that got pulled out of the bypass caps and convert that back to current at a given clock rate. That's assuming the regulator chip doesn't have time to change the amount of current it is providing. That's probably valid, but check the step response graphs in the data sheet. >But by using such a board this current doesn't correspond with the current >that flows into the fpga. Do only the decoupling capacitances have their >influence or also the line inductances of the traces on the board? Generally, the whole idea of the power supply system is to avoid inductances in the power/ground signals so the bypass caps will do their job. -- The suespammers.org mail server is located in California. So are all my other mailboxes. Please do not send unsolicited bulk e-mail or unsolicited commercial e-mail to my suespammers.org address or any of my other addresses. These are my opinions, not necessarily my employer's. I hate spam.Article: 55467
Greetings everyone, Following are some basic (novice) questions I have regarding an application I am planning to experiment with: Project: The motivation is to design an FPGA which has an embedded web services technology in it. I have some light weight C++ code which I have ported on uCLinux/ARM core and would like to deploy on NIOS or Xilinx platform. The software requires launching network listeners (e.g., web server) along with application processes. The software needs a read/writable flash of around 32-64 Mb. The size of the FPGA needs to be small so that it can be embedded in PDAs. 1) Is it logical to design an FPGA for this project? If yes, what hardware, software combinations can be used? 2) What factors should I evaluate in choosing the right hardware platform for development? Is uCLinux OS the best way to go for Altera or Xilinx platforms or is there a better lightweight OS suitable for such an application? 3) So the requirements are FPGA core + flash + RAM + network. Who are some of the manufacturers of such boards with a small size footprint? 4) Eventually, how will an ASIC be derived from such a system? All answers are appreciated. Thank you. with regards, Bobby Sardana. sardana@obsoft.comArticle: 55468
Bobby Sardana wrote: > Greetings everyone, > > Following are some basic (novice) questions I have regarding an > application I am planning to experiment with: > > Project: > > The motivation is to design an FPGA which has an embedded web services > technology in it. I have some light weight C++ code which I have ported > on uCLinux/ARM core and would like to deploy on NIOS or Xilinx platform. > The software requires launching network listeners (e.g., web server) > along with application processes. The software needs a read/writable > flash of around 32-64 Mb. The size of the FPGA needs to be small so that > it can be embedded in PDAs. Hi Bobby, > 1) Is it logical to design an FPGA for this project? If yes, what > hardware, software combinations can be used? I'm not sure whether I understood you correctly. If you just need something with an "embedded web service", i.e. to access the contents of a Flash EEPROM, an FPGA would be some overkill. One uses FPGAs usually when special hardware is required. You should better have a look at some processors for embedded applications. They have mostly integrated all the stuff required - for instance glueless interface to Flash etc. > 2) What factors should I evaluate in choosing the right hardware > platform for development? Is uCLinux OS the best way to go for Altera or > Xilinx platforms or is there a better lightweight OS suitable for such > an application? Assuming you have common CPU (or CPU core), I think embedded Linux or uCLinux are the best (cheapest) solutions. But I have not yet any experience with either of them. > 3) So the requirements are FPGA core + flash + RAM + network. Who are > some of the manufacturers of such boards with a small size footprint? For FPGAs I don't know, but you could build one by yourself quite easily. For embedded processors there are a lot. Have a look at that, for instance: http://www.embeddedplanet.com > 4) Eventually, how will an ASIC be derived from such a system? Assuming you really choose an FPGA and make your design in some HDL, you would more or less simply synthesize the design for the ASIC rather the FPGA. Of course, in reality some small adaptions might be required. Regards, MarioArticle: 55469
We want to use the encrypted bitstream option of a Xilinx FPGA in order to protect IP. However we are having trouble sourcing a suitable battery. Our product needs to have a shelf life of 10 years plus. The customer might stick the unit on a shelf in a cold dark warehouse and not use the product for several years, but it must still work. If it fails on operation that has very expensive consequences for our customers - and us. Has anybody found a suitable battery for this? Are there any alternative way to encrypt the FPGA bitstream? The bitstream and any keys must not be accessible to any probes. Many thanks, -- JP Nicholls / jpnicholls@pwav.com Digital design engineer Powerwave UK Ltd Embassy House Queen's Avenue Bristol, BS8 1SB United Kingdom Tel: +44 (0)117 910 5600 Fax: +44 (0)117 910 5601 Web: http://www.powerwave.com ___________________________________Article: 55470
Jan Panteltje wrote: > 5 on an Euro card 160 x 100 mm > 10 cards in a 19 inch rack. > For my brute force key cracker. Jan, I am also a fan of the Eurocard format. When I was shopping for an FPGA dev board, I found a manufacturer who was just about to start designing his 2nd generation product. So I told him what I would like and he took on my ideas. So I got pretty much a custom board! :-) See http://www.howell1964.freeserve.co.uk/logic/burched/fpga_devkit_b5.htm for a board that will slide in a Euro-rack. 100 mm wide, but 5.4" = 137 mm long. This allows it to mate with a prototyping board fitted with the kind of sockets used on PC104 cards (I bought some 2x23 way ones, cut them into three 2x10 way), like this: http://www.howell1964.freeserve.co.uk/logic/acorn_atom_project.htm I reckon you could ask BurchEd to fit such connectors at manufacture. If you are buying many (sounds like you would need to) you could perhaps then 'stack' them like PC104 cards. You would have to take off the links that route power to the 20-way headers so that they don't short their power rails together! This stack might remove the need for any kind of backplane in your rack. You might just need the one base board to stuff data in and out. Your spec adds up to a count of 800k x 50 per rack. The BurchEd has a 300E part, so you would need 134 such boards split among a dozen or so racks. FPGA's dedicated to one specific task like yours have been used to search DNA sequences for genome mapping projects. Literally hundreds of times faster than GHz desktops! You might have a look to see if you can buy/borrow/rent such machines from people who manufacture them. On the other hand, those people market their machines as some kind of miracle, and probably price them to match. The quintessence is just pumping the search sequence shift registers and xor-gates to detect shorter fragments. Cheers, Keith.Article: 55471
I want to build a proto board with a small CPLD (eg XL9536) and a Microchip PIC (eg 16F877, 18F452). The PICs range in speed from 0..40Mhz. Whatever their clock speed they dispatch instructions at Fosc/4 (which is available as an output if an external oscillator is used (rather than using a crystal or resonator directly)). What would be the best way to generate clocks for these two parts? For some clock ratios synchronization is probably moot. But it would be nice to (say) run the PIC at 25Mhz (6.25 MIPS) and have some multiple of that available to the CPLD, say 62.5Mhz. -- Ben Jackson <ben@ben.com> http://www.ben.com/Article: 55472
Ben Jackson wrote: > I want to build a proto board with a small CPLD (eg XL9536) and a > Microchip PIC (eg 16F877, 18F452). The PICs range in speed from > 0..40Mhz. Whatever their clock speed they dispatch instructions > at Fosc/4 (which is available as an output if an external > oscillator is used (rather than using a crystal or resonator > directly)). > > What would be the best way to generate clocks for these two parts? > For some clock ratios synchronization is probably moot. But it would > be nice to (say) run the PIC at 25Mhz (6.25 MIPS) and have some > multiple of that available to the CPLD, say 62.5Mhz. You could feed the CPLD with a high frequency and let the it generate the clock for the PIC. The higher you choose the CPLD frequency, the more choices you have for the PIC frequency. You might also arrange it in that way, that the majority of your CPLD is not clocked by this rather high frequency, but as well by a derived clock. Regards, MarioArticle: 55473
Hi I'm a PhD student and have to buy a fpga development kit(board, chip, and software) that will be used by students of Electonic Engineer. I need a little suggest about it. The development kit must be simple to use for programming and debug and not very expensive. I'd like that the software included was able to simplify the configuration of the connections of the board and that the debug of the chip could be done by the software. An Altera reseller proposed me the Nios development kit, but I think it is difficult to use for the students. What do u think about it? There is a good product by Xilinx? Thanks for the answer.Article: 55474
"Giando" <GOTEB@katamail.com> wrote in message news:1402ce4.0305090536.2dd72fa@posting.google.com... > Hi I'm a PhD student and have to buy a fpga development kit(board, > chip, and software) that will be used by students of Electonic > Engineer. I need a little suggest about it. The development kit must > be simple to use for programming and debug and not very expensive. I'd > like that the software included was able to simplify the configuration > of the connections of the board and that the debug of the chip could > be done by the software. > An Altera reseller proposed me the Nios development kit, but I think > it is difficult to use for the students. What do u think about it? > There is a good product by Xilinx? > Thanks for the answer. www.digilentinc.com http://www.digilentinc.com/Catalog/digilab_2e.html also have a couple of IO boards and a breadboard which can be plugged in. http://www.digilentinc.com/Catalog/peripheral_boards.html They also make the xilinx coolrunner2 design kit board. Could also have a look at www.xess.com and follow the links on the xilinx site to boards. Alex
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