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Hi all, If you look at the mapped netlist then the lut's are defined as defparam NameOfLut.INIT=16'hE4E4; does anybody know how the INIT defines the functionality of the LUT. In other words what does E4E4 mean? KrisArticle: 57351
On Fri, 27 Jun 2003 18:38:14 -0700, kris wrote: > Hi all, > If you look at the mapped netlist then the lut's are defined as defparam > NameOfLut.INIT=16'hE4E4; > does anybody know how the INIT defines the functionality of the LUT. In > other words > what does E4E4 mean? > Kris It's the hex value of the 16 bits in the LUT RAM.Article: 57352
Naveed wrote: > > Hello, > > I have used both Xilinx and Altera extensively. > > Xilinx: Virtex, VirtexE, VirtexII (but not pro) > Altera: CPLDS, 10K, 10KA, 10KE, 6K, Cyclone (but not Apex, or Stratix) > > here's my thoughts: > > If you are designing a high speed logic (above 100Mhz core), Altera > might be risky. Xilinx software helps you squeeze the last 0.1ns off > of your chip. In xilinx, you can route each and every net manually. > Altera's floor planner is a joke when compared to xilinx. And, Altera > does not even have FPGA editor (for manual tweeking). > > If you are using a lot of small shift registers and memory, xilinx > lets you convert LUT into RAM. No such feature in Altera. > > For all other designs, consider using Altera. Altera's parts are > cheaper and readily available. I just love the fact that Altera has > fix pricing on 6K and Cyclone, whether you buy 1, or 100. Xilinx just > started competing with Altera on pricing. Two years ago, I would use > Altera in any low-cost solution, if the speed wasn't too high. With > Spartan2/3, I now, do consider xilinx. Of course everyone's experiences are different, but I don't think Altera always has great pricing either. Try getting a good price on the ACEX family. I have tried and so far all I get is list price. I was told that even if they go over two columns in the qty vs. price chart, the price only drops 10%. I have one last shot at getting a decent price, but so far it does not look good. > Altera's software is more user friendly. With Quartus, I am not that > sure, but I don't think there ever have been a better CAD tool than > Maxplus2. For quick and dirty digital design, I will always stick > with Altera, as long as they have MaxPlus2. This is the other bone I would pick. I have only done one project with MaxPlus2, but it nearly ruined my career, and I don't mean that lightly. There is a problem with timing analysis in a densely populated 10K100A part so that the chip will not meet timing even though the tool says it will. We could not get the attention of tool support because this chip is no longer supported in any real sense. They brought all the other, newer versions of the 10K parts into Quartus, but not the 10KAs. So we had to write our own constraints generation scripts and play all sorts of games including temperature testing of each design we generated to get a product out the door. > As far as technical support go, both companies suck (probably Altera > sucks more than xilinx). They normally hire fresh college graduate > for support, and those kids can't answer much. > > I am not complaining, as I work for small company. I am sure Cisco > probably gets better support. I do understand that. I know that companies like to think they have good support, but I agree that from a users' perspective none of the FPGA vendors have "good" support. But I will say that my recent experience with Altera is much better than any I have had with Xilinx. But then I have not had to contact Xilinx in a couple of years or more. Maybe they have both improved. Likewise my recent contact with Lattice has been fairly positive with good answers. -- Rick "rickman" Collins rick.collins@XYarius.com Ignore the reply address. To email me use the above address with the XY removed. Arius - A Signal Processing Solutions Company Specializing in DSP and FPGA design URL http://www.arius.com 4 King Ave 301-682-7772 Voice Frederick, MD 21701-3110 301-682-7666 FAXArticle: 57353
Paul Leventis <paul.leventis@utoronto.ca> wrote: > tools to do so, so I can't comment on your comparison. But in general, we > find that while some designs benefit from floorplanning for timing closure; > most designs (in Stratix and Cyclone) do not. The first step when we > receive a design that is not hitting timing is for us to try removing the > user's region constraints -- this often does the trick! > > As far as routing by hand goes... I honestly haven't ever seen a case where > a human could beat the Quartus router (barring major bugs). Ignoring OK, but how's your placer? And do you have a pre-p&r tool like Xilinx's MAP? The designs I work on tend to have large sub-blocks with few connections between them. Some of the sub-blocks have I/O so they need to be near particular pins. I prefer to floorplan these to cut down the placer run time. By reducing the placer's freedom a little you reduce the amount of rope it has to hang itself. I think the floorplanning also avoids some of the damage that Xilinx's MAP tool can do. Hamish -- Hamish Moffatt VK3SB <hamish@debian.org> <hamish@cloud.net.au>Article: 57354
Tolga <demircitolga@hotmail.com> wrote: > #vsim -lib work -t 1ps -L xilinxcorelib_ver -L unisims_ver -L > simprims_ver ................... > > Modelsim starts executing : > > #loading work.testbench > > and then quits without any error/warning messages... I am currently > using Modelsim 5.7c and Xilinx ISE 5.2. > > Any suggestions? Run vsim from the Windows command line; it might print some helpful error messages before it vanishes. Hamish -- Hamish Moffatt VK3SB <hamish@debian.org> <hamish@cloud.net.au>Article: 57355
Hi Im beginning work on a project which I will need a RS422 to I2C Converter. Has anyone ever done anything like this? AndyArticle: 57356
How about xilinx? my co has already picked a vertex-2 in the design. "jetmarc" <jetmarc@hotmail.com> wrote in message news:af3f5bb5.0306270954.67be27fa@posting.google.com... > > The tricky part is keeping the routing from a given > > portion from running into the routing from another portion and also > > being able to provide interfaces for the wiring that needs to hookup. > > > > If there is support for this, I am not aware of it. > > Atmels AT40K toolchain lets you turn a design into a rectangular > routed (hard) macro. With this feature it should be possible to > create partial reconfigurable designs. When all modules are > rectangualar and all contain equal (hand-placed) interconnect > cells at their border, the inter-module routing is equal for > all modules. > > However, this still is not the level of support I'd expect of > partially reconfigurable chips. At least one should be able to > define "keepout" areas like in PCB software. > > MarcArticle: 57357
ah wrote: > > Hi > Im beginning work on a project which I will need a RS422 to I2C Converter. > Has anyone ever done anything like this? > > Andy That should not be hard at all. If your RS-422 format is flexible, you can send the same data over RS-422 you would over I2C and just make a level converter. If your RS-422 format is already laid out, then you will need a protocol converter which will likely need to be a small MCU. You will need to read the I2C spec to make sure you understand all the issues involved with either approach. -- Rick "rickman" Collins rick.collins@XYarius.com Ignore the reply address. To email me use the above address with the XY removed. Arius - A Signal Processing Solutions Company Specializing in DSP and FPGA design URL http://www.arius.com 4 King Ave 301-682-7772 Voice Frederick, MD 21701-3110 301-682-7666 FAXArticle: 57358
"GpsBob" <bobthrasher.news.invalid@web2news.net> wrote in message news:<44312N838@web2news.com>... > Anyone familiar with generating Microblaze uP as a component of a larger > design? > > I have no trouble with the example Microblaze projects (EDK 3.2) when > using the XPS environment only. But, if I try to generate the uP as a > component an integrate using Xilinx's ISE 5.1i, when I download to the > eval board nothing works (although the build appears to complete with no > errors). you need to muck a little with the .BMM file there is some note about that on xilinx microblaze mailinglist basically 1) make system with XPS 2) export to PN 3) create your top level add microblaze 4) create bitstream 5) look the placed block RAMs that belong to MB 5) lock those brams in UCF 6) make a copy of .BMM (from XPS design) 7) add PLACED=RxCx; to the bram lines according to your real placement 8) import the PN compiled .BIT and manual fixed BMM into XPS 9) just click 'download' your C source is compiled, merged with PN .bit and you are done this works, no problems. but had to spend some time to get it working. a simpler solution should also exist but I have not found, I guess PN writes sometimes the PLACED= (I did see them in some .BMM what I did not modify by hand) but I did not find a fully automated way. without manually fixing the .BMM (that what you acutally import to XPS) the microblaze program is not assembled into correct bramsArticle: 57359
Paul Leventis wrote: > As for achieving timing closure and doing manual tweaks, take a look at > appliation note AN198. As of Quartus II 3.0 (which should be out shortly), > we offer a new Chip Editor feature and a bunch of timing-closure features > that you may find handy. I've never floorplanned a design nor used Xilinx's > tools to do so, so I can't comment on your comparison. But in general, we > find that while some designs benefit from floorplanning for timing closure; > most designs (in Stratix and Cyclone) do not. The first step when we > receive a design that is not hitting timing is for us to try removing the > user's region constraints -- this often does the trick! Our experience is different. We find that 80-90% of Stratix designs improve with design planning in Amplify. This may be because the the design plan is done before circuit optimization. I suspect that the floorplanning you refer to is after synthesis. > > Regards, > > Paul Leventis > Altera Corp. > > (Opinions are my own) > > >Article: 57360
enliteneer@mindless.com (eric) wrote in message news:<2b8a3423.0306241311.4a558a28@posting.google.com>... > Does anyone know where I can purchase just the examples for the EDK? > http://www.xilinx.com/ise/embedded/edk_examples.htm > > I contacted Xilinx but never received a response. Perhaps they figure > it wouldnt be of much use without the EDK, but as a (financially) struggling > student I would say its better than nothing! > > Thanks! the examples (sources) are most freely downloadable from xilinx website so just download, no payment or license required. but there is nothing you can do with them, EDK 'project files' are very simple test files that describe the cores being used their connection to buses and parameters. without EDK those files are totally useless. another source for EDK samples are memec support pages, those are only for clients but if you buy the lowest cost kit you receive access to example desings :) anttiArticle: 57361
Keith Williams <krw@attglobal.net> wrote in message news:<MPG.195ce5bed99ea36d9899e1@enews.newsguy.com>... > In article <80a3aea5.0306200609.72f7be70@posting.google.com>, > antti@case2000.com says... > > Hi > > > > does anybody have experience with 1mm BGA sockets? > > > > mpi.tycolectronics.com > > > > there are I think suitable sockets but I havent yet got the price quote > > sometimes the BGA sockets costs over 4000 USD - I do hope the MPI > > sockets are a bit cheaper but if there are other low cost alternatives > > please let me know! > > We've used AQL (http://www.aqlmfg.com) BGA sockets with success. I > don't think they're going to save you much money (we paid about $3000US > each), but they're an alternative. tnx, well the mpi ones are actually REAL CHEAP FF896 socket is $250!!! but the socket kit is additional $200 and the minimum order is 10 so 10 pcs = 4500$ still better that one for 3000 the lowest cost I have found is $820 for FF896 socket (qty 1) anttiArticle: 57362
"Wes." <spamthis@hayclan-oz.com> wrote in message news:<K12dnSBMg8y29nCjXTWcpw@giganews.com>... > "Wes." <spamthis@hayclan-oz.com> wrote in message > news:RIKdnYeX9Omq9HijXTWcpw@giganews.com... > > Hi All, > > > > I have several embedded system boards and one of them has a faulty > MACH210A > > IC and I am unable to get the data off the other boards due to the > security > > fuse on the IC is blown. Does anyone know if it is possible to overcome > the > > security fuse and recover the data? Are there any specialty companies that > > can do this kind of work? > > > > Thanks in advance > > > > Wes. > > Thanks for the help, after drawing out what the Mach210 was doing I found it > was a simple Chip Select function. It was using five address lines and some > CPU control lines. Borrowed a Logic Analyser and with the help of our R&D > hardware pro, reverse engineered its logic table. > > Cool, first time to play with Logic Analyser and writing PLD code <grin> > > Wes. :) cool, well you asked for real RE, in most cases the "functional re-creation" is faster simpler and cheaper, good that you managed that.Article: 57363
Hi Kasper
No doubt about it the printfs are being used to satisfy the
timing requirements. Thanks for the specific timing spec though
as this will help me on the rest of my journey.
Denis
"Kasper Pedersen" <ngfilter@kasperkp.dk> wrote in message news:<3efcb301$0$5138$edfadb0f@dread11.news.tele.dk>...
> "Denis Gleeson" <dgleeson@utvinternet.com> wrote in message
> news:6f080894.0306271209.67e598ba@posting.google.com...
> > Hello all
> >
> > As some might know from my recent postings I am trying to configure
> > an FPGA over a PC parallel port using my own SW.
>
> Looking at the init/load code:
>
> > // clear config
> > _outp(DATA,0x10);
> > printf("configuration memory cleared\n");
> > _outp(DATA,0x14);
> >
> > // Actually configure the FPGA
> > printf("start loading %d bytes\n", length);
> > printf("Programming %d bits\n", length *8);
> >
> > for (i=0; i<length; i++)
> > {
> > for (j=7; j>=0; j--)
> > {
> > tmp = (buf[i]>>j) & 1;
> > _outp( DATA,tmp|0x14);
> > _outp( DATA,tmp|0x16);
> > }
>
> The code has no guaranteed delay between releasing /program and clocking
> in the first bit, and it does not check /init. This bit us on an XCS30
> design:
> What you see is that once you release /prog, /init will stay low for
> some time (max 4 ms for the XCS30), and only then can you start clocking
> data into the device.
> My guess is that, in this case, the printf's are supplying enough delay
> that it works for the 05xl (console output under windows is slooow).
>
> /Kasper
Article: 57364> Our experience is different. We find that 80-90% of Stratix designs > improve with design planning in Amplify. This may be because the > the design plan is done before circuit optimization. I suspect that > the floorplanning you refer to is after synthesis. Yes, I was referring to post-synthesis floorplanning using Quartus. When floorplanning is used to improve synthesis, it makes sense that it could help out more. Quartus provides a good enough flow for cost-conscious users, but 3rd party tools (such as Amplify) provide key advantages for users who need the extra performance, density and features these tools provide. Regards, Paul Leventis Altera Corp.Article: 57365
Not all the packages on the market are unuseable in their own right, but, having had similar experience with software from Xilinx, I have to agree that it could be improved. However, it's not always the software alone. The documentation stream available on the support web site could benefit from segregation between classes of problems, particularly between those that have little in common, e.g. CPLD's vs. FPGA's. Part of the original post's complaint is clearly a problem of pilot error/RTFM, since changing the mode of the editor prior to attempting a move will eliminate the "... causes a loop" problem. What I'd find helpful, however, would be that gross failures as are common in the testbench waveform editor were documented such that one couldn't enter the program without the disclaimer: "caution ... you're about to waste weeks of your valuable time on a bit of software that needs a fix, and badly ..." or something on that order. When fixes are scheduled, it should be a policy that unwitting users of the currently flawed versions be warned immediately, or that the module simply be omitted. One unfortunate side effect of the shift to the major HDL's is the increase in volume of paperwork. A design that will fit on a single sheet of schematic often takes dozens if not hundreds of pages of HDL, and that means one's work is vulnerable to all the simple but common "typer-geographical" errors we all make from time to time. A 4-page ABEL design takes dozens of pages of VHDL. Presenting a one-page schematic, or a hierarchy of schematics makes a lot more sense to managers and software types than does a listing of HDL. There will always be a place for schematics, since a picture, still, is worth 1000 words ... perhaps more in VHDL. Now, it's likely that the schematic entry will continue to be poorly supported, and that software, e.g. XILINX' web back (not to pick on them, since they're not alone) but it's a pity that features that can be entered in the schematic tool by means of features specifically provided for that purpose are ignored/overridden by software. Right now, it's possible to specify features in the schematic editor, only to have it ignore them. Additionally, there are somewhat vital features that are established as defaults, that are not overridden by explicit specification of these features in the schematic tool. That can certainly produce frustration. It's necessary to have defaults, but I'd think the defaults would only be of interest if those parameters are not explicity entered somewhere in the process. Having the software impose defaults despite the explicit setting of a given attribute is VERY annoying. Richard Erlacher "rickman" <spamgoeshere4@yahoo.com> wrote in message news:3EFA1ED4.16F6B3C3@yahoo.com... > Yes, you have discovered the not-so-secret of the lack of bug support > for schematic users. I can't say this is unique to Xilinx since I have > never tried schematic with Altera parts. But I expect the problem will > not get better with time. I can say I am a bit surprised. A few years > ago Xilinx was using an editor that was not perfect, but worked ok. I > guess this was something they were paying for per license and were > eating the cost. To save that fee I assume they switched to something > they bought or wrote in house. > > Regardless, you will be better off using an HDL than schematics. A lot > of people fought tooth and nail against HDL, but it is a better solution > for large designs and the FPGA vendors really don't want to have to > support both. So the support for schematic is not good simply because > not many people use it and why spend money supporting something that is > little used. I know you are thinking, "why have it if you don't support > it?" I can't answer that one, you will need to ask X and A. > > But I can say you are definitely swimming upstream with schematic > capture. I know I did my last schematic design some years ago and will > not look back (or look the schematics up :) Keep in mind the number of > bugs you have found so far and you only worked for half a day. Wait > until you try to place and route your schematic design! You will really > be having fun then! Just think of all the newer chip features and how > poorly they will be supported via schematic. > > > > Chris Carlen wrote: > > > > Hi: > > > > Here's a chronicle of today's headaches. > > > > 1. ECS schematic editor can't deal with filenames that contain anything > > except 0-9 a-z A-Z . > > > > 2. I selected a large block of schematic, and when I tried to move it, > > ECS said "Internal Error: Delete Branch" > > > > 3. I guess nobody uses schematic entry because the editor is simply > > impossible to use. It is an absolute disaster. I try to select a group > > of objects to move, and it simply won't let me select them. They don't > > highlight. I try to select everything I have drawn to move it, and I > > get error mentioned in #2 above. The autorouting is useless. Get rid > > of it. Hint: humans are smarter than computers. Just let me draw my > > own wires. > > > > 4. Oh good grief, I moved some things, and then I simply cannot select > > anything anymore. > > > > You see folks, when you make software this bad, even if it is free, > > rather than making me want to pay for the "good" software, it makes me > > think you simply can't write good software. What evidence do I have > > that if I pay for your non-free tools, that they will be any better? > > None. On the contrary, I have volumous evidence that I will simply be > > paying for the exact same thing, only I will not only be frustrated, but > > poorer. The end result is the same. I can't use your silicon. > > > > So perhaps I have made a big mistake. Perhaps I should have gone with > > Altera. I just don't know now. > > > > Or perhaps analog design would be a way to avoid all this crap > > altogether. I don't seem to have much trouble with SPICE simulators. > > Heck even Linear Technology's LTSpice *FREE* simulator is very useable. > > > > Argh! > > > > 5. I closed the schematic editor hoping that if I re-opened my file it > > might reset som eof its internal data structures, and start working > > again. Now I try to reopen my schematic source from Project Navigator, > > and nothing happens. It simply sits there when I click "open". > > > > <Mr. Carlen strikes head with palm, to try to wake up from the bad dream.> > > > > Nope this is reality. Bummer. > > > > Aha! Project Navigator couldn't open my source because it didn't have > > the same name that I created it with. I created it as "cross32-52" > > which Project Navigator accepted just fine. But ECS wouldn't save the > > file with this name, even though it opened it the first time. So I > > saved it as something else, which of course broke Project Navigator. > > Well that's certainly my fault. I should have expected ECS to not save > > filenames with '-' characters. > > > > 6. After closing everything an reopening, I can select and move things > > in ECS again. Oh joy! > > > > 7. I wanted to start a new project to develop a modified version of a > > previous design done from scratch in 5.2i. I copied the .sch and .ucf > > files to the new project dir. I can edit the schematic, so I deleted > > some stuff I didn't want in there. Then I can't open the .ucf file > > because it has nets that aren't in the schematic. I don't know why in > > the original project, when I would add or remove nets from the > > schematic, the user constraints file was automatically updated to > > reflect the nets in the schematic. This doesn't work now, but perhaps > > it's because there is some file missing. > > > > So I will remove the .ucf source and add a new one which I'll set up > > from scratch. I click "remove" and then I add a new source, a user > > constraints with the same name as the one that isn't working. Project > > NAvigator prompts me if I want to overwrite the old file. I click "Ok" > > and expect that when I open the new .ucf file, it will be a reflection > > of the nets in my schematic. > > > > No such luck, the broken .ucf was not everwritten, so it still complains > > of errors of missing nets. > > > > Well that's all before lunch time. Let's see what happens this afternoon... > > > > I guess if there's a point to all this, I should look around on Xilinx's > > web site some more and find out where to report bugs. But I have > > reached a point with software in general where I am tired of doing this. > > That is because, I often wind up spending hours reporting the bugs in > > the rigorous detail that is needed if there is to be any hope of anyone > > actually fixing them. Unless of course, the software had been > > rigorously tested in the first place. > > > > -- > > _______________________________________________________________________ > > Christopher R. Carlen > > Principal Laser/Optical Technologist > > Sandia National Laboratories CA USA > > crcarle@sandia.gov -- NOTE: Remove "BOGUS" from email address to reply. > > -- > > Rick "rickman" Collins > > rick.collins@XYarius.com > Ignore the reply address. To email me use the above address with the XY > removed. > > Arius - A Signal Processing Solutions Company > Specializing in DSP and FPGA design URL http://www.arius.com > 4 King Ave 301-682-7772 Voice > Frederick, MD 21701-3110 301-682-7666 FAXArticle: 57366
"Nicholas C. Weaver" <nweaver@ribbit.CS.Berkeley.EDU> wrote in message news:bdikok$1toa$2@agate.berkeley.edu... > In article <864a80dc.0306271440.79910d76@posting.google.com>, > Naveed <visualfor@yahoo.com> wrote: > >As far as technical support go, both companies suck (probably Altera > >sucks more than xilinx). They normally hire fresh college graduate > >for support, and those kids can't answer much. > > The major exception is comp.arch.fpga, where you have Peter Alfke and > Austin Lesea answering Xilinx questions. The joke is, you probably get better answers in this newsgroup than if you go through their offical support channels.Article: 57367
I had to change the subject, it isn't a xilinx problem I guess ;-) Richard Erlacher wrote: > > There will always be a place for schematics, since a picture, still, is > worth 1000 words ... perhaps more in VHDL. > I always like the "top-level-schematics-thing" because (at least for me) it seems much easier to see how all the modules depend/are connected to each other. And it is much easier to explain to somebody what you did ... So, I probably wouldn't start any new designs and try to completely make the in schematics only, but in few spaces, schematics REALLY makes sense. just my .02$ cheers P.S. Are they any tools out there, which could automagically generate a "top-level-schematic" out of VHDL code ?Article: 57368
Rick, Based on feedback from users like yourself we have expanded the device coverage to include the Flex10KA devices in QII 3.0, which was released to production/manufacturing last Friday. Quartus II Timing Analysis capabilities and algorithms than Max+Plus II. We are constantly working to improve the design migration experience from Max+Plus II to Quartus, so that the users can easily access the more advanced capabilities if they need it. For a description of the new features available in Quartus II 3.0 please click on the url below http://www.altera.com/products/software/pld/products/q2/whats_new/qts-whatsn ew.jsp?xy=qts1_qwn - Subroto Datta Altera Corp. "rickman" <spamgoeshere4@yahoo.com> wrote in message news:3EFD0883.96EDB7ED@yahoo.com... > > > Altera's software is more user friendly. With Quartus, I am not that > > sure, but I don't think there ever have been a better CAD tool than > > Maxplus2. For quick and dirty digital design, I will always stick > > with Altera, as long as they have MaxPlus2. > > This is the other bone I would pick. I have only done one project with > MaxPlus2, but it nearly ruined my career, and I don't mean that > lightly. There is a problem with timing analysis in a densely populated > 10K100A part so that the chip will not meet timing even though the tool > says it will. We could not get the attention of tool support because > this chip is no longer supported in any real sense. They brought all > the other, newer versions of the 10K parts into Quartus, but not the > 10KAs. So we had to write our own constraints generation scripts and > play all sorts of games including temperature testing of each design we > generated to get a product out the door. > > > -- > > Rick "rickman" Collins > > rick.collins@XYarius.com > Ignore the reply address. To email me use the above address with the XY > removed. > > Arius - A Signal Processing Solutions Company > Specializing in DSP and FPGA design URL http://www.arius.com > 4 King Ave 301-682-7772 Voice > Frederick, MD 21701-3110 301-682-7666 FAXArticle: 57369
Nicholas C. Weaver <nweaver@ribbit.cs.berkeley.edu> wrote:
>>
>> * it does not speed down long chains, it just doesn't give any
>> additional benefit in that case - with the sole exception of
>> exteremely grossly braindead compilers that can't manage tail calls
>
> It does because you potentially spill a lot MORE registers than you
> otherwise would, because the window assume 8 local registers and 8 arg
> registers to be saved, IIRC.
The window doesn't deal with this - more precicely the "window" is made
up of: 8 global registers (same in all windows), 8 local registers (private
in all windows), 8 "in" registers ("out" registers from previous window)
and 8 "out" registers ("in" registers in the next window). The "default"
ABI is a rather straightforward mapping to these. Now which are spilled
and which not is a separate matter from these window components, and
really a matter of the ABI and not hardware - and is done by software
when the window stack over/underflows and not the hardware. So you have
a lot of freedom there.
>
> There was a masters done many years back which I'm trying to get a
> reference to, where MIPS code was transliterated/translated to the
> SPARC, compared with code complied directly onto the SPARC to see the
> impact of register windows.
Having seen what naive compiler ports occasionaly do, yes, of course the
results would be bad as the register allocator would have been using mips
and not sparc register set rules. It doesn't give you an unbiased result.
Really, you shouldn't treat it as having a "flat" register file, or you will
get rather suboptimal results.
Whetever sparc being free pays for the (eral or perceived) inconvinince of
windows will of course depend on details - and possibly the software you run.
--
Sander
+++ Out of cheese error +++
Article: 57370Since Altera only sells Stratix, Cyclon, and APEX kits for their Nios, can Quartus II synthesize the Nios on a small (70k gates) FLEX device? Is this possible or does it require too many internal ram blocks/multipliers that the Flex simply doesnt have? Thanks!Article: 57371
Antti, I think downloading the sample files require being an EDK registered user. Im registered with Xilinx but only for the ISE 2.1 Student Edition software, so nothing happens when I click the examples and enter my account info. Im not familiar with the memec support pages, is this from Xilinx? The EDK costs about $500, so if they have a low priced kit that includes such examples, Im interested! Eric > > Does anyone know where I can purchase just the examples for the EDK? > > http://www.xilinx.com/ise/embedded/edk_examples.htm > > > > I contacted Xilinx but never received a response. Perhaps they figure > > it wouldnt be of much use without the EDK, but as a (financially) struggling > > student I would say its better than nothing! > > > > Thanks! > > the examples (sources) are most freely downloadable from xilinx website > so just download, no payment or license required. > > but there is nothing you can do with them, EDK 'project files' are very > simple test files that describe the cores being used their connection to > buses and parameters. without EDK those files are totally useless. > > another source for EDK samples are memec support pages, those are only > for clients but if you buy the lowest cost kit you receive access to > example desings :) > > anttiArticle: 57372
Paul Leventis wrote: > But in general, we find that while some designs benefit from > floorplanning for timing closure; > most designs (in Stratix and Cyclone) do not. The first step when we > receive a design that is not hitting timing is for us to try removing the > user's region constraints -- this often does the trick! And appx 15 hrs later : Paul Leventis wrote: > There are two exceptions I can think of. > In data-path designs where you as the designer > know very well the exact signal flow you would like and can line up large > amounts of logic so that every hop in a large bus is the minimum length. An > iterative improvement algorithm will have difficulty coming up with a highly > regular solution like this; it might find the right arrangement for 31/32 > bits of the bus, but that one sub-optimal decision slows down your design. > The other case is when you have tight I/O interfacing requirements -- > push-button does a pretty good job (and getting better each release), but > there are times when you can improve results slightly by floorplanning. > Part of this is due to tuning. It's a lot easier to test out algorithms > that improve the maximum clock speed of a chip than it is to test algorithms > that work with multiple conflicting I/O requirements. > > So I believe that human-assisted placement has its place, while I don't > believe much in human-assisted routing. I find these two posts are a tad contradictory ? - and I'd say the two 'exceptions' have rather large footprints :) I would agree it is preferable to let the tools handle the details of routing, BUT you need to be able to control PLACEMENT in such a way that there is (almost) only one routing solution. Then, you should also also be able to 'lock' the routes. so that a design block that has been tested, and 'signed off' will NOT change due to iterations in an unrelated portion of the chip. All of this makes the design more predictable, and SHOULD also give significant P&R runtime savings. -jgArticle: 57373
Subroto Datta (Altera) wrote: > > Rick, > > Based on feedback from users like yourself we have expanded the device > coverage to include the Flex10KA devices in QII 3.0, which was released to > production/manufacturing last Friday. Quartus II Timing Analysis > capabilities and algorithms than Max+Plus II. We are constantly working to > improve the design migration experience from Max+Plus II to Quartus, so that > the users can easily access the more advanced capabilities if they need it. Sounds like good news - even proof newsgroups work well :). There is a tendency to be skewed too much to the latest new thing, and it is good to see tool flow support that accepts there is plenty of life in the middle ground. It is not good to see silicon lifetimes shortened solely by SW 'issues'. -jgArticle: 57374
Hi Jim, > I find these two posts are a tad contradictory ? > - and I'd say the two 'exceptions' have rather large footprints :) My feelings on the frequency with which floorplanning is useful on Stratix/Cyclone are moot, given that our tools provide floorplanning capabilities. That said... I would say that highly regular datapath designs are a small minority of designs. Datapath designs themselves are not, but its rare for the datapath logic to be highly regular and fit nicely in the FPGA in a way that a human can predict the best placement and routing. As for IO timing (my other exception) most designs don't need heavy-duty tweaking of IO timing and will hit the required performance push-button. So I feel my earlier statement that (post-synthesis) floorplanning helps some designs but not most still seems valid even in the context of my later posting. > I would agree it is preferable to let the tools handle the details of > routing, BUT you need to be able to control PLACEMENT in such a way > that there is (almost) only one routing solution. My position is that with a given placement, the router will tend to find the best routing solution; and it will do so in the presence of routing congestion or many different, often conflicting choices. But I agree that if a human could find a placement that results in lower routing stress (not the same as "one solution"), this can in turn result in better routing. All I'm arguing is that more often than not, the push-button placer will beat out the human; that appears to be our only point of disagreement. BTW, this only applies to Stratix/Cyclone -- in FLEX & APEX with their hard-boundaries in the routing, it's easier for a human to find a good floorplan for their design. > Then, you should also also be able to 'lock' the routes. so > that a design block that has been tested, and 'signed off' > will NOT change due to iterations in an unrelated portion of the chip. > All of this makes the design more predictable, and SHOULD also > give significant P&R runtime savings. You should be able to, and you can in Quartus II. Locking routing (we call it routing back-annotation) for the purpose you mention can be handy. It is especially handy for when you make a small change to an already verified design and want to minimize changes in the design, or when you want to port designs between versions of Quartus while maintaining the same fit. But predictability sometimes comes at a price. Using a block-based design methodology where you lock routing then integrate your blocks may result in lower performance or worse routability when compared to the same design with the routing constraints removed. If the router believes it needs to alter the route in one of your blocks, it's usually for a good reason! Regards, Paul
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