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Eventhough I have compiled and mapped Xilinx libraries, when try to simulate my desings Modelsim crashes and quits. After execution of : #vsim -lib work -t 1ps -L xilinxcorelib_ver -L unisims_ver -L simprims_ver ................... Modelsim starts executing : #loading work.testbench and then quits without any error/warning messages... I am currently using Modelsim 5.7c and Xilinx ISE 5.2. Any suggestions? Thanks, Tolga Thomas <tom3@protectedfromreality.com> wrote in message news:<oprq7qmalimo2d8p@news3.news.adelphia.net>... > How do you recompile the libraries for ModelSim 5.7? all the libs I found > at for 5.6 > > I tried to ask modelsim to rebuild them, but there are lots of errors. > I tried the tcl script on xilinx's ftp, as a result it goes for a while and > then modelsim just crashes and quits...Article: 57326
I think its fairly simple. Clued Xilinx People will answer questions in this newsgroup, so a lot of people have figured out "If there is a question, problem, or gotcha, ask here, you get the quickest response". -- Nicholas C. Weaver nweaver@cs.berkeley.eduArticle: 57327
Kelvin Tsai @ Singapore wrote: >Hi, all: > >In the Vertex-2 datasheet, it mentioned about partial reconfiguration, >where can I find more information on this topic? > Check out this App Note. It describes the software flow: http://www.xilinx.com/xapp/xapp290.pdf >I have a variable >design and a fixed design to put on same V-2 chip. > >Will partial reconfiguration process halt the current operation of the >'fixed' design on the chip? > No, you can leave the fixed design running. >How can I guarantee the variable design doesn't rob away the hardware >of my fixed design? > Partial reconfiguration requires our modular design flow where you specify the physical area of each module (or in your case, the fixed design and the reconfigurable design). The modular design router does not go outside the area you have specified. Our bitstream generation tool can look at two bitstreams and generate a difference bitstream to be used for partial reconfiguration. Communication between the modules requires bus macros. It's all explained in the App Note. Steve > >Thanks. >Kelvin > >Article: 57328
make sure your licence is valid, it will do that kind of things otherwise On 27 Jun 2003 08:02:21 -0700, Tolga <demircitolga@hotmail.com> wrote: > Eventhough I have compiled and mapped Xilinx libraries, when try to > simulate my desings Modelsim crashes and quits. > > After execution of : > > #vsim -lib work -t 1ps -L xilinxcorelib_ver -L unisims_ver -L > simprims_ver ................... > > Modelsim starts executing : > > #loading work.testbench > > and then quits without any error/warning messages... I am currently > using Modelsim 5.7c and Xilinx ISE 5.2. > > Any suggestions? > > Thanks, > Tolga > > > > Thomas <tom3@protectedfromreality.com> wrote in message > news:<oprq7qmalimo2d8p@news3.news.adelphia.net>... >> How do you recompile the libraries for ModelSim 5.7? all the libs I >> found at for 5.6 >> >> I tried to ask modelsim to rebuild them, but there are lots of errors. >> I tried the tcl script on xilinx's ftp, as a result it goes for a while >> and then modelsim just crashes and quits... >Article: 57329
Hi,
I implemented into a SPARTAN-II (device xc2s200, package pq208, speed
-5) the design shown in Xapp132, figure 10: "DLL de-skew of board level
clock".
The mydesign.edf file has been generated for 40MHz with synplify_pro,
promising a 47+MHz clock.
My problem is that I can implement the design at 27MHz, but not over.
If I try, after phase 5 of PAR, I get the following messages:
(command is: par -ol 2 -w map.ncd mydesign mydesign.pcf)
IMPORTANT MSG: IRRATIONAL TIMING! SWITCHING TO RESOURCE MODE; (EASE
CONSTRAINTS) (sometimes I don't get this message...)
WARNING:Par:62 - Timing constraints have not been met.
The unmatched constraint is at the output CLK0 of the CLKDLL component,
input of the BUFG:
TS_dllint_clk0 = PERIOD TIMEGRP "dllint_clk0" ts_clkin * 1.000000 HIGH
50.000 %
here are several results of PAR for this TS_dllint_clk0:
Requested: Actual: Logic Level:
36ns 35.46ns 6 (no error here)
35ns 35.118ns 6
25ns 40.810ns 6
I tried CLKDLLHF, but it is worse.
25ns 42.4ns 5 (with CLKDLLHF)
I tried par -ol 5...
25ns 37ns
Any idea of what is happening?
Should I try "par -n 0"? use IO_LVDS_DLL? give up and buy a bicycle?
further details below:
here are the constraints in .UCF file:
NET clkin LOC= P77 ;
NET "clkin" TNM_NET= "clkin";
TIMESPEC "ts_clkin"= PERIOD "clkin" 25 ns HIGH 50 %;
anyway, the trace of the constraint is ok:
INFO:XdmHelpers:851 - TNM "clkin", used in period specification
"ts_clkin", was
traced into CLKDLL instance "dllint". The following new TNM groups and
period specifications were generated at the CLKDLL output(s):
CLK0: TS_dllint_clk0=PERIOD dllint_clk0 ts_clkin*1.000000 HIGH
50.000000%
Article: 57330> The tricky part is keeping the routing from a given > portion from running into the routing from another portion and also > being able to provide interfaces for the wiring that needs to hookup. > > If there is support for this, I am not aware of it. Atmels AT40K toolchain lets you turn a design into a rectangular routed (hard) macro. With this feature it should be possible to create partial reconfigurable designs. When all modules are rectangualar and all contain equal (hand-placed) interconnect cells at their border, the inter-module routing is equal for all modules. However, this still is not the level of support I'd expect of partially reconfigurable chips. At least one should be able to define "keepout" areas like in PCB software. MarcArticle: 57331
In article <1056453399.643807@haldjas.folklore.ee>, Sander Vesik <sander@haldjas.folklore.ee> wrote: >> There is always Sparc, which doesn't have a liscence fee to use the >> ISA, only to use the SPARC trademark. > >sparc licence costs $99 - to use the mark i believe you have to pass >certification, which probably costs more. But don't quote me on this http://www.sparc.org/faq.html The "registry fee" appears to be for tracking purposes, not for use, according ot their FAQ. >> Of course, register windows are a bad idea, but hey, nothing's >> perfect. > >but with block rams, there are much less problems. Even with BlockRAMs, its that register windows: a) FUBAR garbage collectors by hiding the root set b) Don't actually speed up function calling, as long call-chains you end up spilling MORE data than you otherwise would. >of course, everybody can always start from scratch and make a fpga >specific one Too bad intel probably has patents-up-the-wazoo on the IA64's deferred execption model. That is one of the few great things about that architecture. -- Nicholas C. Weaver nweaver@cs.berkeley.eduArticle: 57332
Sander Vesik <sander@haldjas.folklore.ee> wrote in message news:<1054761767.988243@haldjas.folklore.ee>... > Anybody know of Cyclone EP1C12 (preferably) or EP1C20 > (also ok) based PCI development boards? Do such things > even exist - or in other words, what is the approximate > timline after chip availability that one can expect such > to be around? Sander, I am unaware of any existing PCI Cyclone boards, however Nova Engineering is currently developing a PC/104+ Cyclone board for our Constellation FPGA Board line. This board should be available late summer/early fall. More info here: www.nova-eng.com/const-1c.html. Ryan Canning Constellation Tech Support Nova Engineering, Inc. Phone: 513-642-3197 Fax: 513-642-3397 www.nova-eng.comArticle: 57333
jetmarc wrote: > > > The tricky part is keeping the routing from a given > > portion from running into the routing from another portion and also > > being able to provide interfaces for the wiring that needs to hookup. > > > > If there is support for this, I am not aware of it. > > Atmels AT40K toolchain lets you turn a design into a rectangular > routed (hard) macro. With this feature it should be possible to > create partial reconfigurable designs. When all modules are > rectangualar and all contain equal (hand-placed) interconnect > cells at their border, the inter-module routing is equal for > all modules. > > However, this still is not the level of support I'd expect of > partially reconfigurable chips. At least one should be able to > define "keepout" areas like in PCB software. The other problem is that the Atmel parts are very long in the tooth. This means they are not competative in terms of performance and price and may well disappear at any time. I have already been advised not to use the FPSLIC which functionally would be a very good part for my design. At one point the Lucent parts started to look like an array of four smaller chips on one die. If they had provided enough separation to individually clock and configure them, that would have been perfect for my needs. But then Lucent seems to have suffered a lack of enthusiasm for FPGA sales. The newer Orca parts that Lattice is selling are targeted more for the comms market. -- Rick "rickman" Collins rick.collins@XYarius.com Ignore the reply address. To email me use the above address with the XY removed. Arius - A Signal Processing Solutions Company Specializing in DSP and FPGA design URL http://www.arius.com 4 King Ave 301-682-7772 Voice Frederick, MD 21701-3110 301-682-7666 FAXArticle: 57334
On 12 May 2003 11:44:28 -0700, tardi69@hotmail.com (Paolo Tardivel)
wrote:
>I have implemented a testbench in e that drives a VHDL design on the fly.
What do you mean by "on the fly"? Presumably Specman is driving
all or most of the stimulus into the DUT - that's a very reasonable
way to start.
>The VHDL file I drive acts as a shell for the design and simply
>contains the signals that I need to drive. This file contains the
>necessary code to link Specman and ModelSim and is called macro.vhd.
>These signals are then driven into the design in a file called sig_lib
>as follows:
>
> inst_mstim: macro
[...]
OK, that's the usual sort of thing.
>This all works fine and the values driven into the signals can be seen
>in ModelSim's waveform viewer. However I want to be able to view all
>the signals from the design (not just the ones I am driving), in order
>to view the dataout signals.
So, what's the problem? ModelSim can see all the signals in the
loaded design, same as it always can.
>So what I want to be able to do is Specman to drive macro.vhd, but
>ModelSim to load sig_lib.vhd, while keeping the "on the fly" nature of
>my implementation.
>I am currently using the following command to invoke Specman and
>ModelSim (after everything is compiled):
> specview vsim -keepstdout macro
Now I'm confused. You have your "sig_lib" entity, apparently, but you
are not loading it; instead, you are loading the next level down
("macro") which is something that has ports. Why not load sig_lib?
I think it's possible that you have one more level of hierarchy than
you really need. If all the DUT's inputs are being sourced from e
code, then you only need one level of jacket - simply declare one
signal for each DUT port, hook the DUT to those signals, and let
Specman play around with the signals in the jacket module. No ports
on the jacket module - it's just like a testbench. Don't
forget to instantiate the SPECMAN entity in the jacket, too.
When you do this correctly, the HDL simulator can see all signals
in the simulation - so it's easy to load any signal into the
waveform viewer - and you can also issue "wave event" and
"wave exp" commands to display Specman objects in the wave viewer.
You may get more help on the Verisity mailing lists.
--
Jonathan Bromley
Jonathan Bromley
Article: 57335rickman wrote: >Steve Lass wrote: > > >>Kelvin Tsai @ Singapore wrote: >> >> >>>Hi, all: >>> >>>In the Vertex-2 datasheet, it mentioned about partial reconfiguration, >>>where can I find more information on this topic? >>> >>> >>> >>Check out this App Note. It describes the software flow: >> >>http://www.xilinx.com/xapp/xapp290.pdf >> >> >>>I have a variable >>>design and a fixed design to put on same V-2 chip. >>> >>>Will partial reconfiguration process halt the current operation of the >>>'fixed' design on the chip? >>> >>> >>No, you can leave the fixed design running. >> >> >>>How can I guarantee the variable design doesn't rob away the hardware >>>of my fixed design? >>> >>> >>> >>Partial reconfiguration requires our modular design flow where you >>specify the physical area of >>each module (or in your case, the fixed design and the reconfigurable >>design). The modular design >>router does not go outside the area you have specified. Our bitstream >>generation tool can look at >>two bitstreams and generate a difference bitstream to be used for >>partial reconfiguration. >> >>Communication between the modules requires bus macros. It's all >>explained in the App Note. >> >>Steve >> >> > >Thanks for the pointer. This is a useful document. But I am a little >confused about the useage of the term "slices". They talk about a >module 4 slices wide. Do they mean slices in the sense of a pair of FFs >and LUTs and not a CLB? So in a Spartan 3, 4 slices are 1 CLB? > Yes, the minimum config size is 1 CLB column. One thing you might notice in in App Note is that we use TBUFs for communication between modules. Since Spartan3 doesn't have TBUFs, you will need a macro. I think I can get you one that we created, but haven't tested yet. >In my application I would not need to reconfigure while operating. I >just need to be able to pick a design from a list for each module at >configuration time. e.g. Put design A in modules 1 and 3 and put design >B in module 2 and design C in module 4. This would all be decided at >power up time, the FPGA would then be configured once with the >combination of modules. > > I'm pretty sure that the devices need a full configuration first, then partial bistreams can be loaded. You could probably do a simple bitstream with multiple frame writes to fill the device, then load each of your design bitstreams. SteveArticle: 57336
Hello all
As some might know from my recent postings I am trying to configure
an FPGA over a PC parallel port using my own SW.
Today I managed to get SW to configure a spartan xl device through a xilinx
parallel download cable. This is a partial step towards my desired solution.
In the hope that this code may help others it is included below. I targeted
a spartan xl. with some minor modifications this code should work for other
FPGAs.
Regards
Denis
/*****************************************************************************
** Project: Use a Dos Executable to configure a spartan xl FPGA.
** This software operates with a xilinx parallel cable.
** Im using Parallel cable IV but any should work.
** The project was a WIN 32 console application. Built using MSVC 6.
** Run code in debug mode as _inp and _outp will not operate
** otherwise. Running the .exe in a dos window appears to succeed but
** in fact it doesnt. I used Win ME but 95 or 98 should be OK also.
** Not so sure about 2K, XP etc.
**
** File : CFG_bit.c
**
** Author : Denis Gleeson
**
**
** Notes 1. Assumptions made: i.e. things that need changing for other FPGAs.
** (a) Parallel port address starts at 0x378
** (b) configuration file is a .bit file.
** (c) configuration file is in the specified directory.
** (e) configuration file has less than 64K Bytes.
** (f) Device is a xilinx xcs05xl.
**
** 2. Program based on the work of Brittle. Thanks to Philip Freidin
** for the FPGA- FAQ and Question: How can I download a FPGA from
** a linux System
**
** 3. Use this code at your own risk. I guarantee nothing.
** It worked for me, it may not work for you.
** Its just a quick test I put together to allow me to move
** on to my required solution.
**
****************************************************************************/
#include <stdio.h>
#include <conio.h>
#define DATA 0x378
#define STATUS DATA+1
#define CONTROL DATA+2
char buf[64000];
int main(void)
{
FILE *bitfile;
unsigned char head_key;
unsigned long int length=0;
unsigned char length1;
unsigned char length2;
unsigned char length3;
unsigned char length4;
unsigned int i =0;
int j=0;
unsigned char tmp=0;
bitfile = fopen("C:/work/projects/comisn10.bit", "rb");
if(bitfile== NULL)
{
printf("Cant open File \n");
return(0);
}
head_key = 0;
while (head_key != 0x65)
{
fread(&head_key, 1, 1, bitfile);
printf("%c ",head_key);
if (head_key == 0x65)
{
// Cant use fread to read 4 bytes in one go because
// I end up with words switched and bytes within words switched.
// read Byte 1
fread(&length1, 1, 1, bitfile);
length = length | (length1<<24);
// read Byte 2
fread(&length2, 1, 1, bitfile);
length = length | (length2<<16);
// read Byte 3
fread(&length3, 1, 1, bitfile);
length = length | (length3<<8);
// read Byte 4
fread(&length4, 1, 1, bitfile);
length = length | (length4);
// Now read length bytes into the buffer.
fread(buf,length, 1, bitfile);
}
}
fclose(bitfile);
printf("\n");
_outp(CONTROL,0x04);
// sense VCC
tmp =_inp(STATUS);
tmp = (tmp>>3) & 1;
if (!tmp)
{
printf("cabel not found\n");
return(0);
}
else
printf("cabel detected\n");
// clear config
_outp(DATA,0x10);
printf("configuration memory cleared\n");
_outp(DATA,0x14);
// Actually configure the FPGA
printf("start loading %d bytes\n", length);
printf("Programming %d bits\n", length *8);
for (i=0; i<length; i++)
{
for (j=7; j>=0; j--)
{
tmp = (buf[i]>>j) & 1;
_outp( DATA,tmp|0x14);
_outp( DATA,tmp|0x16);
}
}
printf("finish loading\n");
// Done
tmp =_inp(STATUS);
tmp = (tmp>4)&1;
if (tmp)
printf("DONE!\n");
else
printf("FAILED!\n");
printf("Hit any Key to Continue. \n");
while(!kbhit())
{
;
}
return (0);
}
Article: 57337Is there a limitation to what type of divider can be implemented in FPGA hardware vs. ASIC? I come from the ASIC side, and I have something in verilog like: assign Z = (a[15:0] / b[9:0]); and I get an error saying the divisor must be a power of 2. Looking around, it seems that this cannot be implemented into HW?? Any advice is appreciated.Article: 57338
"Denis Gleeson" <dgleeson@utvinternet.com> wrote in message
news:6f080894.0306271209.67e598ba@posting.google.com...
> Hello all
>
> As some might know from my recent postings I am trying to configure
> an FPGA over a PC parallel port using my own SW.
Looking at the init/load code:
> // clear config
> _outp(DATA,0x10);
> printf("configuration memory cleared\n");
> _outp(DATA,0x14);
>
> // Actually configure the FPGA
> printf("start loading %d bytes\n", length);
> printf("Programming %d bits\n", length *8);
>
> for (i=0; i<length; i++)
> {
> for (j=7; j>=0; j--)
> {
> tmp = (buf[i]>>j) & 1;
> _outp( DATA,tmp|0x14);
> _outp( DATA,tmp|0x16);
> }
The code has no guaranteed delay between releasing /program and clocking
in the first bit, and it does not check /init. This bit us on an XCS30
design:
What you see is that once you release /prog, /init will stay low for
some time (max 4 ms for the XCS30), and only then can you start clocking
data into the device.
My guess is that, in this case, the printf's are supplying enough delay
that it works for the 05xl (console output under windows is slooow).
/Kasper
Article: 57339Xilinx, V2, DCM's: Pro's and con's of setting STARTUP_WAIT = "TRUE"? When to use it and when not. Why? On first inspection, it would seem to me that you'd always want to have this set to "TRUE" unless you have a design where you know that an external clock is not guaranteed to be available after configuration or "manually" resetting a DCM. Thanks, -- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ Martin Euredjian To send private email: 0_0_0_0_@pacbell.net where "0_0_0_0_" = "martineu"Article: 57340
hello. i'm just getting started to learn fpga and i'm interested in dsp design in fpga. what small projects do you recommend to start with? i need to define small projects so that i have goals, rather than studying without any target. thanks!Article: 57341
"Skept" <skepticon@yahoo.com> wrote in message news:bbdf4ddd.0306271311.56bcdacb@posting.google.com... > Is there a limitation to what type of divider can be implemented in > FPGA hardware vs. ASIC? No. I come from the ASIC side, and I have > something in verilog like: assign Z = (a[15:0] / b[9:0]); and I get an > error saying the divisor must be a power of 2. Looking around, it > seems that this cannot be implemented into HW?? The limitation is with your synthesis tool, not the capabilities of FPGA. > Any advice is appreciated. Buy a good book on computer arithmetic and implement the operation yourself (or alternatively search a bit hardware around the web and you're bound to find some example code). Don't expect the resultant hardware to be small. Cheers, JonBArticle: 57342
Nicholas C. Weaver <nweaver@ribbit.cs.berkeley.edu> wrote: > In article <1056453399.643807@haldjas.folklore.ee>, > Sander Vesik <sander@haldjas.folklore.ee> wrote: >>> There is always Sparc, which doesn't have a liscence fee to use the >>> ISA, only to use the SPARC trademark. >> >>sparc licence costs $99 - to use the mark i believe you have to pass >>certification, which probably costs more. But don't quote me on this > > http://www.sparc.org/faq.html > > The "registry fee" appears to be for tracking purposes, not for use, > according ot their FAQ. > >>> Of course, register windows are a bad idea, but hey, nothing's >>> perfect. >> >>but with block rams, there are much less problems. > > Even with BlockRAMs, its that register windows: > > a) FUBAR garbage collectors by hiding the root set Observing the number of garbage collectors working just fine on sparc, > > b) Don't actually speed up function calling, as long call-chains you > end up spilling MORE data than you otherwise would. This is plain wrong. Among other things: * it assumes a specific calling convention - you could use something else than the "standard" of doing save/restore on function entry / exit - and instead use it for fast thread switches. * it does speed up function calls * it allows for very fast tail calls and polymorphism * it does not speed down long chains, it just doesn't give any additional benefit in that case - with the sole exception of exteremely grossly braindead compilers that can't manage tail calls The register windows are just a cache for parts of stack frames - like all caches, you get bet perfomance if you don't do braindead things. -- Sander +++ Out of cheese error +++Article: 57343
Hello, I have used both Xilinx and Altera extensively. Xilinx: Virtex, VirtexE, VirtexII (but not pro) Altera: CPLDS, 10K, 10KA, 10KE, 6K, Cyclone (but not Apex, or Stratix) here's my thoughts: If you are designing a high speed logic (above 100Mhz core), Altera might be risky. Xilinx software helps you squeeze the last 0.1ns off of your chip. In xilinx, you can route each and every net manually. Altera's floor planner is a joke when compared to xilinx. And, Altera does not even have FPGA editor (for manual tweeking). If you are using a lot of small shift registers and memory, xilinx lets you convert LUT into RAM. No such feature in Altera. For all other designs, consider using Altera. Altera's parts are cheaper and readily available. I just love the fact that Altera has fix pricing on 6K and Cyclone, whether you buy 1, or 100. Xilinx just started competing with Altera on pricing. Two years ago, I would use Altera in any low-cost solution, if the speed wasn't too high. With Spartan2/3, I now, do consider xilinx. Altera's software is more user friendly. With Quartus, I am not that sure, but I don't think there ever have been a better CAD tool than Maxplus2. For quick and dirty digital design, I will always stick with Altera, as long as they have MaxPlus2. As far as technical support go, both companies suck (probably Altera sucks more than xilinx). They normally hire fresh college graduate for support, and those kids can't answer much. I am not complaining, as I work for small company. I am sure Cisco probably gets better support. I do understand that. qlyus@yahoo.com (qlyus) wrote in message news:<da71446f.0306262230.33862eda@posting.google.com>... > I do not know why you see my post is Xilinx bashing. I did not even > try to criticise Xilinx. Are those posts of Xilinx problems real? Is > it true that there are few Altera related? > > As a matter of fact, I am a long time or all time Xilinx user, I did > not know (or did not want to know) altera product line well. I > started to look at Altera Stratix closely when I started a big DSP > project a couple of month ago. It looks very good in features and > performance (as it says). The documentation is far better than > Xilinx, for example, the DSP section of Stratix User Guider. Altera > rep/distributor did not walk away as Xilinx people did when they heard > small annual volume. > > My next step went to software. Again as a long time Xilinx user > (since M1.2), I do not know anything of Altera backend software. > Browsing and searching this NG is one way trying to gether this kind > of information. I read this NG and Xilinx realated posts quite often. > But I wonder there are very few Altera post, especially its software > problem related, people talked more on chip to chip comparison. It > even surprised me alittle when I counted the numbers of Xilinx vs > Altera posts. > > I do not see your logic how my post affects the value of Xilinx > appearance in this NG, and what kind of criticism is constructive or > destructive. Don't you see Peter and Austin already appeared in this > thread? > > -qlyus >Article: 57344
In article <1056751822.55116@haldjas.folklore.ee>, Sander Vesik <sander@haldjas.folklore.ee> wrote: >> a) FUBAR garbage collectors by hiding the root set > >Observing the number of garbage collectors working just fine on >sparc, Its a performance hit, because they have to force a spill to get at the root set. And if you want to hear some REAL curses, talk to those in charge of Java's GC on the SPARC. Especially the multiprocessor implementation's GC. >> b) Don't actually speed up function calling, as long call-chains you >> end up spilling MORE data than you otherwise would. > >This is plain wrong. Among other things: > * it assumes a specific calling convention - you could use >something else than the "standard" of doing save/restore on function >entry / exit - and instead use it for fast thread switches. > * it does speed up function calls > * it allows for very fast tail calls and polymorphism > > * it does not speed down long chains, it just doesn't give any > additional benefit in that case - with the sole exception of > exteremely grossly braindead compilers that can't manage tail calls It does because you potentially spill a lot MORE registers than you otherwise would, because the window assume 8 local registers and 8 arg registers to be saved, IIRC. There was a masters done many years back which I'm trying to get a reference to, where MIPS code was transliterated/translated to the SPARC, compared with code complied directly onto the SPARC to see the impact of register windows. -- Nicholas C. Weaver nweaver@cs.berkeley.eduArticle: 57345
In article <864a80dc.0306271440.79910d76@posting.google.com>, Naveed <visualfor@yahoo.com> wrote: >As far as technical support go, both companies suck (probably Altera >sucks more than xilinx). They normally hire fresh college graduate >for support, and those kids can't answer much. The major exception is comp.arch.fpga, where you have Peter Alfke and Austin Lesea answering Xilinx questions. -- Nicholas C. Weaver nweaver@cs.berkeley.eduArticle: 57346
Just for grins, generate a binary file from the Xilinx tools and compare it to the bit file. The header should be stripped off to begin with and you might have better luck with the byte ordering (or perhaps not). It's just another form of output - one that we use exclusively.Article: 57347
"Jon Beniston" <dontspam@me.you.bastards> wrote in message news:920b1dbeef215215a6fc038ea46a0b0e@TeraNews... > > "Skept" <skepticon@yahoo.com> wrote in message > news:bbdf4ddd.0306271311.56bcdacb@posting.google.com... > > Is there a limitation to what type of divider can be implemented in > > FPGA hardware vs. ASIC? > > No. > > I come from the ASIC side, and I have > > something in verilog like: assign Z = (a[15:0] / b[9:0]); and I get an > > error saying the divisor must be a power of 2. Looking around, it > > seems that this cannot be implemented into HW?? > > The limitation is with your synthesis tool, not the capabilities of FPGA. > > > Any advice is appreciated. > > Buy a good book on computer arithmetic and implement the operation yourself > (or alternatively search a bit hardware around the web and you're bound to > find some example code). Don't expect the resultant hardware to be small. > > Cheers, > JonB > > To expand on what JonB said, there is a trade off between gate count and number of clock cycles required to perform the operation.Article: 57348
Hi Naveed, I'm steering clear from most of this thread -- bashing of anyone, even X ;-), is silly if you ask me. But I thought I'd respond to a few of your criticisms. > If you are designing a high speed logic (above 100Mhz core), Altera > might be risky. Xilinx software helps you squeeze the last 0.1ns off > of your chip. In xilinx, you can route each and every net manually. > Altera's floor planner is a joke when compared to xilinx. And, Altera > does not even have FPGA editor (for manual tweeking). Stratix and Cyclone are perfectly well suited to high-speed logic. We have customers running at 300+ Mhz. As for comparisons vs. competitive offerings, your best bet is to download the free P & R tools (such as Quartus Web Edition) and run your own tests with a real design. You will likely be pleasantly surprised at the results. As for achieving timing closure and doing manual tweaks, take a look at appliation note AN198. As of Quartus II 3.0 (which should be out shortly), we offer a new Chip Editor feature and a bunch of timing-closure features that you may find handy. I've never floorplanned a design nor used Xilinx's tools to do so, so I can't comment on your comparison. But in general, we find that while some designs benefit from floorplanning for timing closure; most designs (in Stratix and Cyclone) do not. The first step when we receive a design that is not hitting timing is for us to try removing the user's region constraints -- this often does the trick! As far as routing by hand goes... I honestly haven't ever seen a case where a human could beat the Quartus router (barring major bugs). Ignoring congestion, the router should find the fastest path every time. With congestion, what appears as a sub-optimal route often turns out to be the correct choice -- if that route had been shortened, some other route would have lengthened to the point that the critical path length increased. Regards, Paul Leventis Altera Corp. (Opinions are my own)Article: 57349
tk,
The way to use the two options is as follows:
Option 1 queries the boundary-scan chain and indentifies the devices contained on it. Users are then guided through the process of associating programming data files with each device in the
chain. After this step, users can perform whichever function they require on the devices in the chain. This is the default option if you click through the wizard without changing the button settings,
Option 2 allows sophisticated users to manually create a boundary-scan chain of devices to match that on the target system by instantiating devices and programming data files on the tableau.
When the instantiated devices match the composition of the boundary-scan chain the user can then perform operations on the devices as required. If the instantiated boundary-scan chain in
iMPACT does not match the physical chain of the target system, you get errors of the sort you experienced
tk wrote:
the problem is solved!
There are two options in iMPACT in bounday-scan chain:
1. Automatically connect to cable and identify Boundary-Scan chain
2. Enter a Boundary-Scan Chain
If I choose 2, only the xc2vp7 is chosen, which causes the error.
If I choose 1, there are 2 devices detected in the bounday-scan chain,
namely xccace and xc2vp7. The xc2vp7 can be successfully programmed in this
case by assigning the correct .bit file.
"tk" <tokwok@hotmail.com> ¼¶¼g©ó¶l¥ó news:bde17q$igm$1@www.csis.hku.hk...
I'm quite sure that the physical cable connection is ok
actually, the platform I use is ML300 and I try to program the xc2vp7 via
the
Parallel Cable IV. Does anyone have the experience on it ? Are there any
settings on the ML300 board I should pay attention to ?
Thanks in advance.
tk
"Neil Glenn Jacobson" <neil.jacobson@xilinx.com> wrote in message
news:3EF9F98F.30402@xilinx.com...
iMPACT is telling you that you are getting all 0's back from the device
when it is expecting the IDCODE. Assuming the device is currently
unprogrammed, I would first check your physical cable connections to the
device making certain that the device itself and the cable are both
properly powered
This error does not appear to be related to the software
tk wrote:
Hi all,
I get the following error when I try to program xc2vp7 device using
iMPACT
(ISE 5.1i):
ERROR:iMPACT:583 - '1': The idcode read from the device does not match
the
idcode in the bsdl File.
INFO:iMPACT:629 - '1': Device IDCODE :
00000000000000000000000000000000
INFO:iMPACT:630 - '1': Expected IDCODE:
00000001001001001010000010010011
I've found that this problem is discussed in the Xilinx web page:
http://support.xilinx.com/xlnx/xil_ans_display.jsp?iLanguageID=1&iCountryID=
1&getPagePath=16490
However, I don't use the encryption function for the bitstream. Why I
still
get the problem?
Even I install the service pack 3, the problem is still there.
Can anyone kindly tell me how to solve it?
Thanks in advance.
tk
PS: the following are the options used by BitGen:
Summary of Bitgen Options:
+----------------------+----------------------+
| Option Name | Current Setting |
+----------------------+----------------------+
| Compress | (Not Specified)* |
+----------------------+----------------------+
| Readback | (Not Specified)* |
+----------------------+----------------------+
| CRC | Enable** |
+----------------------+----------------------+
| DebugBitstream | No** |
+----------------------+----------------------+
| ConfigRate | 4** |
+----------------------+----------------------+
| StartupClk | JtagClk |
+----------------------+----------------------+
| DCMShutdown | Disable** |
+----------------------+----------------------+
| DisableBandgap | No** |
+----------------------+----------------------+
| CclkPin | Pullup** |
+----------------------+----------------------+
| DonePin | Pullup** |
+----------------------+----------------------+
| HswapenPin | Pullup* |
+----------------------+----------------------+
| M0Pin | Pullup** |
+----------------------+----------------------+
| M1Pin | Pullup** |
+----------------------+----------------------+
| M2Pin | Pullup** |
+----------------------+----------------------+
| PowerdownPin | Pullup** |
+----------------------+----------------------+
| ProgPin | Pullup** |
+----------------------+----------------------+
| TckPin | Pullup** |
+----------------------+----------------------+
| TdiPin | Pullup** |
+----------------------+----------------------+
| TdoPin | Pullnone |
+----------------------+----------------------+
| TmsPin | Pullup** |
+----------------------+----------------------+
| UnusedPin | Pulldown** |
+----------------------+----------------------+
| GWE_cycle | 6** |
+----------------------+----------------------+
| GTS_cycle | 5** |
+----------------------+----------------------+
| LCK_cycle | NoWait** |
+----------------------+----------------------+
| Match_cycle | NoWait |
+----------------------+----------------------+
| DONE_cycle | 4** |
+----------------------+----------------------+
| Persist | No* |
+----------------------+----------------------+
| DriveDone | No** |
+----------------------+----------------------+
| DonePipe | No** |
+----------------------+----------------------+
| Security | None** |
+----------------------+----------------------+
| UserID | 0xFFFFFFFF** |
+----------------------+----------------------+
| ActivateGclk | No* |
+----------------------+----------------------+
| ActiveReconfig | No* |
+----------------------+----------------------+
| PartialMask0 | (Not Specified)* |
+----------------------+----------------------+
| PartialMask1 | (Not Specified)* |
+----------------------+----------------------+
| PartialMask2 | (Not Specified)* |
+----------------------+----------------------+
| PartialGclk | (Not Specified)* |
+----------------------+----------------------+
| PartialLeft | (Not Specified)* |
+----------------------+----------------------+
| PartialRight | (Not Specified)* |
+----------------------+----------------------+
| Encrypt | No** |
+----------------------+----------------------+
| Key0 | pick* |
+----------------------+----------------------+
| Key1 | pick* |
+----------------------+----------------------+
| Key2 | pick* |
+----------------------+----------------------+
| Key3 | pick* |
+----------------------+----------------------+
| Key4 | pick* |
+----------------------+----------------------+
| Key5 | pick* |
+----------------------+----------------------+
| Keyseq0 | M* |
+----------------------+----------------------+
| Keyseq1 | M* |
+----------------------+----------------------+
| Keyseq2 | M* |
+----------------------+----------------------+
| Keyseq3 | M* |
+----------------------+----------------------+
| Keyseq4 | M* |
+----------------------+----------------------+
| Keyseq5 | M* |
+----------------------+----------------------+
| KeyFile | (Not Specified)* |
+----------------------+----------------------+
| StartKey | 0* |
+----------------------+----------------------+
| StartCBC | pick* |
+----------------------+----------------------+
| IEEE1532 | No* |
+----------------------+----------------------+
| Binary | No** |
+----------------------+----------------------+
* Default setting.
** The specified setting matches the default setting.
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