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I've had good success with Synplify for MSB or LSB based shift registers. No problems. Other tools may give other results. Some versions of some tools may have the SRL output come directly from the LUT or from the register attached to the LUT. If you're not pushing your design, you'll get fine results with eaither. "Hal Murray" <hmurray@suespammers.org> wrote in message news:veajr7kvs2efe6@corp.supernews.com... > >Absolutely... if you feed into the lsb and do not reset those nets, > >you can obtain resource savings (flops and routing) by letting the > >tools infer an SRL: > > Are the tools not smart enough to recognize the other pattern? > (left shift vs right shift, if you want to think that way) > > The SRL only goes in one direction, but the software could/should > be smart enough to assign FFs in either order. (or for that matter, > to find a chain of arbitrarily named signals that don't go anyplace > other than the input of the next FF.) > > -- > The suespammers.org mail server is located in California. So are all my > other mailboxes. Please do not send unsolicited bulk e-mail or unsolicited > commercial e-mail to my suespammers.org address or any of my other addresses. > These are my opinions, not necessarily my employer's. I hate spam. >Article: 56626
Say you can't use an SRL, as in: output <= sr[3]; sr[3] <= sr[2]; sr[2] <= sr[1]; sr[1] <= sr[0]; sr[0] <= input && sr[1] && sr[2]; Are there architecture-driven advantages (speed, logic utilization, etc.?) for going LSB-to-MSB vs MSB-to-LSB on Virtex 2? -- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ Martin Euredjian To send private email: 0_0_0_0_@pacbell.net where "0_0_0_0_" = "martineu"Article: 56627
Using iMPACT, try IDCODE looping to see if there are any noise issues that could be interfering with JTAG programming. Any failures mean that JTAG operations are at risk. Are there any other devices in the JTAG chain? -ArthurArticle: 56628
Philippe Molson wrote: > Hi, > We've already committed to Xilinx because we have plunked down $7K for a development card from Nallatech. I need Xilinx cores... Salman > You can try the Altera divider (LPM_DIVIDE) which supports any bit > width. > If you are using Simulink, install DSP Builder (which contains the > divider block) from : > > http://www.altera.com/products/software/system/products/dsp/dsp-builder.html > > Then you can simulate and evaluate in Simulink the Altera Divider > block in your MDL model. > > Philippe Molson > Altera > > > Salman Sheikh <sheikh@pop500.gsfc.nasa.gov> wrote in message > news:<bc2jdm$74$1@skates.gsfc.nasa.gov>... >> Hello, >> >> I modeled my system in Xilinx System Generator and Matlab (using floating >> then fixed point blocks). I found I need to divide a 31 bits number by a >> 24 bits number and need to retain a 44 bit result consisting of an 8 bits >> representing the integer result and 38 bits the fractional part. I tried >> using the Xilinx pipelined divider core but it only handles 32 bit >> remainder or fraction. Anybody have any idea where I can get a core or >> should I try to code this thing from scratch (extremely painful)? >> >> >> Thanks in advance. >> >> >> SalmanArticle: 56629
>If you want better randomness, you can use eight LFSRs of different >length, each generating one bit of the output. Do you get good randomness if you clock a single LFSR 8 steps? I think so, but I'm not smart enough to prove it and I've been tricked by similar things. -- The suespammers.org mail server is located in California. So are all my other mailboxes. Please do not send unsolicited bulk e-mail or unsolicited commercial e-mail to my suespammers.org address or any of my other addresses. These are my opinions, not necessarily my employer's. I hate spam.Article: 56630
Hi, I want to get into FPGA's but havnt the first clue about how to go about it. I would like to learn, hands on projects, about how to use and program FPGA's. I have a very small budget so the less I can spend the better. Can anyone suggest where to start Cheers, Nick -- ------------------oOo------------------------------- Mr Nick Young - MIEE MEng (Hons) nick_young@talk21.com http://www.nickbits.co.ukArticle: 56631
> I'm asking because I wonder how difficult it would be to write one's > own synthesizer and router, if only to see if it can be done without > years of man-hours invested. Most manufacturers give you detailed bitstream information after you signed an NDA. Even if they didn't, reverse-engineering the bitstream format is the easiest part of "roll my own toolchain". Apart from the sheer complexity of such an undergoing, you face another difficult problem: you can't estimate the timing unless you have insider information (which often is not available, not even under NDA). Timing analysis is very complex, and the manufacturer may also reserve special margins for future process changes. Even when you examine a given silicon, you can't build a reliable timing model for that series. You have to add safety margins (voiding your product for state-of-the- art designs), or reverse-engineer the manufacturers' toolchain. And last not least, the manufacturers have a big database of known problems and bugs. You are likely to oversee the same problems, and they remain unfixed until the users report those bugs to YOU (again). Your product will be inferior to the "original" unless it is employed as widely as, say, GNU G++. MarcArticle: 56632
yes, but we used SiI 178 transmitter, from Silicon Image or TI, to generate the TMDS signal the VirtexII just need to output a De ( combination of Line and Frame blanking) a Vsync and Hsync and the pixel data pyng Martin Thompson <martin.j.thompson@trw.com> wrote in message news:<u4r2youcy.fsf@trw.com>... > Hi all, > > Has anyone out there successfully implemented a DVI (Digital Video > Interface) in a Virtex-II (or any other FPGA for that matter)? The > tricky bit seems to be the physical layer which is > sort-of-differential-but-not-really (it's called TMDS - transition > minimised digital signalling). I'm sure there's a nifty way of doing > it though... > > Thanks in advance! > MartinArticle: 56633
Hal, I am not an expert either. But my first question always is: Do you need randomness to cover all instances, to generate noise, or in other ways to "fight mother nature"? In that case the rules are very relaxed, and LFSRs can be useful in many ways. And LFSRs with repetition rates of years or millenia are very cheap. (16 bits per LUT in Xilinx devices) Or: Are you fighting a smart enemy trying to crack your code the help of with hundreds of computers? In that case, LFSRs are just one of many building blocks for very sophisticated systems. That's out of my range of expertise. Peter Alfke ============================ Hal Murray wrote: > > >If you want better randomness, you can use eight LFSRs of different > >length, each generating one bit of the output. > > Do you get good randomness if you clock a single LFSR 8 steps? > > I think so, but I'm not smart enough to prove it and I've been > tricked by similar things. > > -- > The suespammers.org mail server is located in California. So are all my > other mailboxes. Please do not send unsolicited bulk e-mail or unsolicited > commercial e-mail to my suespammers.org address or any of my other addresses. > These are my opinions, not necessarily my employer's. I hate spam.Article: 56634
"Suhaib Fahmy" <sf199@doc.ic.ac.uk> wrote in message news:Pine.LNX.4.50.0306101252440.21396-100000@kiwi.doc.ic.ac.uk... > I am using the Coregen Dual-Port Virtex II Block Ram. In Coregen, you > can simply enter a 0 and it should initialise all your entries to '0'; > But when I simulate (functional) in Modelsim I get 'X's. I have also > tried using the Memory editor to create a COE file, and it created a > .mif, which was referenced in the component declaration. But still in > Modelsim, I get X's. Is there something else I should be doing? > > Thanks. > Hi, If I remember correctly, you need to put the .mif file in the directory where your simulation is running. Regards, Alvin.Article: 56635
"tote" <tote_last@yahoo.de> wrote in message news:91e0be86.0306100201.1c354e67@posting.google.com... > I'm generating a edf file with Symplify Pro. When I want to > place&route or generate a bit file with the project navigator, the > XILINX tool doesn't use my ucf file with all my pin assignments. This > does not happen when I synthesise the whole design with the project > navigator. > Anyway I can see all the constraints and pin assignments in the > constraints editor (exactly what is in the ucf file) but the tool > generates another pin assignment. > > Does anybody have an idea why this could happen? Does it have anything > to do with the pcf file? > > Thanks for any help. > > Thorsten Hi, Which ISE version are you using? I know that the behaviour for automatically including .ucf files changed a bit: in the old versions, doing P&R based on a top.edf would automatically include the top.ucf file when it existed; currently, the top.ucf must be included explicitely. Apart from the .pcf, there might also be an .ncf file generated by Synplify, so there is lots of room for conflicting constraints. Do you capture all logs and check them for errors and mentioning of the above files? Regards, Alvin.Article: 56636
In article <3EE61F1F.9366B1F2@xilinx.com>, Peter Alfke <peter@xilinx.com> wrote: >Or: Are you fighting a smart enemy trying to crack your code the help of >with hundreds of computers? In that case, LFSRs are just one of many >building blocks for very sophisticated systems. That's out of my range >of expertise. In THIS case (cryptographic adversary), LFSRs "Blow Dead Goats" compared to other options such as a good block cipher in CTR mode, or Blum Blum Shub, or any of a dozen other cryptographic primitives. AES is ~10 BlockRAMs, ~800 LUTs for a design which can operate at 1.3 Gbps in a Spartan II. CTR mode is good for ~2^64 encryptions before you need to change keys, so if you are using it as a PRNG, its good for 2^(64+9) bits before you should rekey. Yeah, its a LOT bigger than a few LFSRs, but its much more solid from a crypto standpoint. -- Nicholas C. Weaver nweaver@cs.berkeley.eduArticle: 56637
On 9 Jun 2003 13:10:34 -0700, kalimuddin@hotmail.com (Muhammad Khan) wrote: >Hi there , > >I am Khan and I have a problem regarding material suppiled by Xilinx. Ther is nothing wrong with the Xilinx "material". >I am using Xilinx FPGA Editor to view the placed route in actual >hardware. The problem is the proper pin assignment. For example in my >Constraint file I define signal X to pin 57 and when I observed that >particular signal in the editor than I find that this signal is being >placed at pin 107. The problem will be with the way you are specifying the constraint in the constraint file, or whether the constraints are even being read in. Either you have the syntax wrong, or you are not processing the file correctly. The place and route process produces several] report files. If there is a syntax error in your constraints, it will be reporting an error, assuming that the constraint file was correctly supplied. Constraints can come from many places .UCF, .NCF, .NGC (probably), and via the EDIF files. These are all combined by NGDBUILD. The MAP phase creates an output file of <design-name>.PCF that has the combined constraints. You should look at this file and see if your constraint is in there, and if it is correct. Until this is correct, there is no point in continuing. >I am using actual hardware to implement my design >so I can not just download the code in to chip. Right. You need to get this right, or else you will damage things. Another file you will need to look at, and is much easier than the FPGA editor (if all you want to do is check the pinout constraints) is to check the <design-name>.PAD file that reports the actual pin assignments. This is created by PAR. >The package I am using >is HQ240 and device is Xilinx Vertex XCV600 with speed 4. I used all >the above mentioned parameter in my project file. > >Does any body have any idea how to overcome this problem. See above. >Thanking you in advance. I hope this gets you to where you want to be. Philip Freidin Philip Freidin FliptronicsArticle: 56638
"Wes." <spamthis@hayclan-oz.com> wrote in message news:<RIKdnYeX9Omq9HijXTWcpw@giganews.com>... > Hi All, > > I have several embedded system boards and one of them has a faulty MACH210A > IC and I am unable to get the data off the other boards due to the security > fuse on the IC is blown. Does anyone know if it is possible to overcome the > security fuse and recover the data? Are there any specialty companies that > can do this kind of work? > > Thanks in advance > > Wes. http://www.bltinc.com/Services.CPLD-Reverse-Engineering.htmArticle: 56639
As a hardware-oriented guy, I have been watching this thread in amazement. The difference between calling something LSB or MSB, or bit number whatever is just in your mind. The circuitry does not give a damn, it just shifts the content of one latch or flip-flop into the neighbor that it is connected to. Whether you call that left-shift or right-shift is entirely up to you, ditto for the bit numbering. Physically, the carry logic goes vertically up ( in Xilinx parts), and LFSR shifting is towards the higher binary address, but that should not be confused with an architectural limitation. A name is just a name... Peter Alfke Martin Euredjian wrote: > > Say you can't use an SRL, as in: > > output <= sr[3]; > sr[3] <= sr[2]; > sr[2] <= sr[1]; > sr[1] <= sr[0]; > sr[0] <= input && sr[1] && sr[2]; > > Are there architecture-driven advantages (speed, logic utilization, etc.?) > for going LSB-to-MSB vs MSB-to-LSB on Virtex 2? > > -- > ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ > Martin Euredjian > > To send private email: > 0_0_0_0_@pacbell.net > where > "0_0_0_0_" = "martineu"Article: 56640
>This 5V trouble is also true of PCI cards. There are still _many_ 5V PCI cards >around. All you need is one 5V card in a backplane and your 3.3V limited >FPGA card is in trouble... Does anybody make PCs with 3V PCI slots? Can I get a motherboard at Fry's? Seems like a chicken/egg problem. All the PCI cards I've seen only have the 5V slot cutout so they wouldn't fit into a 3V only system. So why would anybody make a PC with 3V slots if there aren't any cards to go into them? Best clean idea I know about is to use a PCI-PCI bridge chip and put your FPGA on the isolated bus with nothing else on it. The bridge adds other problems, obviously, but they might be worth it to use the new/big FPGAs. Several years ago, I put a scope on a 5V PCI system. Nothing went over 3V. We were considering cheating for a research project. -- The suespammers.org mail server is located in California. So are all my other mailboxes. Please do not send unsolicited bulk e-mail or unsolicited commercial e-mail to my suespammers.org address or any of my other addresses. These are my opinions, not necessarily my employer's. I hate spam.Article: 56641
I don't know much about Altera but I have learned quite a bit about the bitstream by looking at the Xilinx tool outputs. Some of the output files tell exactly where the bits are in the bitstream. You can do a design with one LUT read it in to the FPGA editor and change the LUT value. Then use the partial bitstream capability to see how the bitstream changes. Steve "Peter Sommerfeld" <petersommerfeld@hotmail.com> wrote in message news:5c4d983.0306100645.715207af@posting.google.com... > Has anyone figured out (or tried to) the format of the bitstream used > to configure an FPGA. Obviously each vendor's, and maybe each part's, > bitstream format is different. > > I'm curious if it just serially goes along and sets up 16x1 LUTs (in > the 4-input LUT case), and then there are all the special cases for > embedded RAMs, MACs, etc. I suppose by making a one-LE circuit with > the LE manually placed, and then making another one-LE circuit with > the LE placed one LE to the right, etc, and then diff'ing the > bitstream, one could eventually determine the bitstream layout. Or > maybe it is much more involved? > > I'm asking because I wonder how difficult it would be to write one's > own synthesizer and router, if only to see if it can be done without > years of man-hours invested. > > -- PeteArticle: 56642
Hal Murray wrote: >>If you want better randomness, you can use eight LFSRs of different >>length, each generating one bit of the output. >> >> > >Do you get good randomness if you clock a single LFSR 8 steps? > > Of course, but you also get a sequence that is 1/8th as long. Actually, it often works out better, as the sequences are generally 2^n-1, so dividing that by 8 still gives the full length, but the sequence ends up repeating itself rotated by one bit at a time, 8 times. So, that may compromise the validity of the randomness, depending on the application. If it is for cryptographic purposes, it would be a disasterous compromise of the randomness. If it was to feed white noise to a filter for audio testing or some similar purpose, it is probably OK. The idea of having 8 different-length LFSRs is really good! JonArticle: 56644
Krzysztof Szczepanski wrote: >Hello > >I have a problem with programming the XC95288-HQ208-15 device. I can see the >chip in JTAG chain and I can erase it. Unfortunately, a program process was >failed. >I have used the ISE 5.2.02i and the ISE 5.2.03i software. >In the ISE 5.2.02i a program process was failed. >In the ISE 5.2.03i a program process was hanged. > >The device worked correctly for 2 years and now I was trying to reconfigure >it. > >Did anybody have a similar problem? > >Regards, >Krzysiek > > > > I have run into this a number of times. Are you using the Parallel Cable III? It has some flakyness in the design, and will not work with the parallel port chip on some computers. The symptom is the programming process dies at some point in the process, usually complaining about the state of the JTAG controller in the chip. I have found that other computers are totally reliable, and will program chips hundreds of times without a squawk. So, you might want to try the programming on a different computer system. One other possibility is noisy power or a weak power supply on the board the 9500 part is on. It seems that the erase or program operation requires a MUCH higher power supply current than normal operation. (I think there's a charge pump that only runs during these operations, to supply the voltages necessary for changing the flash memory.) If the +5 V power supply droops under the load, the part will fail to program. Note that a power supply that is TOTALLY adequate for normal operation of the chip will not be sufficient to power it during ISP! Jon > > >Article: 56645
'When I use a word,' Humpty Dumpty said, in a rather scornful tone,' it means just what I choose it to mean, neither more nor less.' 'The question is,' said Alice, 'whether you can make words mean so many different things.' 'The question is,' said Humpty Dumpty, 'which is to be master - that's all.' I could not say it better. Peter Alfke ============================= Peter Alfke wrote: > > As a hardware-oriented guy, I have been watching this thread in amazement. > The difference between calling something LSB or MSB, or bit number > whatever is just in your mind. The circuitry does not give a damn, it > just shifts the content of one latch or flip-flop into the neighbor that > it is connected to. Whether you call that left-shift or right-shift is > entirely up to you, ditto for the bit numbering. > Physically, the carry logic goes vertically up ( in Xilinx parts), and > LFSR shifting is towards the higher binary address, but that should not > be confused with an architectural limitation. A name is just a name... > Peter Alfke > > Martin Euredjian wrote: > > > > Say you can't use an SRL, as in: > > > > output <= sr[3]; > > sr[3] <= sr[2]; > > sr[2] <= sr[1]; > > sr[1] <= sr[0]; > > sr[0] <= input && sr[1] && sr[2]; > > > > Are there architecture-driven advantages (speed, logic utilization, etc.?) > > for going LSB-to-MSB vs MSB-to-LSB on Virtex 2? > > > > -- > > ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ > > Martin Euredjian > > > > To send private email: > > 0_0_0_0_@pacbell.net > > where > > "0_0_0_0_" = "martineu"Article: 56646
Peter Alfke <peter@xilinx.com> wrote: >As a hardware-oriented guy, I have been watching this thread in amazement. >The difference between calling something LSB or MSB, or bit number >whatever is just in your mind. The circuitry does not give a damn, it >just shifts the content of one latch or flip-flop into the neighbor that >it is connected to. Whether you call that left-shift or right-shift is >entirely up to you, ditto for the bit numbering. >Physically, the carry logic goes vertically up ( in Xilinx parts), and >LFSR shifting is towards the higher binary address, but that should not >be confused with an architectural limitation. A name is just a name... It's true that it shouldn't be described as an architectural limitation. Synthesis tool limitations are a real problem, though. Generally, if the tool can recognise the complex function that's coded, it can match it to a built in library function and implement it with fewer gates and higher speed. However, in the case of the example given, I don't think it's likely to make much difference. Martin could check for himself by synthesising a minimal version of both examples and examining the back-annotated VHDL code. -- Dave FarranceArticle: 56647
"Where can I get cheap development tools for programmable devices?" You see that question frequently in this group. Brian Dipert has written a nice article in EDN on just that subject. Go to: http://www.e-insite.net/ednmag/index.asp?layout=article&articleid=CA300026&pubdate=5%2F29%2F2003 Bob Perlman Cambrian Design WorksArticle: 56648
Andras Tantos wrote: > > >>How much delay skew do you need ? - it might be cleaner to > >>apply the same idea to an external tiny-logic gate, where the > >>Vcc range can be wider, and there is no Vcc/Gnd competing noise > > The problem there is that the interface levels are tied to the VCC while the > Xilinx FPGA has different VCCIO and VCCINT voltages. The delay I need is in > the 30-40ns range total but I would like to have taps at each 2-3ns point. That's relatively coarse, by modern device standards. If you can tolerate quantize jumps, of this order, then a simple digital multi-tap delay line should do ? If the circuit self-centers, (by the phase comp action) then the temp/batch/routing variations are taken care of. -jgArticle: 56649
Jon Masters wrote: > I am trying to persuade Xilinx's abomination of gdb to allow me to step > through the startup code on a Virtex II Pro using their stub and JTAG > cable debugging support kit. I can trace regular C code as one would > expect but even after verifying the code is being compiled with > appropriate '-g' or '-gstabs' flags[0] and so forth - I am frustrated. > Any helpful comments appreciated. The following works on microblaze via xmd and mb-gdb. I expect it will be slightly different on PPC, so you might have to think about it a bit or even, gasp, read the gdb documentation... get xmd connected to the ppc target fire up the debugger open the console window enter these commands: file myprogram.elf target remote localhost:1234 load stepi now with stepi/nexti you can single step through the assembly startup sequence. Don't use "step/next", because they will race ahead until the first C symbol info is found, ie at main(). Another useful tip with gdb is to say "break *0xdeadbeef" where 0xdeadbeef is whatever arbitrary address you want to stop at - helpful if you don't have symbol infomation in the elf file. John
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