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I have run Quartusii 2.2 SP2 on Slackware 9.0. I think because Redhat 9.0 adopt LWP lib instead of LinuxThreads lib,so Quartusii 2.2 might not runs well on Redhat 9.0. leon "H. Peter Anvin" <hpa@zytor.com> wrote in message news:bd8mr9$cm4$1@cesium.transmeta.com... > Since I see that some Altera people are reading this group... the > current version of Quartus II has a Linux version, which I have access > to; however, it's a Winelib application and they only formally support > RedHat 7.1, which is ancient by now. It does not work on my RedHat 9 > workstation. > > Does Altera have any plans to upgrade this to a modern version of > Linux? > > -hpa > -- > <hpa@transmeta.com> at work, <hpa@zytor.com> in private! > "Unix gives you enough rope to shoot yourself in the foot." > Architectures needed: ia64 m68k mips64 ppc ppc64 s390 s390x sh v850 x86-64Article: 57176
Followup to: <bdatl3$1ivc3$1@ID-185326.news.dfncis.de> By author: "leon qin" <leon.qin@2911.net> In newsgroup: comp.arch.fpga > > I have run Quartusii 2.2 SP2 on Slackware 9.0. > I think because Redhat 9.0 adopt LWP lib instead of LinuxThreads lib,so > Quartusii 2.2 might not runs well on Redhat 9.0. > Yeah, unfortunately not. However, LinuxThreads was quite frankly so broken so we (the Linux community) really need to move forward. NPTL is a much nicer threading library. -hpa -- <hpa@transmeta.com> at work, <hpa@zytor.com> in private! "Unix gives you enough rope to shoot yourself in the foot." Architectures needed: ia64 m68k mips64 ppc ppc64 s390 s390x sh v850 x86-64Article: 57177
Rene Tschaggelar <tschaggelar@dplanet.ch> wrote in message news:<8245b847a9b07918c6f46ec55662a58c@free.teranews.com>... > GC wrote: > > Hi all, > > I have the following problem compiling my project with Quartus II on > > EP1K100QC208-3 (Acex 1K family): resources utilization is under limits > > (4537/4992 LEs, 34816/49152 mem bits, 84/147 pins) and if I remove all pin > > assignments the project compiles properly. When I set pin assignments the > > compilation process can not end successfully, with several error messages > > like this: "Can't route source node ....". > > I don't know how I can solve this problem. > > Any suggestion would be highly appreciated. > > There are several options to be checked to get the full > routing possibilities. I wouldn't know them off memory. > You already have the pcb made and therefore cannot > reassign pins for a better routing, haven't you ? > > Rene Thanks for your attention. Yes I can not reassign pins because pcb is already made. Could you give me any suggestion to improve routing capabilities? I have tried with custom regions but without usefull results. AndreaArticle: 57178
stenasc@yahoo.com (Bob) writes: > Hello, > > I have constructed a 256 pt complex fft. My scaling is causing > problems as the outputs from each stage are divided by 4 to avoid > overflow. The input data and the twiddle factor coeffs are 16 bits > wide (Q15). My problem is that when the data arrives at the last two > butterfly stages of the FFT, it is non-existant, due to all the > scaling beforehand. All inputs to these stages are zero. Thus I get > nothing at the output. > As I recall it (which may not be very well, it has been a while!) an FFT only grows at a maximum of 1 bit per stage, so you would only need to divide by 2. Or have I missed something? You might be better off asking on comp.dsp... the gurus there (some of whom hang out here as well) can answer this sort of thing in their sleep. Cheers, Martin -- martin.j.thompson@trw.com TRW Conekt, Solihull, UK http://www.trw.com/conektArticle: 57179
Thanks. Nice posting, with C code too. I noticed a difference though. I use exclusively "xor" gates, while Lasse uses one "or" gate. So we treat the illegal condition where "both quadrature inputs toggle together" differently. Jean "Allan Herriman" <allan_herriman.hates.spam@agilent.com> wrote in message news:qpgffvs8q87c6t6a2shrekr3al7o9galqi@4ax.com... > On Mon, 23 Jun 2003 17:04:12 GMT, "Jean Nicolle" > <j.nicolle@sbcglobal.net> wrote: > > >Well, I wasn't aware of your posting, but looks like we came to the same > >conclusions. > > Well, the design is rather obvious, so I guess any competent engineer > would come up with an identical solution. > The earliest reference I have found to this design is from Jerry > Avins, in about 1968. (Search the comp.dsp archives for details - > Jerry is a frequent poster there.) > > >Do you have a link to your post? > > It seems to have disappeared from Google. The message id was > 35ca56ef.4862712@newshost > > Here is a slightly modified version converted to schematic (by Lasse) > http://groups.google.com/groups?oi=djq&as_umsgid=%3C36C137B5.281D73D0%40kom.auc.dk%3E%231/1 > > Regards, > Allan. > > >Jean > > > >"Allan Herriman" <allan_herriman.hates.spam@agilent.com> wrote in message > >news:7k9dfvcak1nqs07rn6khdqdtjulot80sf8@4ax.com... > >> On Sun, 22 Jun 2003 22:19:00 GMT, "Jean Nicolle" > >> <j.nicolle@sbcglobal.net> wrote: > >> > >> >Hi all, > >> > > >> >I posted a new project, quadrature decoder in an FPGA. > >> >http://www.fpga4fun.com/QuadratureDecoder.html > >> > >> This seems to be a straightforward translation of some VHDL I posted > >> in 1998. > >> > >> Allan. > > >Article: 57180
Hi all, I get the following error when I try to program xc2vp7 device using iMPACT (ISE 5.1i): ERROR:iMPACT:583 - '1': The idcode read from the device does not match the idcode in the bsdl File. INFO:iMPACT:629 - '1': Device IDCODE : 00000000000000000000000000000000 INFO:iMPACT:630 - '1': Expected IDCODE: 00000001001001001010000010010011 I've found that this problem is discussed in the Xilinx web page: http://support.xilinx.com/xlnx/xil_ans_display.jsp?iLanguageID=1&iCountryID= 1&getPagePath=16490 However, I don't use the encryption function for the bitstream. Why I still get the problem? Even I install the service pack 3, the problem is still there. Can anyone kindly tell me how to solve it? Thanks in advance. tk PS: the following are the options used by BitGen: Summary of Bitgen Options: +----------------------+----------------------+ | Option Name | Current Setting | +----------------------+----------------------+ | Compress | (Not Specified)* | +----------------------+----------------------+ | Readback | (Not Specified)* | +----------------------+----------------------+ | CRC | Enable** | +----------------------+----------------------+ | DebugBitstream | No** | +----------------------+----------------------+ | ConfigRate | 4** | +----------------------+----------------------+ | StartupClk | JtagClk | +----------------------+----------------------+ | DCMShutdown | Disable** | +----------------------+----------------------+ | DisableBandgap | No** | +----------------------+----------------------+ | CclkPin | Pullup** | +----------------------+----------------------+ | DonePin | Pullup** | +----------------------+----------------------+ | HswapenPin | Pullup* | +----------------------+----------------------+ | M0Pin | Pullup** | +----------------------+----------------------+ | M1Pin | Pullup** | +----------------------+----------------------+ | M2Pin | Pullup** | +----------------------+----------------------+ | PowerdownPin | Pullup** | +----------------------+----------------------+ | ProgPin | Pullup** | +----------------------+----------------------+ | TckPin | Pullup** | +----------------------+----------------------+ | TdiPin | Pullup** | +----------------------+----------------------+ | TdoPin | Pullnone | +----------------------+----------------------+ | TmsPin | Pullup** | +----------------------+----------------------+ | UnusedPin | Pulldown** | +----------------------+----------------------+ | GWE_cycle | 6** | +----------------------+----------------------+ | GTS_cycle | 5** | +----------------------+----------------------+ | LCK_cycle | NoWait** | +----------------------+----------------------+ | Match_cycle | NoWait | +----------------------+----------------------+ | DONE_cycle | 4** | +----------------------+----------------------+ | Persist | No* | +----------------------+----------------------+ | DriveDone | No** | +----------------------+----------------------+ | DonePipe | No** | +----------------------+----------------------+ | Security | None** | +----------------------+----------------------+ | UserID | 0xFFFFFFFF** | +----------------------+----------------------+ | ActivateGclk | No* | +----------------------+----------------------+ | ActiveReconfig | No* | +----------------------+----------------------+ | PartialMask0 | (Not Specified)* | +----------------------+----------------------+ | PartialMask1 | (Not Specified)* | +----------------------+----------------------+ | PartialMask2 | (Not Specified)* | +----------------------+----------------------+ | PartialGclk | (Not Specified)* | +----------------------+----------------------+ | PartialLeft | (Not Specified)* | +----------------------+----------------------+ | PartialRight | (Not Specified)* | +----------------------+----------------------+ | Encrypt | No** | +----------------------+----------------------+ | Key0 | pick* | +----------------------+----------------------+ | Key1 | pick* | +----------------------+----------------------+ | Key2 | pick* | +----------------------+----------------------+ | Key3 | pick* | +----------------------+----------------------+ | Key4 | pick* | +----------------------+----------------------+ | Key5 | pick* | +----------------------+----------------------+ | Keyseq0 | M* | +----------------------+----------------------+ | Keyseq1 | M* | +----------------------+----------------------+ | Keyseq2 | M* | +----------------------+----------------------+ | Keyseq3 | M* | +----------------------+----------------------+ | Keyseq4 | M* | +----------------------+----------------------+ | Keyseq5 | M* | +----------------------+----------------------+ | KeyFile | (Not Specified)* | +----------------------+----------------------+ | StartKey | 0* | +----------------------+----------------------+ | StartCBC | pick* | +----------------------+----------------------+ | IEEE1532 | No* | +----------------------+----------------------+ | Binary | No** | +----------------------+----------------------+ * Default setting. ** The specified setting matches the default setting.Article: 57181
GC wrote: > Rene Tschaggelar <tschaggelar@dplanet.ch> wrote in message news:<8245b847a9b07918c6f46ec55662a58c@free.teranews.com>... > >>GC wrote: >> >>>Hi all, >>>I have the following problem compiling my project with Quartus II on >>>EP1K100QC208-3 (Acex 1K family): resources utilization is under limits >>>(4537/4992 LEs, 34816/49152 mem bits, 84/147 pins) and if I remove all pin >>>assignments the project compiles properly. When I set pin assignments the >>>compilation process can not end successfully, with several error messages >>>like this: "Can't route source node ....". >>>I don't know how I can solve this problem. >>>Any suggestion would be highly appreciated. >> >>There are several options to be checked to get the full >>routing possibilities. I wouldn't know them off memory. >>You already have the pcb made and therefore cannot >>reassign pins for a better routing, haven't you ? >> >>Rene > > > Thanks for your attention. > Yes I can not reassign pins because pcb is already made. > Could you give me any suggestion to improve routing capabilities? > I have tried with custom regions but without usefull results. It is a while I last worked with these settings. Look at Assignment organizer, timing and such. Yes, sometimes the stories to the entries are not sufficiently descriptive, especially when you have no idea about a concept. It appears you're short of routing paths. So it might help to manually move blocks around. Rene -- Ing.Buero R.Tschaggelar - http://www.ibrtses.com & commercial newsgroups - http://www.talkto.netArticle: 57183
BTW, here is the post from 1998 that I referred to earlier: http://jamaica.ee.pitt.edu/Archives/NewsGroupArchives/comp.lang.vhdl/Aug1998/14320.txt Regards, Allan.Article: 57184
Ed Stevens <ed@stevens8436.fslife.co.uk> wrote: > Hi, > > I need to interface an IDE hard drive to a Spartan2E. The trouble is the > Spartan2E works at 3.3V and the signals coming out of the IDE hard drive are > 5V. Does anyone know a simple method to get around the voltage problem? I > don't suppose the Spartan2E could tollerate a 5V input? > > I found a company called BurchEd which sells an IDE interface to a Spartan2E > evaluation board. Looking at the picture of the IDE interface it has no > logic between the hard drive and the Spartan2E. How do they do it? The 3.3V coming out of the FPGA are related to I/O pins which are "LVTTL" compliant. LVTTL is a logic with the same Low/High thresholds as ordinary LS-TTL, with the exception that the maximum VCC does not reach 5V but only 3.3V. As an input, LVTTL tolerates the 5V level. So, you can simply connect LS-TTL circuits to the 2E (provided the pins are configured as LVTTL), and it will work. If you want to be careful, you could buffer the FPGA pins with 74LVC241 buffers or alike, but this is technically not necessary. So, effectively the BurchEd IDE interface is just a small PCB board with an IDE connector on it and some cable to plug into a port of the FPGA (there might be some 10ohm resistors in series or some buffer capacitors, but they are not relevant. HolgerArticle: 57185
Holger Veit <veit@ct-mail.citytraffic.de> wrote: >Ed Stevens <ed@stevens8436.fslife.co.uk> wrote: >> Hi, >> >> I need to interface an IDE hard drive to a Spartan2E. The trouble is the >> Spartan2E works at 3.3V and the signals coming out of the IDE hard drive are >> 5V. >The 3.3V coming out of the FPGA are related to I/O pins which are >"LVTTL" compliant. LVTTL is a logic with the same Low/High thresholds >as ordinary LS-TTL, with the exception that the maximum VCC does not reach >5V but only 3.3V. As an input, LVTTL tolerates the 5V level. So, you >can simply connect LS-TTL circuits to the 2E (provided the pins are >configured as LVTTL), and it will work. The Spartan IIE datasheet shows an absolute maximum input voltage of 4.0v. They are not 5v tolerant. In the datasheet introduction there is a one line bullet claiming "5V tolerance with external resistor". I haven't yet found anything explaining this further. Anyone have pointers to an explanation?Article: 57186
Try level translators like IDT's IDTQS3126. This converts 5V signal to 3V3 and is Bi-directional. It also does not introduce much delay. "Ed Stevens" <ed@stevens8436.fslife.co.uk> wrote in message news:bdbtk5$a86$1@newsg4.svr.pol.co.uk... > Hi, > > I need to interface an IDE hard drive to a Spartan2E. The trouble is the > Spartan2E works at 3.3V and the signals coming out of the IDE hard drive are > 5V. Does anyone know a simple method to get around the voltage problem? I > don't suppose the Spartan2E could tollerate a 5V input? > > I found a company called BurchEd which sells an IDE interface to a Spartan2E > evaluation board. Looking at the picture of the IDE interface it has no > logic between the hard drive and the Spartan2E. How do they do it? > > Thanks for any help, > >Article: 57187
g.cocchi@libero.it (GC) wrote in message news:<bbb909f0.0306240757.39a769d9@posting.google.com>... > Hi all, > I have the following problem compiling my project with Quartus II on > EP1K100QC208-3 (Acex 1K family): resources utilization is under limits > (4537/4992 LEs, 34816/49152 mem bits, 84/147 pins) and if I remove all pin > assignments the project compiles properly. When I set pin assignments the > compilation process can not end successfully, with several error messages > like this: "Can't route source node ....". > I don't know how I can solve this problem. > Any suggestion would be highly appreciated. > Thanks in advance, > > Andrea Hi Andrea, Unlocking the pins allows the fitter (place and route engine) more flexibility in placing your design, and reduces wiring demand. You are most likely running out of wiring when you lock the pins down, but not when you don't. If you send me your design I can see if I or someone else around here can fit it. There are various options we can play with, some of which aren't visible to regular users. If you can't send the design, sending the entire list of messages will let me see if you're running out of routing in much of the device, or in just a couple of hot spots. Things to check/try in the Settings->Fitter settings dialog: - Make sure "Limit to one fitting attempt is not selected." - Make sure Normal fit is selected (not fast fit). - Try turning off "Optimize Timing" during the compile. Your timing will get worse, but perhaps you can get a fit, since sometimes optimizing your design timing will hurt routability. VaughnArticle: 57188
The use of the 100 ohms is to limit the forward current into the diode clamp which is enabled for 3.3 V LVTTL. There is a wealth of information on this subject on our website. Search on: 5V virtex E, or similar combinations to get all of the answers. (ie answer 7800) Austin nospam wrote: > Holger Veit <veit@ct-mail.citytraffic.de> wrote: > > >Ed Stevens <ed@stevens8436.fslife.co.uk> wrote: > >> Hi, > >> > >> I need to interface an IDE hard drive to a Spartan2E. The trouble is the > >> Spartan2E works at 3.3V and the signals coming out of the IDE hard drive are > >> 5V. > > >The 3.3V coming out of the FPGA are related to I/O pins which are > >"LVTTL" compliant. LVTTL is a logic with the same Low/High thresholds > >as ordinary LS-TTL, with the exception that the maximum VCC does not reach > >5V but only 3.3V. As an input, LVTTL tolerates the 5V level. So, you > >can simply connect LS-TTL circuits to the 2E (provided the pins are > >configured as LVTTL), and it will work. > > The Spartan IIE datasheet shows an absolute maximum input voltage of 4.0v. > They are not 5v tolerant. > > In the datasheet introduction there is a one line bullet claiming "5V > tolerance with external resistor". I haven't yet found anything explaining > this further. > > Anyone have pointers to an explanation?Article: 57189
The problem of interfacing the spartan2E to 5 volts is current flow into the spartan's input clamp diodes. A suitably sized resistor in between the 5 volt signal and the Spartan2E input will lower this current to an acceptable level. You will need to look at the edge speed tradeoff with this approach however. Cheers; C.W. Thomas Sr. Design Engineer Bittware, Inc. "nospam" <nospam@nospam.invalid> wrote in message news:sf6jfvk0nlbemt8kgjift4btsla4f7ta80@4ax.com... > Holger Veit <veit@ct-mail.citytraffic.de> wrote: > > >Ed Stevens <ed@stevens8436.fslife.co.uk> wrote: > >> Hi, > >> > >> I need to interface an IDE hard drive to a Spartan2E. The trouble is the > >> Spartan2E works at 3.3V and the signals coming out of the IDE hard drive are > >> 5V. > > >The 3.3V coming out of the FPGA are related to I/O pins which are > >"LVTTL" compliant. LVTTL is a logic with the same Low/High thresholds > >as ordinary LS-TTL, with the exception that the maximum VCC does not reach > >5V but only 3.3V. As an input, LVTTL tolerates the 5V level. So, you > >can simply connect LS-TTL circuits to the 2E (provided the pins are > >configured as LVTTL), and it will work. > > The Spartan IIE datasheet shows an absolute maximum input voltage of 4.0v. > They are not 5v tolerant. > > In the datasheet introduction there is a one line bullet claiming "5V > tolerance with external resistor". I haven't yet found anything explaining > this further. > > Anyone have pointers to an explanation?Article: 57190
Austin Lesea <Austin.Lesea@xilinx.com> wrote: >nospam wrote: >> In the datasheet introduction there is a one line bullet claiming "5V >> tolerance with external resistor". I haven't yet found anything explaining >> this further. >The use of the 100 ohms is to limit the forward current into the diode clamp which >is enabled for 3.3 V LVTTL. >There is a wealth of information on this subject on our website. Search on: 5V >virtex E, or similar combinations to get all of the answers. (ie answer 7800) I hadn't found anything because I figured I should be looking for Spartan not Virtex datasheets and application notes.Article: 57191
Ed, You should simulate the performance of the 5V to 3.3V interface using the 100 ohm resistor and see if it meets your requirements. Simulating multiple Vcco voltages is not possible with some IBIS simulators, so you may have to get the spice models, and perform a spice simulation. Even performing a 3.3V to 3.3V IBIS simulation with a 100 ohm resistor in series will tell you if it is likely to work or not. Austin Ed Stevens wrote: > Thanks for your replies. > > I've looked at the document '5V Tolerant I/Os' on the XILINX website. Using > the 100ohm resistor would be the easiest to implement, but would it allow > bidirectional communications? > > I've looked on the XILINX website and it > "Ed Stevens" <ed@stevens8436.fslife.co.uk> wrote in message > news:bdbtk5$a86$1@newsg4.svr.pol.co.uk... > > Hi, > > > > I need to interface an IDE hard drive to a Spartan2E. The trouble is the > > Spartan2E works at 3.3V and the signals coming out of the IDE hard drive > are > > 5V. Does anyone know a simple method to get around the voltage problem? > I > > don't suppose the Spartan2E could tollerate a 5V input? > > > > I found a company called BurchEd which sells an IDE interface to a > Spartan2E > > evaluation board. Looking at the picture of the IDE interface it has no > > logic between the hard drive and the Spartan2E. How do they do it? > > > > Thanks for any help, > > > >Article: 57192
Article intended for FPGA-types has a nice summary (for dummies like me) of the state of the wire-delay/interconnect problem: http://www.us.design-reuse.com/articles/article5786.html "James Meindl at the Georgia Institute of Technology, who has become an expert in predicting the impending impact of physical parameters on future IC generations, has taken on the interconnect problem. His analysis predicts 80 levels of metal by 2014 if no architectural changes are made in circuit design." Won't happen of course. Possible solutions: get away from Manhattan routing (25% savings in wire delay--yawn), copper interconnect (been done of course, discovered from the same article that copper atoms like to diffuse into silicon, maybe it's just as well that chips become obsolete every few years), repeaters every few atoms or so (why do we keep trying to do it with electrons? Because we're *electrical* engineers, that's why), and then "Another possibility in this direction is the introduction of photonic waveguides for long interconnect lines. There is some hope here. With recent work on building photonic bandgap structures into silicon circuits, this might become a practical option for designers. Photonic structures can now be defined on-chip with the same lithographic processes used in CMOS manufacturing. Photonic interconnects do not carry the RC delay penalty that creates so many problems for wire inter connects." RMArticle: 57193
Ed, A quick hyperlynx sim with LVCMOS 3.3V 12 mA F at both ends, and a single 100 ohm reisistor at one end shows that this should work at frequencies below 50 MHz, min of 10 ns high time, or low time (pulses can get to almost 100% of Vcco, and near to ground). At higher frequencies, the pulses don't get up to the high, or down to the low value. All done using the SLOW/WEAK IBIS corner (worst case for silicon and temerature. Since the design goal is to limit the current to ~ 10 mA with the resistor, if you had a real TTL driver at the 5V end, it may not pull up to 5V at all, and you may not need a resistor (or may use a much smaller value). Austin Ed Stevens wrote: > Thanks for your replies. > > I've looked at the document '5V Tolerant I/Os' on the XILINX website. Using > the 100ohm resistor would be the easiest to implement, but would it allow > bidirectional communications? > > I've looked on the XILINX website and it > "Ed Stevens" <ed@stevens8436.fslife.co.uk> wrote in message > news:bdbtk5$a86$1@newsg4.svr.pol.co.uk... > > Hi, > > > > I need to interface an IDE hard drive to a Spartan2E. The trouble is the > > Spartan2E works at 3.3V and the signals coming out of the IDE hard drive > are > > 5V. Does anyone know a simple method to get around the voltage problem? > I > > don't suppose the Spartan2E could tollerate a 5V input? > > > > I found a company called BurchEd which sells an IDE interface to a > Spartan2E > > evaluation board. Looking at the picture of the IDE interface it has no > > logic between the hard drive and the Spartan2E. How do they do it? > > > > Thanks for any help, > > > >Article: 57194
It just depends on what you have to drive. If it is a CMOS input ( effectively zero dc load) you just figure the RC delay ( like: 100 Ohm x 50 pF = 5 ns). If there aretermination resistors, it gets more tricky... Peter Alfke Ed Stevens wrote: > > Thanks for your replies. > > I've looked at the document '5V Tolerant I/Os' on the XILINX website. Using > the 100ohm resistor would be the easiest to implement, but would it allow > bidirectional communications? > > I've looked on the XILINX website and it > "Ed Stevens" <ed@stevens8436.fslife.co.uk> wrote in message > news:bdbtk5$a86$1@newsg4.svr.pol.co.uk... > > Hi, > > > > I need to interface an IDE hard drive to a Spartan2E. The trouble is the > > Spartan2E works at 3.3V and the signals coming out of the IDE hard drive > are > > 5V. Does anyone know a simple method to get around the voltage problem? > I > > don't suppose the Spartan2E could tollerate a 5V input? > > > > I found a company called BurchEd which sells an IDE interface to a > Spartan2E > > evaluation board. Looking at the picture of the IDE interface it has no > > logic between the hard drive and the Spartan2E. How do they do it? > > > > Thanks for any help, > > > >Article: 57195
Good point! We are often the first ones to forget that we have information in strange places. Since Virtex was cost reduced, and is also known as Spartan II, and Viirtex E was further cost reduced, so it became Spartan IIE. The technical answers database which is primarily a very busy place is not very busy for Spartan II and IIE, as those questions were already answered (and are still valid) for Virtex and Virtex E. Austin nospam wrote: > Austin Lesea <Austin.Lesea@xilinx.com> wrote: > > >nospam wrote: > > >> In the datasheet introduction there is a one line bullet claiming "5V > >> tolerance with external resistor". I haven't yet found anything explaining > >> this further. > > >The use of the 100 ohms is to limit the forward current into the diode clamp which > >is enabled for 3.3 V LVTTL. > > >There is a wealth of information on this subject on our website. Search on: 5V > >virtex E, or similar combinations to get all of the answers. (ie answer 7800) > > I hadn't found anything because I figured I should be looking for Spartan > not Virtex datasheets and application notes.Article: 57196
What IDE HD are you using, what ATA version does it compliance? The T13's ATAPI-6 spec (T13/1410D rev 3b) already recommend some series termination at both device and host for UDMA. If your host and your device follow T13's spec, it seems to be all right, all signals have about 100 ohm series termination, except data lines DD[15:0] have 66 ohm,in my opinion it's probbably okay. I also attemp to build such thing (ATAPI-6) in a Spartan2E/VirtexE, let me know if this work for you? regard,Article: 57197
Hi:
I have a schematic design from Webpack 4.2 that I want to use in 5.2. I
went through the several hours of hell yesterday, finally finishing
today, figuring out how to use the new WEbpack which is a little more
convoluted than before, but I got it to work for a new test design.
Now when I try to use my old design, it complained about the syntax in
the .ucf file, and that I should use the new .xcf format, which is
ridiculous since there is no apparent way to create this. The
constraints editor with Webpack 5.2i creates a .ucf file.
So I even deleted my old .ucf file, and made a fresh one with the
contraints editor, and the darned program still gives the same errors:
=========================================================================
* HDL Analysis *
=========================================================================
Analyzing Entity <cross32> (Architecture <schematic>).
Entity <cross32> analyzed. Unit <cross32> generated.
Reading constraint file F:\xilinx\cross32\cross32.ucf.
WARNING:Xst:1574 - This style constraint file will be obsoleted in a
future release.
Please use the XCF file with a .xcf extension.
WARNING:Xst:45 - Unknown keyword: NET.
ERROR:Xst:46 - Syntax error in constraint file (line: 1).
My constraints file looks like this:
NET "IO27" LOC = "p27";
NET "IO9" LOC = "p9";
NET "IO21" LOC = "p21";
NET "IO40" LOC = "p40";
etc.
Pretty goofy since the same exact syntax works just fine in the test
design I did to figure out how to use the Webpack 5.2i.
What is going on here?
Thanks for input.
--
_______________________________________________________________________
Christopher R. Carlen
Principal Laser/Optical Technologist
Sandia National Laboratories CA USA
crcarle@sandia.gov -- NOTE: Remove "BOGUS" from email address to reply.
Article: 57198Anyone familiar with generating Microblaze uP as a component of a larger design? I have no trouble with the example Microblaze projects (EDK 3.2) when using the XPS environment only. But, if I try to generate the uP as a component an integrate using Xilinx's ISE 5.1i, when I download to the eval board nothing works (although the build appears to complete with no errors). -- Direct access to this group with http://web2news.com http://web2news.com/?comp.arch.fpga To contact in private, remove no3s8pp-1a+mmArticle: 57199
I am looking for a datasheet for this part. The Xilinx website says that to obtain a datasheet for a discontinued part you have to "open a case" with them, which requires you register with them, providing all sorts of irrelevant, but very personal details of your life, and then, "for your security", you must wait a "full business day" to confirm the registration. I'm hoping someone can dispense with this nonsense and just email me the PDF file.
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