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Hi All, I discovered that I use in my working application the x2 Clock Output as the feedback - after the GBUF - for a DLL that deskews a 48Mhz input clocks and provides to output clocks for internal usage. Is this wrong, I am not shure anymore, however I read in XAPP132 and XAPP174 that you have to use x1 output signal - after the GBUF - if you want to to make use of an internal x1 and x2 clock that are in phase, controlled by one DLL... A short note would help markus -- Mit freundlichen Grüssen Markus Meng P.S. Achtung wir haben eine neue FAX-Nummer ******************************************************************** ** Meng Engineering Telefon 056 222 44 10 ** ** Markus Meng Natel 079 230 93 86 ** ** Bruggerstr. 21 Telefax 056 222 44 34 <-- NEU !! ** ** CH-5400 Baden Email meng.engineering@bluewin.ch ** ** Web www.meng-engineering.ch ** ******************************************************************** ** You cannot create experience. You must undergo it. Albert Camus** -----= Posted via Newsfeeds.Com, Uncensored Usenet News =----- http://www.newsfeeds.com - The #1 Newsgroup Service in the World! -----== Over 80,000 Newsgroups - 16 Different Servers! =-----Article: 57626
Peter Sommerfeld wrote: > To find out where SOPC Builder is: > > Run "regedit32" from Start menu/Run. > > Look for the Software/Altera/SOPC Builder branch. This will tell you > all of the currently installed versions of SOPC Builder, and also > which one is currently active. HKCU\Software\Altera Corporation\Quartus II\2.2 has no SOPC section HKLM\Software\Altera Corporation\SOPC Builder contains SOPC_Builder_Home REG_SZ: c:\altera\excalibur\SOPC_builder which is right. > > I hope I got the branch right .. I don't have my work PC in front of > me at the moment. > > One other thing: Do you also have a separate Cygwin installed? This > can seriously screw things up. I've done this and got the symptoms you > have, and it took awhile to debug. Cygwin ? HKCU\software\cygnus solutions\cygwin is mainly empty HKLM\software\cygnus solutions\cygwin includes a pointer the Altera directory tree HKLM\System\controlset001\control\session manager\environment HKLM\System\controlset002\control\session manager\environment HKLM\System\currentcontrolset\control\session manager\environment have a path including the altera cygwin HKU\..whatever.. \software\cygnus solutions\cygwin is mainly empty A file/directory search for cygwin turns up a few more cygwin.dll. Since I don't need them anymore, I remove them. Nothing changes. Hmm. > > >>I'm trying to follow the NIOS tutorial for the Stratix1S10. >>At one point, page 16 of the 'tt_nios_hw_stratix_1s10.pdf' >>I should start the SOPC builder. A quick console window opens, >>to fast to recognize anything, and vanishes. >>There is no error message, nowhere. >>There is no SOPCBuilder as it should be according to the pdf. >>I browswed the SOPC Builder solutions in the knowledge base. >> >> From this FAQ I could gleam that the SOPC builder has to >>be installed. How can I check whether it was installed, and if >>not, where is this SOPC Builder to be found ? >> >>I'm using Quartus2 Build 176 02/04/2003 SJ Full Version >>plus the SP1 Thanks for the input anyway ReneArticle: 57627
Hello, The "glbl.v" module connects the global signals to the design, which makes it necessary to compile this module with the other design files and to load it along with the "toplevel.v" file or the "testbench.v" file for simulation. You need to compile it in the simulator, with the timing netlist. Sandeep "Jay" <yuhaiwen@hotmail.com> wrote in message news:be0h4j$117mq8$1@ID-195883.news.dfncis.de... > in ISE project navigator, when I run the 'generate post-PAR simulation > model' process, I get a warning below: > > WARNING:NetListWriters:108 - In order to compile this verilog file > successfully, please add $XILINX/verilog/src/glbl.v to your compile command. > > I'm using a GUI software, how can I change its default command line under > the button? > >Article: 57628
Hi All, some notes I could not figure out directly from one of the XAPP132, 174 from Xilinx. If I want to drive an Off-Chip device with half of the clkin frequency without using a GBUF driver, can I feedback the devided signal from the obuf driving the pin through an IBUFG and still having the DLL functionality of phase shift an duty cycle correction. I read that the feedback signam MUST be clkout or 2xclkout. The problem is that I am running out of GBUF's in my design ... markus -- Mit freundlichen Grüssen Markus Meng P.S. Achtung wir haben eine neue FAX-Nummer ******************************************************************** ** Meng Engineering Telefon 056 222 44 10 ** ** Markus Meng Natel 079 230 93 86 ** ** Bruggerstr. 21 Telefax 056 222 44 34 <-- NEU !! ** ** CH-5400 Baden Email meng.engineering@bluewin.ch ** ** Web www.meng-engineering.ch ** ******************************************************************** ** You cannot create experience. You must undergo it. Albert Camus** -----= Posted via Newsfeeds.Com, Uncensored Usenet News =----- http://www.newsfeeds.com - The #1 Newsgroup Service in the World! -----== Over 80,000 Newsgroups - 16 Different Servers! =-----Article: 57629
Dear Falk & Peter,
Thanks for replying, As Iam basic to this information, Please
correct me if iam wromg
NRZ coding say it doesn't return to 0v. For transmitting '1' +V is
used
and for transmitting '0' -V volt is used.
we have signalling standards like LVTTL, TTL, CMOS they represent '1'
as +V and '0' as 0V
What do i say the chip, which provides the NRZ interface,
1) Its signalling varies from +v to -v doesn't return to 0V
2) Or it has used NRZ coding over Some (say CMOS) signalling
standard then one is represented by + Vdd and zero is represented by
0V, am I wright..?
3) what is NRZ, is it not an line coding, i.e how to represent the 1
and 0 across the physical link ?
Thanks in Advance
Article: 57630-----Original Message----- From: Arrigo Benedetti [mailto:arrigo@bologna.vision.caltech.edu] Sent: 02 July 2003 15:06 To: Aziz AhmedSaid Subject: Re: Does anyone know about hardware implementations of the SVD ? Hi Aziz, can you please post a summary of your findings to the group? I'm very interested in computing the SVD in hardware myself. Best, -Arrigo -------------------------------------------- I have implemented the Brent Luk and Van loan SVD systolic array described in the following paper: R.P. Brent, F.T. Luk, and C. Van Loan "Computation of singular value decomposition using mesh-connected processors" J. VLSI. Comput Syst, vol. 1, no. 3, pp. 242-270, 1985. This systolic array can perform the SVD of a square N*N matrix in O(N logN) time using (N/2)^2 processors. This architecture doesn't compute singular vectors and is not suitable for (relatively) large matrices as it uses too many processors (it is the price for the speed).It suffers as well from inefficiency because each processor works for only third of the time. What I did is first make some modifications in order to improve the efficiency, adapt the array to compute singular vectors and finally I implemented it using a High-level hardware design language Handel-C. The result was a higher efficiency (more than double) a reduced computation time (divided by three) and a completely parameterized code that can be used for any matrix size, word length and FPGA target. Example: Target: Xilinx XC2000e, speed grade 6 Matrix size: 8*8 World length: 16 Area: 99 % Speed: 84 mhz Clock cycles per sweep: 3430 (for an 8*8 matrix, 3 or 4 sweeps are enough) Efficiency: 77.6 %Article: 57631
hmurray@suespammers.org (Hal Murray) wrote in message news:<vg62lr9dhc0282@corp.supernews.com>... > >The problem is the output of the PBGA seem to be producing a 1HZ pulse > >which is expected when the 28V is on but not expected when the 28V is > >turned off. The 1HZ pulse has a amplitude of 2V when the 28V is off > >but when the 28V is on, the amplitude is 5V. > > >I have tested the power supply stand-alone and it works perfectly. > >When the 28V is off, the PBGA power should be zero but in this case, > >the voltage is 1.4V when connected to the PCB. > > What's the voltage on your supply rails/planes on the side > that you expect to be off? > I have two 5 V and two 3V3 power lines. One pair (5V and 3V3) is used to power the PBGA and the other pair is used to power the SRAM and the counter. When the 28V is off, the power lines to the PBGA should turn off while the other power line should stay on to power the SRAM and the counter. > My guess is that you have some signals going from the > expect-to-be-on section to the expect-to-be-off section, > and the protection diodes are kicking in and connecting the > energy from the signals to the power rail and there is enough > power getting through for the logic to start to work. I have checked the power supply design and I think I will add a transistor circuit to switch the power lines to ground when the 28V is off. Thanks for the help. PaulArticle: 57632
So both of you are suggesting going a different direction than Altera. I have been burned twice before by prog logic parts going away. That's why I am only going to consider designing in something that is in widespread use - either Altera or Xilinix. Its got to be around for >10 years. The Xilinx XPLA3 are better parts than the MAX3000. Even the Altera FAE here admits it. But are they going to be around in the future? I know MAX3000 will be around because there are tons of people using them. I just don't know how many XPLA3 are in use. Won't touch Atmel, Lattice or anything else. Too risky, too little market share. My requirement is full 3.3V in and out. So XC2 is no good (2.5V). The Altera people told me that a new CPLD family is coming out soon. It will be lower power. Sounds like Altera has gotten very sick of hearing their parts are current hogs. Xilinx says that they also have a new CR (2.5V) part coming out, but it will probably replace the XC2 line, not XPLA3. They say XPLA3 is not going to be obsolete. Does not sound like either of you are using the XPLA3. That concerns me. Chris.Article: 57633
Gee, I wouldn't pick either of those. Of all the different FPGAs I've used the one's I liked the best were QuickLogic pASIC. They are antifuse so the code is permanent. They wake up with the brains working. Very fast, very clean, very cheap, very reliable, and wonderful to design with. Routed many parts with 100% utilization and never had a problem. Great stuff. Only downside was long prog times. Too bad they are now trying to push their Embedded product line instead of their FPGA lines. Chris.Article: 57634
lecroy <lecroy7200@chek.com> wrote: > support the Xilinx devices we use. Of course, not all > the Xilinx tools like to be co-installed, so it's multiple > computers or swap installs. All the tools co-exist from what I've seen. You just need to set your PATH and XILINX environment variables appropriately for each version. That probably precludes selecting any version of any tool from the Start menu, but you can easily write a batch file to choose a version then run the tool from the command line. (floorplanner, fpga_editor, par, pace, etc.) I don't think dropping support for old devices is too unreasonable. Otherwise the QA effort for each new software version (major, minor, even service pack) just grows bigger and bigger, and the design of the software gets more complex and messier etc. We just did something similar at my work - dropped support for old hardware in a new software version. The complexity and QA effort was killing us. At least Xilinx keep all the support notes for the old tool versions on their web site. Hamish -- Hamish Moffatt VK3SB <hamish@debian.org> <hamish@cloud.net.au>Article: 57635
<guest> schrieb im Newsbeitrag news:ee7e625.2@WebX.sUN8CHnE... > Dear Falk & Peter, > Thanks for replying, As Iam basic to this information, Please correct me if iam wromg > NRZ coding say it doesn't return to 0v. For transmitting '1' +V is used > and for transmitting '0' -V volt is used. Yes, this is right, BUT it seems you confuse an electrical IO-standard with an logic data encoding scheme. > we have signalling standards like LVTTL, TTL, CMOS they represent '1' as +V and '0' as 0V > What do i say the chip, which provides the NRZ interface, > 1) Its signalling varies from +v to -v doesn't return to 0V > 2) Or it has used NRZ coding over Some (say CMOS) signalling standard then one is represented by + Vdd and zero is represented by 0V, am I wright..? Yes, you can easyly use a CMOS IO-buffer for NRZ. As well as for Manchaster, CMI, RZ, NRZI. Again, dont mix up electrical IO-standards with encoding schemes. > 3) what is NRZ, is it not an line coding, i.e how to represent the 1 and 0 across the physical link ? Yes, NRZ is a line coding (the simples you can imagine). It is absolutely independent on the physical representation. al LOGIC "1" can be 5V, 3.3V, 20mA, +15V etc. where a logic "0" can be 0V, 0mA, -15V etc. -- Regards FalkArticle: 57636
Hi there i'm currently trying to configure Alteras JAM Player for a Mitsubishi M16 Controller to program multi vendor device JTAG chains. Input files are either *.jam (JAM file) or *.jbc (JAM-ByteCode file). Is there a (preferably free) Xilinx tool to produce either one of these file types? Where can i download the tool?Article: 57637
On Tue, 01 Jul 2003 11:16:52 -0700, Eric Crabill <eric.crabill@xilinx.com> wrote: > >Hi, > >There are a number of boards available. You should look >for a server class motherboard, one that supports PCI-X >or at least PCI at 66 MHz. A board that supports either >of those will be (by requirement) at 3.3v slot, not a 5.0v >slot. Last time I looked, there was one desktop class motherboard that seemed to fit the bill. Tyan Trinity GCSL. http://www.tyan.com/products/html/trinitygcsl.html I haven't gotten around to trying it however. - BrianArticle: 57638
On Wed, 02 Jul 2003 13:38:32 -0700, Mike Treseler <mike.treseler@flukenetworks.com> wrote: > > >Matt wrote: > >> The two FIFO array assignment statements at the bottom are the >> predominant problem.... The object is to assign the break bit to the 9th >> bit of the array of 9-bit words >> ............ >> end if; >> FIFO(FIFOhead)(7 downto 0) <= RReg; -- DUMMY >> FIFO(FIFOhead)(8) <= RxD; -- stash the break bit >> FIFO(FIFOhead)(7 downto 0) <= RReg; -- stash the received data >> ............ >> >> then both assignments work properly. There appears to be some amount >> of latency inherent in updating the variable before it can be used as an >> index, but why? > > >The change you show should not have made any difference. >Post the complete process. Something else is going on. > >Try changing if(FIFOhead = 3) to > if(FIFOhead >= 3) I agree, something else may be going on. Be aware that if : a) this is all within a single process, and b) Fifohead is a signal not a variable, the assignment of the new value to Fifohead is postponed to the end of the process (or explicit Wait) thus Fifohead will have the old value at the point of the assignments to Fifio(Fifohead). This MUST be the case to avoid race conditions within clocked processes, as a little thought will show. >> FIFO(FIFOhead)(7 downto 0) <= RReg; -- DUMMY >> FIFO(FIFOhead)(8) <= RxD; -- stash the break bit Another potential problem can arise, where the fields within a std_logic_vector are addressed by variables and must synthesise to an assignment to the whole vector. For that reason, an assignment to the whole vector is to be preferred. >> FIFO(FIFOhead)RxD & RReg; -- DUMMY However, since you use numeric constants 8, 7 downto 0 here, I don't THINK this is the problem, unless it is a tools bug. - BrianArticle: 57639
guest <> wrote: : Dear Falk & Peter, <BR> : Thanks for replying, As Iam basic to this information, : Please correct me if iam wromg <p>NRZ coding say it doesn't return to : 0v. For transmitting '1' +V is used <BR> : and for transmitting '0' -V volt is used. <p> we have signalling standards : like LVTTL, TTL, CMOS they represent '1' as +V and '0' as 0V <p>What do i : say the chip, which provides the NRZ interface, <BR> : 1) Its signalling varies from +v to -v doesn't return to : 0V <BR> : 2) Or it has used NRZ coding over Some (say CMOS) : signalling standard then one is represented by + Vdd and zero is represented : by 0V, am I wright..? <p>3) what is NRZ, is it not an line coding, i.e how : to represent the 1 and 0 across the physical link ? <p>Thanks in Advance Could you please post in ASCII and not in HTML. Especially as a "guest", please keep to the habits. Bye -- Uwe Bonnes bon@elektron.ikp.physik.tu-darmstadt.de Institut fuer Kernphysik Schlossgartenstrasse 9 64289 Darmstadt --------- Tel. 06151 162516 -------- Fax. 06151 164321 ----------Article: 57640
You guys should also look into Innoveda's Visual hdl (Now bought by Mentor, I think). It translates State Machines, Flow Diagrams, FSM into Verilog, vhdl and SystemC. All ready for synthesys.Article: 57641
Chris_S <nospam@nospam.com> wrote: : So both of you are suggesting going a different direction than Altera. : I have been burned twice before by prog logic parts going away. That's why : I am only going to consider designing in something that is in widespread : use - either Altera or Xilinix. Its got to be around for >10 years. : The Xilinx XPLA3 are better parts than the MAX3000. Even the Altera FAE : here admits it. But are they going to be around in the future? I know : MAX3000 will be around because there are tons of people using them. I just : don't know how many XPLA3 are in use. : Won't touch Atmel, Lattice or anything else. Too risky, too little market : share. : My requirement is full 3.3V in and out. So XC2 is no good (2.5V). ... XC2 (Coolrunner II) is 3.3 Volt in and out, if you provide that IO voltage. Bye -- Uwe Bonnes bon@elektron.ikp.physik.tu-darmstadt.de Institut fuer Kernphysik Schlossgartenstrasse 9 64289 Darmstadt --------- Tel. 06151 162516 -------- Fax. 06151 164321 ----------Article: 57642
My distributor (Insight, Germany) told me, there are no Spartan-3 engineering samples available or orderable yet. Also, there are no prices available. All they can say is that parts and samples can be ordered by the end of the year. Is this also true for other countries ? I urgently need some samples of the XC3S50-4PQ208C part. Can someone help me to get them ? Does Xilinx really advertise parts, that are not available, or is there another reason that Insight cant order parts for me up to now ? -Manfred Kraus mkraus_at_cesys_dot_comArticle: 57643
>So both of you are suggesting going a different direction than Altera. > >I have been burned twice before by prog logic parts going away. That's why >I am only going to consider designing in something that is in widespread >use - either Altera or Xilinix. Its got to be around for >10 years. > >The Xilinx XPLA3 are better parts than the MAX3000. Even the Altera FAE >here admits it. But are they going to be around in the future? I know >MAX3000 will be around because there are tons of people using them. I just >don't know how many XPLA3 are in use. > >Won't touch Atmel, Lattice or anything else. Too risky, too little market >share. > Hi gang - sorry for the marketing blitz below :) Hi Chris - Lattice has over 40% marketshare in CPLD, ALtera has over 40% market share in CPLD, Xilinx is ~10% in CPLD. Lattice has obsoleted very few of the CPLD device families introduced over the past 11 years ( some older MACH devices from the Vantis acquisition, mainly). Lattice offers multiple different architectures in CPLD, from 32 macrocells to 1024 macrocells, in 1.8v, 2.5v ,3.3v, and 5v. I would strongly recommend Lattice at least be given a close look.(of course I am a bit biased :) ) I am not sure where "nospam.com" is located, but I am willing to bet we have resources neardby! A local FAE would be happy to talk with you. Our downloadable LEVER3 starter software includes Synplicity for VHDL/VERILOG synthesis, ABEL and Schematic capture, funtcional and timing simulation. Supports all product families. Michael Thomas LSC SFAE New York/New Jersey 631-874-4968 fax 631-874-4977 michael.thomas@latticesemi.com for the latest info on Lattice products - http://www.latticesemi.com LATTICE - BRINGING THE BEST TOGETHERArticle: 57644
In article <3f042929$0$23100$5a62ac22@freenews.iinet.net.au>, hamish@cloud.net.au writes: |> I don't think dropping support for old devices is too unreasonable. |> Otherwise the QA effort for each new software version (major, minor, |> even service pack) just grows bigger and bigger, and the design of |> the software gets more complex and messier etc. Why would this be so? If the software is modularized, e.g. the fitter (placer/router) is its very own piece of command-line software there is no need to touch that code again (plus, doing so eases portability). If integration of the necessary calls into the GUI is an issue, well, then just leave it out. From what I read in this and other "tech" groups, developers seem to prefer to write their own batch scripts anyway. (If the shared development machines sit "two networks further", you don't want to wait for GUI updates anyway.) Just my $0.02, RainerArticle: 57645
Rene, please use mysupport.altera.com or the hotline. I have also forwarded this to the relevant group inside Altera. - Subroto Datta Altera Corp. "Rene Tschaggelar" <tschaggelar@dplanet.ch> wrote in message news:270bd5f9eee3e76944507a61ff1c81ea@free.teranews.com... > I'm trying to follow the NIOS tutorial for the Stratix1S10. > At one point, page 16 of the 'tt_nios_hw_stratix_1s10.pdf' > I should start the SOPC builder. A quick console window opens, > to fast to recognize anything, and vanishes. > There is no error message, nowhere. > There is no SOPCBuilder as it should be according to the pdf. > I browswed the SOPC Builder solutions in the knowledge base. > > From this FAQ I could gleam that the SOPC builder has to > be installed. How can I check whether it was installed, and if > not, where is this SOPC Builder to be found ? > > I'm using Quartus2 Build 176 02/04/2003 SJ Full Version > plus the SP1 > > > Rene > -- > Ing.Buero R.Tschaggelar - http://www.ibrtses.com > & commercial newsgroups - http://www.talkto.net >Article: 57646
Is there a way to generate SVF files in Quartus II? If not, is there a way to convert JAM files to SVF? TIA Petter -- A: Because it messes up the order in which people normally read text. Q: Why is top-posting such a bad thing? A: Top-posting. Q: What is the most annoying thing on usenet and in e-mail?Article: 57647
Sander Vesik <sander@haldjas.folklore.ee> wrote in message news:<1054761767.988243@haldjas.folklore.ee>... > Anybody know of Cyclone EP1C12 (preferably) or EP1C20 > (also ok) based PCI development boards? Do such things > even exist - or in other words, what is the approximate > timline after chip availability that one can expect such > to be around? Altera will be shipping a Cyclone, 1C20-based PCI development kit soon. Introduction is slated for late August. Cost will be under $1000, and it will include DDR ram and be in a short board form factor. Watch the Altera development kits page (http://www.altera.com/products/devkits/kit-dev_platforms.jsp) for details. VaughnArticle: 57648
I found this on the XILINX Website located in document: http://www.xilinx.com/products/spartan3/faq105_s3.pdf 13. When will Spartan-3 devices be available? Spartan-3 samples began shipping in March. First available devices are the XC3S1000 and XC3S50. 14. How much will Spartan-3 devices cost? Volume pricing at the end of 2004 will be under $3.50 for the XC3S50 and under $20 for the XC3S1000, and under $100 for the XCS4000 (based on 250K unit quantities).Article: 57649
Chris_S wrote: > So both of you are suggesting going a different direction than Altera. > > I have been burned twice before by prog logic parts going away. That's why > I am only going to consider designing in something that is in widespread > use - either Altera or Xilinix. Its got to be around for >10 years. > > The Xilinx XPLA3 are better parts than the MAX3000. Even the Altera FAE > here admits it. But are they going to be around in the future? I know > MAX3000 will be around because there are tons of people using them. I just > don't know how many XPLA3 are in use. > > Won't touch Atmel, Lattice or anything else. Too risky, too little market > share. > > My requirement is full 3.3V in and out. So XC2 is no good (2.5V). > > The Altera people told me that a new CPLD family is coming out soon. It > will be lower power. Sounds like Altera has gotten very sick of hearing > their parts are current hogs. > > Xilinx says that they also have a new CR (2.5V) part coming out, but it will > probably replace the XC2 line, not XPLA3. They say XPLA3 is not going to be > obsolete. > > Does not sound like either of you are using the XPLA3. That concerns me. I'm using XPLA3, about 20 or so a year :-D But they are very nice. The only thing I hate is the schematic editor, which sucks real bad, and the ISE Webpack software, which overall gets a C- . I am considering ABEL, which might take the schematic editor hell out of the picture, making the Xilinx XPLA3 an overall nice part to work with. But for your 10 years requirement, you must certainly realize that there can be no guarantees. I would look into modularizing the CPLD onto a daughterboard or something that can be reworked without changing your main board design, if you really want such a long term. Good day! -- _______________________________________________________________________ Christopher R. Carlen Principal Laser/Optical Technologist Sandia National Laboratories CA USA crcarle@sandia.gov -- NOTE: Remove "BOGUS" from email address to reply.
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