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In article <3DC0F259.A51597BA@dlr.de>, xx_markus.wolfgart@dlr.de says... > Hi NG, > > I need Your advise for may first pci-io card project. > I would like to transfer a serial data stream (ttl, ecl, > diff-ecl in nrz, bi-phase-l etc. code, up to 100mbit/s) > to hd or a raid array. > I would like to use the win driver software by jungo. > But I'm not quit sure which io-chip to take, as they > support many brands (PLX,V3,Galileo,Altera,QuickLogic, > PLDA and AMCC). I had good luck with the PLX PCI9054. It all went rather smoothly. Watch the PCI clock spec! I didn't and got away with it, but... I decided not to do the PCI stuff in the FPGA directly for bring up ease. PCI isn't the easiest thing to debug and the cost of the PLX chip was insignificant ($25 IIRC) to my time. Using the PLX part everything came up as expected, after I got the byte ordering right on the local bus. Oops. > So I'm hopeing you could give me some hints on this topic. > In addition I had to mentioned, that my pcb design tool > only support 4x multilayer pcb and I had the need to solder > the pci-chip by hand for my prototype. Depending on what you're doing, four layers is plenty. I used ten (5P5S), but I had lots of supplies and some fairly serious routing length problems elsewhere on the board. Hardware cost was not a consideration for that project. Four layers (2P2S) is plenty for the PCI portion. The chips are laid out to fan directly to the bus pins. The 9054 I used was in a PLCC package. I had the prototype company mount all the parts. I had a bunch of PGAs and an FGA anyway. There was no reason for me to attempt to solder all those tiny legs. I know people who have done it though. > Hope this constellation could make it? I don't think there's anything you've told us (so far ;-) that hasn't been done thousands of times before. ---- KeithArticle: 49076
Peter Wallace <pcw@karpy.com> writes:
> On Thu, 31 Oct 2002 02:59:35 -0800, Thomas Heller wrote:
>
> > I'm planning to configure a Spartan-II device from a small uP in slave
> > parallel mode.
> >
> > From looking at the datasheet I have the impression that the following
> > could work (the processor I want to use is an AMD Am186ED):
> >
> > Connect the processor's decoded chip select ~PCS signal to the FPGA's
> > ~WR input.
> >
> > Connect the processor's write signal ~WR to the FPGA's ~CS input, and
> > also connect this to the FPGA's CCLK input.
> >
> > Does anyone have some words of wisdom whether this should work?
> >
> > Thanks,
> >
> > Thomas Heller
>
> If you get a write signal (~WR) without a chip select (another device
> accessed), you will get a configuration abort.
> also the CCLK hold time versus CS may be a problem
>
>
> Peter Wallace
Yes, after some thinking I came to the following solution:
Connect the uP's ~WR pin to CCLK, and the uP's ~PCS pin to the
Spartan's ~CS and ~WR pin. So the FPGA's timing should be:
________ ______________
~CS == ~WR \_______/
__________ _____ _______
CCLK \___/ \__/
This looks better, doesn't it?
Thomas Heller
Article: 49077> Need a hand-holding from high-level concepts, right down to > programming techniques and tools - and the full process (obtaining the > FPGA, installing it, testing it (simulations?), supporting circuitry, > development, etc.). Have a look at http://tutor.al-williams.com -- not 100% complete, but you'll find some high level info, a Xilinx ISE tutorial with schematics and Verilog and an Alteral MAX Plus tutorial. Good luck! Al Williams AWC http://www.al-williams.com/pldhome.htmArticle: 49078
Since you're just starting out on HDL design, I'd suggest you go back and make it right (pass simulation). It seems like a lot of work, and maybe you lucked out on this early small design, but in the long run, you will NEED to depend on your simulation results. You're better off going back and doing it right on a small design then going forward with a flawed methodology. Regards President, Quadrature Peripherals Altera, Xilinx and Digital Design Consulting email: kayrock66@yahoo.com http://fpga.tripod.com ----------------------------------------------------------------------------- joefrese@hotmail.com (Joe Frese) wrote in message news:<c176b8c2.0210301440.4b91e39f@posting.google.com>... > First off, thanks to all who responded to my last post, re: FPGA > fullness. Your comments and suggestions were incredibly helpful. > > We recently purchased Active-HDL 5.1XE, and in experimenting with it, > I discovered an FPGA design that does not simulate (post > place-and-route) correctly . . . which is strange, as the design has > been tested and verified as operating correctly in actual hardware. > Digging a little deeper, I was able to identify a number of constructs > in the design that cause problems in simulation, but should NOT cause > problems in real hardware. > > Now, I could fix these areas so that the design simulates correctly, > but the problem constructs are sprinkled heavily throughout, so to do > so would be no small undertaking. My question is, therefore: how > important is it to have a completely clean simulation? Is it > important enough to renovate a working and tested design? Thanks in > advance for your input. > > Joe FreseArticle: 49079
Hi; Thanks for reading this. I have a design based on VHDL modules instantiated in a schematic. The schematic is the top. In some of the modules I have derived clocks. I need to set periods and other timing constraints. I have tried this in the VHDL modules as well as the top.ucf file. How do you get xst or whatever to use these. I even have issues with signals being optimized out and them the PAR complaining about nmot finding the signal mentioned in the ICF file. Where do you put what hierical level timing/placment constraignts? 1. IN ucf file 2. In the schematic? 3. Elsewhere? What are the rules? Thanks C.W. ThomasArticle: 49080
Thanks guys. As a follow-up to Uwe and Peter's kind replies... If the clock has the absolute capabilites of 0 and 1 (low and high) which have clear semantic in digital systems, is the "edge" exploited as a 3rd "state" - is the "transition" period (latency) recognized by circuitry and acted-upon (e.g., to "prepare" for the low state, in a falling edge, or for the high state (in a rising edge)? Further, is there any granularity in the edge beyond "being between" high and low? Can anyone offer a simplified example of the "preparation" (if this concept is proper) that a chip[set] might perform "on/at the edge"? Is this just wiggle-room, elbow-room where the "latency" of the transition is exploited by a chip[set] to perform certain actions? Phew. Thanks much for any further information. -- VirtualSean Peter Alfke <peter@xilinx.com> wrote in message news:<3DC06559.4348AA0F@xilinx.com>... > In a digital system, it is the clock that orchestrates or controls the sequence of > events ( like the conductor controlling an orchestra). The clock is itself a > digital signal that is either High or Low. In most system only one clock > transition ( "edge") really matters, in many cases it is the rising edge, the > transition from Low to High, but it might also be the opposite, from High to Low, > and in some modern systems both edges cause an action. > When you stomp your feet to the music, it is the falling edge of your foot > movement that signals the beat. > Enough analogies? > > Peter Alfke > =============== > Virtual Sean wrote: > > > <insert neophyte question> > > > > What is "clock edge"??? Anyone care to take a moment to enlighten the unwashed? > > > > Thanks much. > > > > -- > > VirtualSeanArticle: 49081
Steve Casselman wrote: > Simulations are worse case. So your design may work at 3.3v and room temps > but fail under other conditions. A static timing analysis confirms that the FPGA function, *whatever it is*, will work reliably at the specified clock frequency. A functional testbench is important for another reason. It allows me to make changes to my design and verify, right from my editor, in a few seconds, that I haven't broken any functions covered by the testbench. This means I don't have to do synthesis and place+route to verify each logic change or code "clean up" pass. -- Mike TreselerArticle: 49082
C.W. THomas wrote:
> I have a design based on VHDL modules instantiated in a schematic. The
> schematic is the top. In some of the modules I have derived clocks. I need
> to set periods and other timing constraints.
Consider deriving clock enables instead of clocks.
This makes one global fmax constraint work for everything
and will save you many hours of work.
-- Mike Treseler
Article: 49083On Thu, 31 Oct 2002 07:55:30 -0800, Thomas Heller wrote: > Peter Wallace <pcw@karpy.com> writes: > >> On Thu, 31 Oct 2002 02:59:35 -0800, Thomas Heller wrote: >> >> > I'm planning to configure a Spartan-II device from a small uP in >> > slave parallel mode. >> > >> > From looking at the datasheet I have the impression that the >> > following could work (the processor I want to use is an AMD Am186ED): >> > >> > Connect the processor's decoded chip select ~PCS signal to the FPGA's >> > ~WR input. >> > >> > Connect the processor's write signal ~WR to the FPGA's ~CS input, and >> > also connect this to the FPGA's CCLK input. >> > >> > Does anyone have some words of wisdom whether this should work? >> > >> > Thanks, >> > >> > Thomas Heller >> >> If you get a write signal (~WR) without a chip select (another device >> accessed), you will get a configuration abort. also the CCLK hold time >> versus CS may be a problem >> >> >> Peter Wallace > > Yes, after some thinking I came to the following solution: > > Connect the uP's ~WR pin to CCLK, and the uP's ~PCS pin to the Spartan's > ~CS and ~WR pin. So the FPGA's timing should be: > > ________ ______________ > ~CS == ~WR \_______/ > > __________ _____ _______ > CCLK \___/ \__/ > > This looks better, doesn't it? > > Thomas Heller That looks like it would work Also, if you dont need readback, you might be able to simply ground write... PCWArticle: 49084
VirtualSean wrote: > > If the clock has the absolute capabilites of 0 and 1 (low and high) > which have clear semantic in digital systems, is the "edge" exploited > as a 3rd "state" A D flop is really an asynchronous state machine and the concept of "edge triggering" is a simplification of what's really going on. A D flop can be made of two cascaded transparent latches. The first latch transfers the data input while the clock is low and holds it's value on an intermediate node while the clock is high. The second latch transfers the intermediate node to the Q output while the clock is high. This only works as long both the positive and negative clock pulses are wide enough and the data input is stable during the positive edge. -- Mike TreselerArticle: 49085
I am trying to run the Map tool on my current design and get the message "Error:MapLib:30 - Bad Format for LOC constraint." I have tried several different ways of entering the pins I want to reserve (some shown below) and all combinations have failed. Looking at the pinouts for the FT256, T9 has function name "GCK0, I", which is correct for my clock signal, E6 has the function "I/O, L3N" and E11 is "I/O, L15N_YY". Is there anything glaringly wrong here? NET p_clk10 LOC = T9; NET "p_k1a_cntrl" LOC = PE6; NET "p_k1a_cntrl" SLOW; NET "p_k10a_cntrl" LOC = "PE11"; NET "p_k10a_cntrl" SLOW;Article: 49086
Clocks are mostly used to "trigger" flip-flops. In the case of "rising-edge-triggered" flip-flop, it consists of a Master Latch that captures the incoming data while the clock level is Low ( and stays unaffected by input changes while the clock is High). This Master Latch drives its data into a Slave Latch that captures the incoming ( Master Latch) data when the clock is High, but remains locked up when the clock level is Low. So, effectively, the Slave Latch ends up, for a whole clock period, with the data input right before the rising clock edge. Clock level thresholds are adjusted that there is never a race condition from master input to slave output. (Analogy: Rotating hotel door, where the wind can never blow through). Peter Alfke ===================== VirtualSean wrote: > Thanks guys. > > As a follow-up to Uwe and Peter's kind replies... > > If the clock has the absolute capabilites of 0 and 1 (low and high) > which have clear semantic in digital systems, is the "edge" exploited > as a 3rd "state" - is the "transition" period (latency) recognized by > circuitry and acted-upon (e.g., to "prepare" for the low state, in a > falling edge, or for the high state (in a rising edge)? > > Further, is there any granularity in the edge beyond "being between" > high and low? Can anyone offer a simplified example of the > "preparation" (if this concept is proper) that a chip[set] might > perform "on/at the edge"? Is this just wiggle-room, elbow-room where > the "latency" of the transition is exploited by a chip[set] to perform > certain actions? > > Phew. > > Thanks much for any further information. > > -- > VirtualSean > > Peter Alfke <peter@xilinx.com> wrote in message news:<3DC06559.4348AA0F@xilinx.com>... > > In a digital system, it is the clock that orchestrates or controls the sequence of > > events ( like the conductor controlling an orchestra). The clock is itself a > > digital signal that is either High or Low. In most system only one clock > > transition ( "edge") really matters, in many cases it is the rising edge, the > > transition from Low to High, but it might also be the opposite, from High to Low, > > and in some modern systems both edges cause an action. > > When you stomp your feet to the music, it is the falling edge of your foot > > movement that signals the beat. > > Enough analogies? > > > > Peter Alfke > > =============== > > Virtual Sean wrote: > > > > > <insert neophyte question> > > > > > > What is "clock edge"??? Anyone care to take a moment to enlighten the unwashed? > > > > > > Thanks much. > > > > > > -- > > > VirtualSeanArticle: 49087
This is a multi-part message in MIME format. --------------7010260E6A23B9BB76123537 Content-Type: text/plain; charset=us-ascii Content-Transfer-Encoding: 7bit It would seem that you got the pin names incorrect by placing a "P" infront of them. Remove the "P" and it should be fine. Regards, Stephan BDoherty wrote: > I am trying to run the Map tool on my current design and get the > message "Error:MapLib:30 - Bad Format for LOC constraint." > > I have tried several different ways of entering the pins I want to > reserve (some shown below) and all combinations have failed. Looking > at the pinouts for the FT256, T9 has function name "GCK0, I", which is > correct for my clock signal, E6 has the function "I/O, L3N" and E11 is > "I/O, L15N_YY". > > Is there anything glaringly wrong here? > > NET p_clk10 LOC = T9; > > NET "p_k1a_cntrl" LOC = PE6; > NET "p_k1a_cntrl" SLOW; > > NET "p_k10a_cntrl" LOC = "PE11"; > NET "p_k10a_cntrl" SLOW;Article: 49088
In article <aprgi2$t72$1@sirius.dur.ac.uk>, Christopher Saunter <christopher.saunter@durham.ac.uk> wrote: >Dear All, > > I am investigating supplimenting a small AMD/Linux/Gigabit >Ethernet cluster we opperate with some FPGA processers. The processing >done by the cluster is carried out by parallel processes communicating via >MPI. > >I am interested in offloading some calculations (FFT ;-) to the FPGA >fabric of a V2Pro, using a RocketIO port to talk to the gigabit interlink >and using off the shelf TCP/IP and MPI code for the PPC as a basis of >bridging the hardware accelerators transparently into the cluster. You are probably going to take a pretty big latency hit going through a full TCP/IP network to communicate. You would probably do better putting FPGAs on PCI cards (which you can buy today) and using those. >So the big question is: Is anyone aware of existing or upcoming >evaluation/dev boards suitable for such an excercise? Such a board would >have a medium to large V2Pro onboard, 1 (or more ;-) RocketIOs configured >with the appropriate hardware for gigabit ethernet over copper (not fiber) >cabling, with 16+ megs of external RAM that can be used by the FPGA etc. I'm not aware of one existing, HOWEVER: You would need effectively the guts of a media converter (copper to fiber converter, minus the fiber transeiver) to use the Rocket I/Os with copper, which is NOT a serial protocol, but rather a funky 4-pair interface. -- Nicholas C. Weaver nweaver@cs.berkeley.eduArticle: 49089
Please allow me to disagree. In a properly designed master slave flip-flop, there is no requirement for the clock to rise or fall a certain way. You can have any rise or fall time you want, but that will give you a timing uncertainty, since you do not know where the threshold really is. Also, while the clock level is close to the threshold, any noise in the system can cause double-triggering, which can be really bad, especially in a state machine or in a counter. Thus there a secondary issues that recommend a swift rise and fall time, max 1 or 2 ns in modern flip-flops inside the chip, but there is no inherent edge-rate limitation. Input pins usually have a slight hysteresis and plenty of gain, so that the slow pc-board edge rate is considerably enhanced before it reaches the flip-flops inside the chip. Peter Alfke, Xilinx Applications Mike Rosing wrote: > VirtualSean wrote: > > Thanks guys. > > > > As a follow-up to Uwe and Peter's kind replies... > > > > If the clock has the absolute capabilites of 0 and 1 (low and high) > > which have clear semantic in digital systems, is the "edge" exploited > > as a 3rd "state" - is the "transition" period (latency) recognized by > > circuitry and acted-upon (e.g., to "prepare" for the low state, in a > > falling edge, or for the high state (in a rising edge)? > > > > Further, is there any granularity in the edge beyond "being between" > > high and low? Can anyone offer a simplified example of the > > "preparation" (if this concept is proper) that a chip[set] might > > perform "on/at the edge"? Is this just wiggle-room, elbow-room where > > the "latency" of the transition is exploited by a chip[set] to perform > > certain actions? > > > > Phew. > > > > Thanks much for any further information. > > There are usually requirements for an "edge" to work. Usually it's > 1/10th of a clock period, so if you have a triangle wave instead of > a square wave, your logic may not function the way you like. The > critical events usually occur when the voltage crosses a threshold, > and most of the time you want that to happen as fast as possible. > This boils down to analog functioning - the transistors can move > so many electrons so fast, and you want things to always work. > > There is also the concept of "setup and hold" time - the time before > the clock edge happens many of your signals need to be stable. Again > this is a spec defined by the underlying analog circuit. So some > signals need to change before the clock so that when the clock edge > happens all your digital information is where you want it. > > Digital electronics is still all analog components. Just lots > of 'em :-) > > Patience, persistence, truth, > Dr. mike > > -- > Mike Rosing > www.beastrider.com BeastRider, LLC > SHARC debug toolsArticle: 49090
i downloaded xapp175.zip where the implementation of a dual port 8 bit fifo is described in vhdl i need a wider fifo so i used two dual port ram_s16_s16 connected (32 bit). however when i try to read the data i stored , i do not get the correct results. i believe that the two lines of code in the S8_S8 implementation provided by xilinx need to be modified and maybe this is the source of my problem. read_linearfeedback <= NOT (read_addr(8) XOR read_addr(4)); write_linearfeedback <= NOT (write_addr(8)XOR write_addr(4)); does anyone have an opinion ? i tried (read_addr(16) XOR read_addr(8)); as an experiment but it did not work.Basically i do not know why it XORs with bit 4 . . . thank you in advanceArticle: 49091
I do not quite understand your problem. Making the data path wider does not affect the addressing The XORing of the address bits seems to be part of the linear-feedback shift register design. You should not touch that, since you are not changing the addressing. (I was not involved in this design, and I overly complicated...) What is your read clock rate, and what is your write clock rate? Do you need only FULL and EMPTY, or also ALMOST FULL and ALMOST EMPTY outputs? Let me know... Peter Alfke, Xilinx Applications ================ faidon wrote: > i downloaded xapp175.zip where the implementation of a dual port 8 bit fifo is described in vhdl > > i need a wider fifo so i used two > dual port ram_s16_s16 connected (32 bit). > however when i try to read the data i stored , i do not get the correct results. > > i believe that the two lines of code in the S8_S8 implementation provided by xilinx need to be modified and maybe this is the source of my problem. > > read_linearfeedback <= NOT (read_addr(8) XOR read_addr(4)); > write_linearfeedback <= NOT (write_addr(8)XOR write_addr(4)); > > does anyone have an opinion ? > i tried (read_addr(16) XOR read_addr(8)); as an experiment but it did not work.Basically i do not know why it XORs with bit 4 . . . > > thank you in advanceArticle: 49092
Why don't you just use two instances of the s8_s8 fifo. It will cost you a couple of CLBs, but it will run faster and will be easier to place and
route since each block RAM has its own set of address generators that way (the placer is notoriously bad at placing block rams, and unless you place
them next to one another, the routing delays will significantly hamper performance of one with shared addressing).
If you use Coregen, you can also modify the parameters to generate a fifo, but you do give up visibility into the source code in that case.
faidon wrote:
> i downloaded xapp175.zip where the implementation of a dual port 8 bit fifo is described in vhdl
>
> i need a wider fifo so i used two
> dual port ram_s16_s16 connected (32 bit).
> however when i try to read the data i stored , i do not get the correct results.
>
> i believe that the two lines of code in the S8_S8 implementation provided by xilinx need to be modified and maybe this is the source of my problem.
>
> read_linearfeedback <= NOT (read_addr(8) XOR read_addr(4));
> write_linearfeedback <= NOT (write_addr(8)XOR write_addr(4));
>
> does anyone have an opinion ?
> i tried (read_addr(16) XOR read_addr(8)); as an experiment but it did not work.Basically i do not know why it XORs with bit 4 . . .
>
> thank you in advance
--
--Ray Andraka, P.E.
President, the Andraka Consulting Group, Inc.
401/884-7930 Fax 401/884-7950
email ray@andraka.com
http://www.andraka.com
"They that give up essential liberty to obtain a little
temporary safety deserve neither liberty nor safety."
-Benjamin Franklin, 1759
Article: 49093In article <aprv0m$4uj$1@moonstone.imsb.nrc.ca>, tom.burgess@nrc.ca says... > Micrel sells a differential 2-channel part (SY55856U) that is used this way. > http://www.micrel.com/_PDF/Synergy-PDF/sy55856u.pdf > Much coarser steps (50 ps) and fewer - only 7, for +/- 350 ps delay. > And it's CML, which is nice, but it's a bit awkward to interface CML outputs > to legacy PECL chips without AC coupling. I've used the Micrel/Synergy SY100E195 as a fine delay adjust. 2nsec delay with ~20ps resolution (8 bit). These are guaranteed monotonic. I used a pair cascaded for a 4ns range. They fed SYEL92's to convert to LVPECL levels for the Virtex-E clock inputs. ...worked quite well. ---- KeithArticle: 49094
Just want see anyone here has any experience of converting a Xilinx FPGA design into an ASIC implementation. If so, which vendor did you use? What's the cost? Are you happy with the result? We are using the Virtex series and considering this option. ThanksArticle: 49095
Hello Faidon.. Xapp258 has a 36 bit fifo in both verilog and vhdl. I've used the verilog version with success. Eric Pearson "faidon" <faidon@inaccessnetworks.com> wrote in message news:ee7a1ab.-1@WebX.sUN8CHnE... > i downloaded xapp175.zip where the implementation of a dual port 8 bit fifo is described in vhdl > > i need a wider fifo so i used two > dual port ram_s16_s16 connected (32 bit). > however when i try to read the data i stored , i do not get the correct results. > > i believe that the two lines of code in the S8_S8 implementation provided by xilinx need to be modified and maybe this is the source of my problem. > > read_linearfeedback <= NOT (read_addr(8) XOR read_addr(4)); > write_linearfeedback <= NOT (write_addr(8)XOR write_addr(4)); > > does anyone have an opinion ? > i tried (read_addr(16) XOR read_addr(8)); as an experiment but it did not work.Basically i do not know why it XORs with bit 4 . . . > > thank you in advanceArticle: 49096
Tom Burgess wrote: > Micrel sells a differential 2-channel part (SY55856U) that is used this > way. > http://www.micrel.com/_PDF/Synergy-PDF/sy55856u.pdf > Much coarser steps (50 ps) and fewer - only 7, for +/- 350 ps delay. > And it's CML, which is nice, but it's a bit awkward to interface CML > outputs to legacy PECL chips without AC coupling. > Just saw the datasheets for the new TI SN65LVDS100 and SN65LVDS101. These are LVPECL/LVDS/CML to LVDS (100) or LVPECL (101) translators good to 2 GHz. regards, TomArticle: 49097
Peter Alfke wrote: > > Please allow me to disagree. > In a properly designed master slave flip-flop, there is no requirement for > the clock to rise or fall a certain way. You can have any rise or fall time > you want, but that will give you a timing uncertainty, since you do not > know where the threshold really is. Also, while the clock level is close to > the threshold, any noise in the system can cause double-triggering, which > can be really bad, especially in a state machine or in a counter. > Thus there a secondary issues that recommend a swift rise and fall time, > max 1 or 2 ns in modern flip-flops inside the chip, but there is no > inherent edge-rate limitation. Input pins usually have a slight hysteresis > and plenty of gain, so that the slow pc-board edge rate is considerably > enhanced before it reaches the flip-flops inside the chip. Hmmm - I think even this needs qualification.. :) Master-Slave implies/requires a hand-over, or make-before-break action. In an extreme slow edge case, the threshold skews could cause make-before-break to become break-before-make, so I don't agree "You can have any rise or fall time you want" - 'Properly designed' cannot eliminate threshold variations, due to process shifts, as well as practical things like local gound/vcc movement. A minimum slew rate is giving you three things - sufficently narrow time skew across multiple registers - sufficently narrow time skew within the master-slave core - Improves noise margin, as Q driven bounce in CMOS shifts the threshold ( == your double clocking case, which can also include miss-clocking ) -jgArticle: 49098
On 30 Oct 2002 14:40:07 -0800, joefrese@hotmail.com (Joe Frese) wrote: >First off, thanks to all who responded to my last post, re: FPGA >fullness. Your comments and suggestions were incredibly helpful. > >We recently purchased Active-HDL 5.1XE, and in experimenting with it, >I discovered an FPGA design that does not simulate (post >place-and-route) correctly . . . which is strange, as the design has >been tested and verified as operating correctly in actual hardware. >Digging a little deeper, I was able to identify a number of constructs >in the design that cause problems in simulation, but should NOT cause >problems in real hardware. > >Now, I could fix these areas so that the design simulates correctly, >but the problem constructs are sprinkled heavily throughout, so to do >so would be no small undertaking. My question is, therefore: how >important is it to have a completely clean simulation? Is it >important enough to renovate a working and tested design? Thanks in >advance for your input. > >Joe Frese I've done some pretty hairy stuff (77 MHz OC-3 data, microengines, nasty state machines prowling multiport ram) without simulation, and without a lot of trouble bringing them up. Just a timing report tells us that the p&r looks OK. After all, simulation just tells you that you made a mistake, and ultimately it becomes obvious, so why not just inspect the design carefully before you compile it? JohnArticle: 49099
Hi all One of my friend, who study electrical eng at university, ask me what kind of technology is used to implement a 9500, meaning is it a BI-CMOS, ACT, TTL, etc... This is for a lab he as to do. I was not able to find this information on Xilinx web site. Cheers !
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