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kevinbraceusenet@hotmail.com (Kevin Brace) wrote in message news:<cc7b0b5f.0302231456.ce5e3f9@posting.google.com>... Kevin, Thanks for answer. > Goran, > > Which Xilinx part are you planning to target? Spartan IIe, smaler Virtex (mainly because multipliers).Below 300K gates. > As long as you are targeting Xilinx devices below 300K system gates or > you don't have to target a 2.5V Virtex device, you may want to try the > free ISE WebPACK first before paying for ISE BASE-X. > Unlike ISE BASE-X users, ISE WebPACK users won't have access to FPGA > Editor or CORE Generator, but if those tools aren't important to you, > you should be fine with ISE WebPACK. I would like to use CORE Generator. I think it's a nice thing and ISE baseX doesn't seem to expencive. I don't like paying every year, but... > Regarding ModelSim XE, you may want to try ModelSim XE-Starter > first before paying for ModelSim XE. > Yes, ModelSim XE-Starter has a 500 statements limit, but what that > really means is that the simulation speed will drop after that limit, > and the simulator will still continue to run past that limit. > In the past, I have simulated a design that exceeded the 500 > statements limitation by 40,000 lines, but ModelSim XE-Starter > completed the simulation fine. > However, it took quite a time to complete because I was doing a Post > P&R simulation of a design, and a Post P&R simulation is inherently > very slow compared to an RTL simulation. The problem is we have some older version of Aldecs ActiveVHDL, I think 3.2. I did lot of behavioral simulations on this one, and I like it. My question is can I import post place & route design from ISE and perform simulation in ActiveVHDL 3.2? I'm beginer in this, so really need help! > I also agree with Spam Hater that XST's synthesis quality is > good, so unless you don't mind paying $8,000 for a third party > synthesis tool, I will just use XST. Lot of people are saying XST is OK. Since I mind paying that much I'll go with XST. Regards, Goran > > > Kevin Brace (If someone wants to respond to what I wrote, I prefer if > you will do so within the newsgroup.) > > > > goran@net.yu (Goran) wrote in message news:<3c0f6336.0302221215.1ab0ed0d@posting.google.com>... > > Hi all, > > I work in small, development company, and we would like to start some > > more advanced FPGA designs (we are now using Xilinx FPGAs for simple > > glue logic only). My question is what tools we need to complete medium > > sized projects on Spartan IIe & smaller Virtex members. > > I learned (on Xilinx web site) that ISEbaseX would be OK? > > Does "one year license" that you buy from Xilinx mean your software > > stops working after one year, or you just don't have access to > > updates? > > If we purchase ModelSim XE does the same license apply? > > Can we use another VHDL simulator for post place & route simulation? > > We have, for example, Active VHDL, can we use it? > > How does XST behave, do we have to buy other synthezis tool to compile > > anything more advanced? > > Thanks in advance, > > Goran.Article: 52826
Hello sir, what is use of expansion ROM in case of PCI. Usually there will be external EPROM for loading the content of configuration part of PCI bridge. Does the expansion ROM have the same content. So instead of external EPROM, expansion ROM can be used..... Is it????? please reply soon waiting for reply praveenArticle: 52827
Hi, I am doing project using four Xilinx XCv600 FPGA. I need fe_shell.exe file. i am using Xilinx 5.1 foundation series software and there is no fe_shell.exe file in any of it's folder. Does any one know or have this file? Is there is any othee name of this file in version 5.1 as I have seen this file in version 3.1? Thanking you in advance M.K.KhanArticle: 52828
Hi Muhammad, fe_shell.exe is the program used to run the FPGA Express synthesis in a command line fashion. The FPGA Express tool from Synopsys used to be shipped with the Xilinx tools. As of the Xilinx 5.1i tools, Xilinx does not support the FPGA Express synthesis tool anymore and so you will not find this file in that release of software. --Stephan Muhammad Khan wrote: > Hi, I am doing project using four Xilinx XCv600 FPGA. I need > fe_shell.exe file. > i am using Xilinx 5.1 foundation series software and there is no > fe_shell.exe file in any of it's folder. > Does any one know or have this file? > Is there is any othee name of this file in version 5.1 as I have seen > this file in version 3.1? > Thanking you in advance > > M.K.KhanArticle: 52829
Hi there, I'm looking for my thesis for a virtex 2 pro prototype board with flash (like compact flash) on it, which is not so expensive. Also I'm looking for an operation system for the hardcore PPC 405 in the virtex 2 pro. Is there an open source projekt which have ported linux for the PPC for the virtex 2 pro? Thanks all, MartinArticle: 52830
Hello! I'm hacking a FSM together (spartan-II), and I'm trying to have an external clock and then a double-speed internal clock (multiplied via a DLL). I'd like the FSM to transition on the rising edge of the external (1x) clock, so I tried using the other clock to determine my next state, but this does two different things in behavioral and post-P&R! So, any suggestions how to have an FSM with a CLK and a 2x CLK? The only thing I could think of that would be guaranteed to work would be to use another DLL (!) to offset CLK by 90, so I can always be sure that I'm sampling what I expect to be sampling when switching states on the internal 2X clk. Is there a better way?Article: 52831
Hi all, I'am trying to program a serial data flash with a standard SPI interface through a XC9536 via the JTAG interface. Has this done before? markus -- Mit freundlichen Grüssen Markus Meng P.S. Achtung wir haben eine neue FAX-Nummer ******************************************************************** ** Meng Engineering Telefon 056 222 44 10 ** ** Markus Meng Natel 079 230 93 86 ** ** Bruggerstr. 21 Telefax 056 222 44 34 <-- NEU !! ** ** CH-5400 Baden Email meng.engineering@bluewin.ch ** ** Web www.meng-engineering.ch ** ******************************************************************** ** You cannot create experience. You must undergo it. Albert Camus** -----= Posted via Newsfeeds.Com, Uncensored Usenet News =----- http://www.newsfeeds.com - The #1 Newsgroup Service in the World! -----== Over 80,000 Newsgroups - 16 Different Servers! =-----Article: 52832
Basically you need to put the XC9536 in EXTEST mode and drive the pins that are connected to the flash SPI interface according to the timing and sequences required in the flash spec. HTH, Jim "Markus Meng" <meng.engineering@bluewin.ch> wrote in message news:3e5a1afd$1_4@corp.newsgroups.com... > Hi all, > > I'am trying to program a serial data flash with a standard SPI interface > through a XC9536 via the JTAG interface. Has this done before? > > markus > > -- > Mit freundlichen Grüssen > Markus MengArticle: 52833
Hi Naveen,
"Wait statement" is not filly supported by XST.
see the table "Table 6-8 Sequential Statements" in the below link
http://toolbox.xilinx.com/docsan/xilinx4/data/docs/xst/vhdl12.html
--Sasi
cvmnk@yahoo.com (naveen) wrote in message news:<b7f5eb6a.0302232046.282b06f9@posting.google.com>...
> hi,
> iam using "wait until boolean expression" inside while loop of vhdl
> code to implement a design on fpga virtex 2 fpga chip.
> iam gettin an error:-
>
> ERROR:Xst:825 - D:/changemachine/CONVERT.vhd line 30: Wait
> statement in a procedure is not accepted.
>
> wat shall i do for this problem
>
> thanx
> naveen
Article: 52834Hi! In order to connect several parts of design I use some form of internal bus with many sources and many sinks. Should I pay any attention to keep bus values defined all the time (i.e. occasions when bus is not driven by any device exists)? Regards, Joze DedicArticle: 52836
cvmnk@yahoo.com (naveen) wrote in message news:<b7f5eb6a.0302232046.282b06f9@posting.google.com>... > hi, > iam using "wait until boolean expression" inside while loop of vhdl > code to implement a design on fpga virtex 2 fpga chip. > iam gettin an error:- > > ERROR:Xst:825 - D:/changemachine/CONVERT.vhd line 30: Wait > statement in a procedure is not accepted. > > wat shall i do for this problem > > thanx > naveen hi, i know that "wait for" funcitonis not synthesisablw in a fpga board. but iamnot sure abt "wait until" if somebody could help me it will b great regards naveenArticle: 52837
hi,
iam using "wait until boolean expression" inside while loop of vhdl
code to implement a design on fpga virtex 2 fpga chip.
iam gettin an error:-
ERROR:Xst:825 - D:/changemachine/CONVERT.vhd line 30: Wait
statement in a procedure is not accepted.
I know that "wiat for" is not synthesisable on fpga, but iam not
sure abt wiat unitl.
wat shall i do for this problem
thanx
naveen
Article: 52838
"naveen" <cvmnk@yahoo.com> wrote
> i know that "wait for" funcitonis not synthesisablw in a fpga board.
> but iamnot sure abt "wait until"
> if somebody could help me it will b great
"wait until" is synthesisable only in one special case:
wait until clock = '1'; -- or '0'
This waits for an active clock edge in a clocked process.
It is an ugly coding style and it's much better to use the
style illustrated below in my state machine example.
To wait for anything else to happen, use a state machine:
type state_type is (idle, active, recovery);
signal state: state_type;
process (clock, reset)
begin
if reset = '1' then
state <= idle;
elsif rising_edge(clock) then
case state is
when idle =>
if test_condition then
state <= active;
end if;
when active =>
state <= recovery;
when recovery =>
if not test_condition then
state <= idle;
end if;
end case;
end if;
end process;
The state machine is in the "active" state for exactly one
clock cycle, just after the test condition becomes true.
You can use that fact to make something else happen.
test_condition is whatever you are waiting for. If it
is derived from asynchronous inputs, you need to register
those inputs first.
Read any good text on logic design for more details.
--
Jonathan Bromley, Consultant
DOULOS - Developing Design Know-how
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Doulos Ltd. Church Hatch, 22 Market Place, Ringwood, Hampshire, BH24 1AW, UK
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Article: 52839jsmith wrote: > I see some new spartan family on my latest Synplicity tools. I hear > that its on 90nm IBM. Why would anyone try and build a low cost FPGA > family on an aggressive new process technology? They can't make 0.13um > VII pro, what hope do they have in building 90nm any time soon. Just found this link: http://toolbox.xilinx.com/docsan/xilinx5/data/docs/irn/irn0040_8.html waiting to get the the 5.2i CD. PatrickArticle: 52840
On 24 Feb 2003 08:46:45 -0800, cvmnk@yahoo.com (naveen) wrote: >hi, > iam using "wait until boolean expression" inside while loop of vhdl >code to implement a design on fpga virtex 2 fpga chip. > iam gettin an error:- > > ERROR:Xst:825 - D:/changemachine/CONVERT.vhd line 30: Wait >statement in a procedure is not accepted. > > I know that "wiat for" is not synthesisable on fpga, but iam not >sure abt wiat unitl. > > wat shall i do for this problem > > thanx > naveen If you're waiting for a condition to change you can just stay in the same state till it changes. You don't have to use wait. Basically stay in the same state while your condition is false and go to a different state when it becomes true. This way wait until is implicit in the state machine. Muzaffer Kal http://www.dspia.com ASIC/FPGA design/verification consulting specializing in DSP algorithm implementationsArticle: 52841
Matt wrote: >>And as a little comparison, I recently ran a simulation of a couple >>thousand line program on similar machines. A simulation that under >>Modelsim SE/Linux took 20 seconds, required 30 minutes under Modelsim >>XE-Starter/Windows 2000! Yikes! >> >>... oops, are we not supposed to post benchmarks ;) > > > ModelSim SE (Linux) vs. ModelSim XE-Starter (Win2K)... huh? And what > Scientific method are claiming to use? I don't believe I made any such claim. I merely found a 90 to 1 difference to be rather astonishing. -- My real email is akamail.com@dclark (or something like that).Article: 52842
Hi Jim, do you need a special tool to add the sequences for SPI clocking, or is there a backdoor through which you can use Xilinx IMPACT JTAG Tool to do the stuff ... markus "Jim Wu" <jimwu88NOOOSPAM@yahoo.com> schrieb im Newsbeitrag news:nFq6a.4972$8f7.1367@nwrdny02.gnilink.net... > Basically you need to put the XC9536 in EXTEST mode and drive the pins that > are connected to the flash SPI interface according to the timing and > sequences required in the flash spec. > > HTH, > Jim > > "Markus Meng" <meng.engineering@bluewin.ch> wrote in message > news:3e5a1afd$1_4@corp.newsgroups.com... > > Hi all, > > > > I'am trying to program a serial data flash with a standard SPI interface > > through a XC9536 via the JTAG interface. Has this done before? > > > > markus > > > > -- > > Mit freundlichen Grüssen > > Markus Meng > > -----= Posted via Newsfeeds.Com, Uncensored Usenet News =----- http://www.newsfeeds.com - The #1 Newsgroup Service in the World! -----== Over 80,000 Newsgroups - 16 Different Servers! =-----Article: 52843
Steve T Shannon wrote:
> The only thing I could think of that would be guaranteed to work would
> be to use another DLL (!) to offset CLK by 90, so I can always be sure
> that I'm sampling what I expect to be sampling when switching states
> on the internal 2X clk. Is there a better way?
Yes. Run everthing on the 2x clock.
You can arrange output changes every other clock.
-- Mike Treseler
Article: 52844Hi, I'm considering the design of a PCI card that will use a fairly big (400 I/Os, maybe) Xilinx FPGA and a bunch of SRAM to hold images (2D histograms, actually). There would be a bunch of control registers in the FPGA, and PCI block transfers to/from the dual-ported image RAM. The thing is, I'd like to have the PC application code be able to configure the FPGA for various applications. So the FPGA would likely not be the actual PCI interface, and would power up un-configured. So, any suggestions on an architecture? Some possibilities I've thought of are... A standard PCI chip, like the AMCC or PLX parts, do the real PCI interface, with some sort of path (maybe a little glue logic) for initializing and configuring the FPGA. A second, fix-configured FPGA or CPLD to front-end the big one, ditto. Partial reconfiguration somehow? Like initial config from a EEPOM, with self-managed reconfig afterwards? Sounds nasty. Ideas welcome. And if anybody has this all worked out already, we'd consider buying the IP. JohnArticle: 52845
"Clyde R. Shappee" <cshappee@ieee.org> wrote in message news:<3E59435E.FA7EDB6F@ieee.org>... > Steve, > > I did an interface to the PLX9030 and it was straightforward. The hardest > part was getting the config prom correct, a task which I did not do. > > They have a utility to help, but I have never tried it. > > If you are in a time crunch, this is the way to go. Clyde, I did a 9030 design and it was a piece of cake. Getting the config PROM right was a bit tricky, since if you get it wrong, you may get stuck in a state where you can't re-program it! The trick was to lift the data-out pin on the PROM from its pad so the thing would realize there's no config PROM and it'll start up in its "default" state. Then you can tie the data-out pin back to the pad and re-program the PROM. Yowza. BTW: I wish PLX would come out with a 66 MHz target-only device. The 9030 won't work in this case because it is a target only device. The ethernet chip probably needs a master to configure it at boot time. A 9052 or 9080 or something like that will work. Of course, you'll need some logic, or a processor, on the local side of that chip to do what needs to be done. --aArticle: 52846
Sorry if this is the incorrect group As a project I've got a motherboard with an LVDS connector, which I understand can be used to control an LCD screen. Can I simply purchase an LCD screen (small <10") and connect it to this socket and it work? Drivers? Alternatively can someone point me to introductory material on how to connect LCDs and which also explains the necessary components such as the different controller boards. So far I have been bewildered by the lack of introductory material and the impenetrable information from which I cannot glean the basic knowledge of the roles of controller boards, when they are needed, to what extent they are interchangable/compatible and whether I would have to write a driver for it myself. Any help appreciatedArticle: 52847
"Kevin Neilson" <kevin_neilson@removethistextattbi.com> wrote in message news:<iiy5a.193221$tq4.3488@sccrnsc01>... > > module(input [7:0] a); > > But how do I use a parameter with this style of declaration to make the > width of 'a' parameterizable? I don't think I can insert a parameter before > the module declaration. For this reason, the ANSI-C style declarations allow a list of parameters to appear inside #() before the port list. This syntax is supposed to be reminiscent of the syntax used in instantiations when overriding parameters. Here is an example of the declaration syntax: module foo #(parameter WIDTH = 8) (input [WIDTH-1:0] a); And the instantiation syntax would be: foo #(16) f1(data); Or with connection by name (including Verilog-2001 parameter override by name), the syntax would be: foo #(.WIDTH(16)) f2(.a(data)); Or if you don't want to override the parameter, you can leave the "connection" of the parameter off, just as in the past. foo f3(.a(data[7:0)); Note that the syntax of the declaration doesn't quite match the instantiation, since the parameter list appears after the module name in the declaration, but before the instance name in the instantiation. You can still declare more parameters inside the module, and override them. This is allowed for backward compatibility with Verilog-1995. The only time you really need to put them in the #() before the port list is if you want to use them in the port list. However, it may be reasonable to list the parameters you expect to get overridden in the ANSI-C style header anyway, since they are effectively part of the module interface.Article: 52848
I am new to FPGA's and its programming language VHDL. I am working on an electrical engineering senior project and have a few questions. 1.) is it possible to connect a USB device (ie a digital camera) to the Spartan 2e FPGA? 2.) If it is possible, could someone give a quick overview or a good resource for me to research. 3.) If not, any good suggestions on how i would go about accomplishing my objective(see below) My main goal is to connect a Digital camera directly to the FPGA board to get a picture from the camera. Once the picture is loaded into the FPGA memory i am going to compress that image and then send it to a computer. Thanks in advance!! ScottArticle: 52849
What do you mean by "high"? I believe the industrial specs for most components is maximum around +70 deg. C. Are you trying to find a limit for FPGA technology? I believe (at least the Altera Cyclone family is) some FPGA's are solved using SRAM technology, so there must be something to find there. However, if I were running an oil plant, I would never exceed temperature ratings anyway. "makmorbi" <m_kochar@yahoo.com> skrev i melding news:1993b25f.0302191841.4a5d01ee@posting.google.com... > Hi All, > > I am about to write a paper on effects on FPGA's at high temperatures. > One application maybe an oil well where the temperatures are very > high. Can somebody point me to some references or have any thoughts on > that. Would apprectiate it. > > Thanks
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Compare FPGA features and resources
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