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Hello, assembling an EDK 3.2.2 design I encountered some difficulties: 1. The peripheral reset signals of the Processor System Reset Module are not assigned properly. I declared a peripheral reset port of width 3 in the MPD file: C_NUM_PERP_RST = 3 and assigned the modules reset signals to the port in the MHS file PORT Peripheral_Reset = module1_reset & module2_reset & module3_reset The auto-generated system.vhd file contains the lines: peripheral_reset_vec(0 TO 0) <= module1_reset; peripheral_reset_vec(1 TO 1) <= module2_reset; peripheral_reset_vec(2 TO 2) <= module3_reset; other then the expected module1_reset <= peripheral_reset_vec(0); ... 2. Inferring some interrupt handlers causes the LibGen process to stop with the error message: ERROR:MDT - system.mss:90 - Property interrupt_handler is not found (Frank posted the same problem recently, have you solved it?) Many Thanks for any kind of advice ChristianArticle: 64026
Hi all, It's the first time that I am using ChipScope Pro to analyze my design. My design is based in MicroBlaze so I want to analyze the OPB Bus. I have created a ICON core with a single Control Port and another IBA/OPB core with 1 master and 5 slaves. I have instantiated it through ISE and compiled the design. Then I execute the ChipScope Analyzer and the problem comes here: it generates a warning telling that he can't find any cores in any of devices in the JTAG chain. Any help would be welcome. Thanks in advance, Arkaitz.Article: 64027
"Christian Haase" <nospams@today.de> wrote in message news:3fd9cddf$1@news.fhg.de... > Hello, > > assembling an EDK 3.2.2 design I encountered some difficulties: > > 1. The peripheral reset signals of the Processor System Reset Module > are not assigned properly. I declared a peripheral reset port of width 3 > in the MPD file: > C_NUM_PERP_RST = 3 > and assigned the modules reset signals to the port in the MHS file > PORT Peripheral_Reset = module1_reset & module2_reset & module3_reset > > The auto-generated system.vhd file contains the lines: > peripheral_reset_vec(0 TO 0) <= module1_reset; > peripheral_reset_vec(1 TO 1) <= module2_reset; > peripheral_reset_vec(2 TO 2) <= module3_reset; > > other then the expected > module1_reset <= peripheral_reset_vec(0); > ... > > > 2. Inferring some interrupt handlers causes the LibGen process to stop > with the error message: > ERROR:MDT - system.mss:90 - Property interrupt_handler is not found > > (Frank posted the same problem recently, have you solved it?) > > > Many Thanks for any kind of advice > Christian > Hi Christian, yes I solved it. What you have to do is making a dummy driver. At this moment, I guess, your opb device is using a generic driver. In the mss file you have the following line for your opb device: PARAMETER DRIVER_NAME = generic The generic driver doesn't have a "INT_HANDLER" parameter. So you can't use this parameter in your mss file. To use the "INT_HANDLER" parameter (in order to assign your interrupt handler) you have to make a dummy driver. This driver only exists of a mdd and tcl file. You can see examples of them in your install directory of the EDK. FrankArticle: 64028
Hi,
I've a small program in bram which has a pointer to sdram.
static volatile BYTE * const p_sdram = (BYTE *) XPAR_SDRAM_CTRL_BASEADDR;
in my code I try to fill the sdram (by the way, it's 32-bits wide databus):
for (i = 0; i < 16; i++) {
*(p_sdram+i) = i;
}
Now comes the problem: when I read back the data, each 2 bytes are
exchanged. Reading back is done with the same byte pointer:
for (i = 1; i <= 16; i++) {
xil_printf("%02X ", (BYTE) *(p_sdram+i-1));
}
The output is:
01 00 03 02 05 04 07 06 09 08 0B 0A 0D 0C 0F 0E
What is wrong?! If I have a byte pointer, the big or little endian story
doesn't matter, does it? I'm posting this here, because I have the feeling
that it has to do with the opb sdram controller? Can somebody explain the
above?
Frank
Article: 64029
The MAX106/104 family is a famous Flash ADC from Maxim,
that has PECL outputs based on 3.0 to 5.0V V_CCO. The data
sheet for the Xilinx Virtex-II Pro (V2P) claims inputs that
are PECL compatible, but only for V_CCO 2.5 V. So on paper,
there is a half-volt gap, and one would need some level
shifting hardware between them -- maybe just a few resistors?
Speeds are pretty high, 250 to 500 MS/s per digital signal
differential pair, which the V2P should handle OK in DDR mode
with a 125 to 250 MHz clock.
Has anybody tried this match-up, either directly (by slightly
abusing one or both of the parts) or with additional level
shifting hardware?
- Larry
Article: 64030> It was easy to identify a culprit: almost all the conditional assignments > are incompletely specified. ... > Anyway, I'm having problems describing to the design team why their coding > style is incomplete, especially because they claim that it works perfectly > in a back-annotated simulation. If your design team doesn't understand this I would be afraid, very afraid to place a design of any significance in their hands. -- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ Martin Euredjian To send private email: 0_0_0_0_@pacbell.net where "0_0_0_0_" = "martineu"Article: 64031
Did you verify it's not going wrong at step 4? The CEO of the first PROM toggles at the end of the PROM, not the end of the first configuration file. Make sure you create the PROM file as a daisy chain in the PROM File Formatter, not as two independent files. Also note that the Spartan-IIE (as with all Virtex derivatives) does not send header data to the downstream devices the way the Spartan/XL did (and all XC4000 derivatives). "Jerker Hammarberg (DST)" wrote: > Hello! I'm trying to configure two Spartan IIE (XC2S300E) in a daisy chain > using two PROMs (XC18V02) but I cannot seem to make any configuration data > reach the second (slave) FPGA. As a result, the DONE pin will be held low by > the second FPGA and the system will never start. > > That was the short version, here is the long one: The four components, two > XC18V02 and two XC2S300E, are connected exactly according to figure 5 in the > XC18V00 data sheet, that is: > * /CF of both PROMs are connected to /PROGRAM of both FPGAs > * DONE of both FPGAs are connected to /CE of first PROM > * /CEO of first PROM is connected to /CE of second PROM > * INIT of both FPGAs are connected to /RESET of both PROMs > * D0 of both PROMs are connected to DIN of master FPGA > * DOUT of master FPGA is connected to DIN of slave FPGA > * CCLK of master FPGA is connected to CLK of both PROMs and to CCLK of slave > FPGA. > > So at power up, I expect the following: > > 1. Both FPGAs pull DONE low, enabling first PROM. > 2. Both FPGAs release /INIT when initialization is done, the wire is pulled > up and /RESET on both PROMs go high. > 3. First PROM sends data from D0 to DIN of master FPGA, clocked by CCLK of > master FPGA. > 4. When done, /CEO of first PROM goes low, enabling second PROM. At the same > time, master FPGA releases the DONE pin; however, slave FPGA keeps it down > since it is not yet configured. > 5. Second PROM sends data from D0 to DIN of master FPGA, which should > forward the data from its DOUT into DIN of slave FPGA. > 6. When done, slave FPGA should release DONE, the wire should be pulled up > and both FPGAs should go into normal function. > > Things go wrong at step 5. The problem is that master FPGA never forwards > any data. In fact, DOUT is high constantly as soon as power is on. Having > read some earlier posts, I think that DOUT should not only copy all bits > dedicated for slave FPGA at step 5, but it should also present the first 32 > or 40 synchronization bits when master FPGA itself is being configured at > step 3. This doesn't happen either. Anyone has any ideas about what is > wrong? Does the above description make sense, or have I misunderstood > anything? > > Here are some more clues: > * We use Xilinx iMPACT for configuration. DONE and /INIT are both pulled up > by 3.3kOhm resistors, but we have also tried 4.7kOhm. > * We have two boards to experiment with and the same thing happens with both > boards, so it's unlikely that there's something wrong with the FPGAs. > * When disconnecting the DONE pin of slave FPGA, the DONE wire goes high > after configuration of master FPGA, which works fine afterwards. > * The MODE pins are actively held 000 on master and 111 on slave. > > Thanks in advance! > > /Jerker -- Marc Baker Xilinx Applications (408) 879-5375Article: 64032
The M2 does "change its polarity" for pullup control in Master Serial mode. The Mode pin settings were selected to maintain consistency with earlier families, where for example "000" would select Master Serial and "111" would select Slave Serial. The Mode pins should be considered as a group, and not as individual functions, to avoid confusion. The Spartan-II data sheet does mention on p2 that there are no pull-ups on the global clock pins, as you confirmed in the FPGA Editor. lecroy wrote: > Looking at the mode selection M2 on the SII devices in Xilinx document > DS-001_2, table 8, I wonder if the M2 for master mode is correct? It > seems to match the rest of the data sheet, but I would have thought > the the pullups would always follow the M2 pin and this is the only > mode where it does not. > > On the SII, there is no mention of allowing for a weak pullup on the > global clock lines. Interesting enough that using the 6.x tools and > placing the following in the constraints: > > NET "p_pclock" LOC = "P88" | IOSTANDARD = LVTTL | PULLUP ; > > I get the following message from project manager during place and > route: > > Annotating constraints to design from file "main.ucf" ... > Attached a PULLUP primitive to pad net p_pclock > > If I look at the FPGA editor at pin 88 after place and route, there is > no dialog box to allow for pullups, etc, like there are with a > standard I/O. So, I would have to guess that in the actual device > there was no pullup added. Can someone at Xilinx confirm this? > > Thanks -- Marc Baker Xilinx Applications (408) 879-5375Article: 64033
I have this piece of code. I have just used char instead of BYTE. I get
the proper output. I do not see the interleaving that you specify.
If you can give more info about the design you are seeing this problem
with, we can take a look.
=====
int main()
{
static volatile char * const p_sdram = (char *) 0xe000000;
int i;
for (i = 0; i < 16; i++) {
*(p_sdram+i) = i;
}
for (i = 1; i <= 16; i++) {
xil_printf("%02X ", (char) *(p_sdram+i-1));
}
while (1);
}
======
Frank wrote:
>Hi,
>
>I've a small program in bram which has a pointer to sdram.
>
>static volatile BYTE * const p_sdram = (BYTE *) XPAR_SDRAM_CTRL_BASEADDR;
>
>in my code I try to fill the sdram (by the way, it's 32-bits wide databus):
>
>for (i = 0; i < 16; i++) {
> *(p_sdram+i) = i;
>}
>
>Now comes the problem: when I read back the data, each 2 bytes are
>exchanged. Reading back is done with the same byte pointer:
>
>for (i = 1; i <= 16; i++) {
> xil_printf("%02X ", (BYTE) *(p_sdram+i-1));
>}
>
>The output is:
>
>01 00 03 02 05 04 07 06 09 08 0B 0A 0D 0C 0F 0E
>
>What is wrong?! If I have a byte pointer, the big or little endian story
>doesn't matter, does it? I'm posting this here, because I have the feeling
>that it has to do with the opb sdram controller? Can somebody explain the
>above?
>
>Frank
>
>
>
>
Article: 64034I'm trying to do some division in a Microblaze soft core. The question I have: Can you typecast a float to an integer (x = (int)jet) so the GPIO write statement can send data out to external hardware? I check the Microblaze and Embedded refernces guides. On Page 218 of the Embedded Refernce guide, the guide states Microblaze can do floating point math. If it can do the math, how do you get the data ffrom the controller to external devices? Thanks, MattArticle: 64035
I need to make some filters now for some project in FPGA. I was wondering if some free (open source?) software exists that outputs verilog (or a xilinx module for example) with as input say -3dB point, slope, poles, low / high pass etc.? These programs do exist for analog filters, some from IC manufacturers. Is such a thing feasable (to do in verilog) does it exist? JanArticle: 64036
Hi all! Can someone tell me the advantages and disadvantages of an ethernet MAC core implemented in a FPGA for a System On Chip? Why to buy a lincese for several thousand dollar for an ethernet MAC core and there is also an external PHY chip on the board? There are also external chips which combine the MAC and the PHY layer. Thanks MartinArticle: 64037
Hello Frank, You are exactly right - the OPB SDRAM controller will convert the 32-bit access on the OPB bus to two 16-bit accesses to the SDRAM. (it actually looks like a SDRAM burst of 2). Thanks! anita Frank wrote: > Is it possible to use the opb sdram controller with a 32-bits opb bus to a > microblaze one side and a 16-bits sdram to the other side? What if I do a > 32-bits access to sdram. Will the controller convert this automatically in > two 16-bits cycles? The datasheet of the opb sdram controller says: "Since > the sdram will always be accessed to provide data the width of the OPB bus, > ...". So it looks like it will convert a 32-bits access to two 16-bits > accesses, but can anyone acknowledge this? > > FrankArticle: 64038
Frank,
I've also used char in my code when testing the OPB SDRAM controller and not
seen a problem.
There is a bit-ordering difference that is really only important in the address
bus simply because when setting the SDRAM mode register, the address bus
contains the data for that register.
So I reccommend checking the bit-ordering connections. There are some examples
in the design spec.
Thanks!
anita
Vasanth Asokan wrote:
> I have this piece of code. I have just used char instead of BYTE. I get
> the proper output. I do not see the interleaving that you specify.
> If you can give more info about the design you are seeing this problem
> with, we can take a look.
>
> =====
> int main()
> {
> static volatile char * const p_sdram = (char *) 0xe000000;
> int i;
>
> for (i = 0; i < 16; i++) {
> *(p_sdram+i) = i;
> }
>
> for (i = 1; i <= 16; i++) {
> xil_printf("%02X ", (char) *(p_sdram+i-1));
> }
>
> while (1);
> }
> ======
>
> Frank wrote:
>
> >Hi,
> >
> >I've a small program in bram which has a pointer to sdram.
> >
> >static volatile BYTE * const p_sdram = (BYTE *) XPAR_SDRAM_CTRL_BASEADDR;
> >
> >in my code I try to fill the sdram (by the way, it's 32-bits wide databus):
> >
> >for (i = 0; i < 16; i++) {
> > *(p_sdram+i) = i;
> >}
> >
> >Now comes the problem: when I read back the data, each 2 bytes are
> >exchanged. Reading back is done with the same byte pointer:
> >
> >for (i = 1; i <= 16; i++) {
> > xil_printf("%02X ", (BYTE) *(p_sdram+i-1));
> >}
> >
> >The output is:
> >
> >01 00 03 02 05 04 07 06 09 08 0B 0A 0D 0C 0F 0E
> >
> >What is wrong?! If I have a byte pointer, the big or little endian story
> >doesn't matter, does it? I'm posting this here, because I have the feeling
> >that it has to do with the opb sdram controller? Can somebody explain the
> >above?
> >
> >Frank
> >
> >
> >
> >
Article: 64039Christian Haase wrote: > Hello, > > assembling an EDK 3.2.2 design I encountered some difficulties: > > 1. The peripheral reset signals of the Processor System Reset Module > are not assigned properly. I declared a peripheral reset port of width 3 > in the MPD file: > C_NUM_PERP_RST = 3 > and assigned the modules reset signals to the port in the MHS file > PORT Peripheral_Reset = module1_reset & module2_reset & module3_reset > > The auto-generated system.vhd file contains the lines: > peripheral_reset_vec(0 TO 0) <= module1_reset; > peripheral_reset_vec(1 TO 1) <= module2_reset; > peripheral_reset_vec(2 TO 2) <= module3_reset; > > other then the expected > module1_reset <= peripheral_reset_vec(0); > ... This is a bug and it's fixed in EDK.6.2. To work-around your issue you can insert IP pcore. That takes the bus as input and splits it into individual bits as outputs.Article: 64040
Hi Jan, Our company Tyder has a product ONEoverT and it outputs VHDL which you can use to design filters on FPGAs....FIRs (Windowed & Optimal) loads of other FIR types, and also different types of IIR filters. It is not free but it is on sale at a very low price. There are some case studies on the website which you can download. You can also download the demo version. See website www.tyder.com Regards Michael Gallen "Jan Panteltje" <pNaonStpealmtje@yahoo.com> wrote in message news:1071261764.857468@evisp-news-01.ops.asmr-01.energis-idc.net... > I need to make some filters now for some project in FPGA. > I was wondering if some free (open source?) software > exists that outputs verilog (or a xilinx module for example) > with as input say -3dB point, slope, poles, low / high pass etc.? > These programs do exist for analog filters, some from IC > manufacturers. > Is such a thing feasable (to do in verilog) does it exist? > JanArticle: 64041
Martin wrote:
> Hi all!
>
> Can someone tell me the advantages and disadvantages of an ethernet
> MAC core implemented in a FPGA for a System On Chip?
>
> Why to buy a lincese for several thousand dollar for an ethernet MAC
> core and there is also an external PHY chip on the board?
>
> There are also external chips which combine the MAC and the PHY layer.
It's all about trade-offs, isn't it? Do you want to one large lump sum,
or a little at a time over a long period? Do you have board space?
Spare I/O? Voltage rails available? Do you need the PHY layer, or are
you paying for something you won't put to good use?
Have fun,
Marc
Article: 64042Just use a filter design tool to generate the coefficients. The HDL is pretty simple. ScopeFIR is one example. Of course, you can also do a lot of this work using tools like Excel from fundamental DSP/Filter theory/math. Excel has a SUMOFPRODUCTS() function that come in handy for some of this work (like implementing a DFT to generate filter frequency response and graph it). ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ Martin Euredjian To send private email: 0_0_0_0_@pacbell.net where "0_0_0_0_" = "martineu" "Jan Panteltje" <pNaonStpealmtje@yahoo.com> wrote in message news:1071261764.857468@evisp-news-01.ops.asmr-01.energis-idc.net... > I need to make some filters now for some project in FPGA. > I was wondering if some free (open source?) software > exists that outputs verilog (or a xilinx module for example) > with as input say -3dB point, slope, poles, low / high pass etc.? > These programs do exist for analog filters, some from IC > manufacturers. > Is such a thing feasable (to do in verilog) does it exist? > JanArticle: 64043
On a sunny day (Sat, 13 Dec 2003 07:37:46 GMT) it happened "Martin Euredjian" <0_0_0_0_@pacbell.net> wrote in <elzCb.70799$Ns6.25727@newssvr25.news.prodigy.com>: >Just use a filter design tool to generate the coefficients. The HDL is >pretty simple. ScopeFIR is one example. > >Of course, you can also do a lot of this work using tools like Excel from >fundamental DSP/Filter theory/math. Excel has a SUMOFPRODUCTS() function >that come in handy for some of this work (like implementing a DFT to >generate filter frequency response and graph it). > > >~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ >Martin Euredjian Hi, I downloaded ScopeFIR, and guess what, it runs fine on wine too, in Linux. So thank you. Then I played a bit with it, now I may perhaps input those coefficients to the FIR I found on opencores. But playing with ScopeFIR I got that 'deja-vue' feeling.... Some time ago I did some FIR in C for a horizontal re-scaler (see paper at http://www.home.zonnet.nl/panteltje/subtitles/lowpass.html ). Think I did not use that FIR in the end, that project was abandoned when I started using DVD. But in that time I did a whole lot of reading up on digital signal processing and IIR FIR etc.. Now then I used a program in Linux called 'remez' to calculate coefficients. I think ScopeFIR is either from the same author or a blunt copy (windows port) of remez, I dunno. But even the examples and the frequency choice is the same...... So I looked up remez on my machine (google for /root/compile/filters/remez/REMEZ16.EXE if you use windows), I do not remember where I found remez, google remez or remez.c remez uses gnu-plot..... hehe Since ScopeFIR asks 100$ after 60 days, I will be using remez likely after that time. JanArticle: 64044
Martin wrote:
> Why to buy a lincese for several thousand dollar for an ethernet MAC
> core and there is also an external PHY chip on the board?
If you want to do ethernet you
need both a MAC and PHY.
The MAC is a CPU to PHY interface.
Some CPUs have it built in and a few
PHYs have it built in. Unlike the PHY,
a MAC is purely digital and can be
designed into an FPGA.
If you are making thousands of
boards, or have space constraints,
a MAC core might make sense.
If you are just making a few hundred,
stick to commercial parts.
-- Mike Treseler
Article: 64045>Making your own PCB for these purposes is not a job to be undertaken >lightly, particularly as you usually need at least 4 layers ! Just for reference... It may not be too expensive to have a 4 layer board made commercially. I've used PCB Express - www.pcbexpress.com. There are several similar sites. 4 boards, 20 sq inches, 4 layers, no silk screen or solder mask is $183. $274 gets top side screen/mask. $45 more for bottom. They are non-fancy design rules: 7/7. That's probably good enough for hobby type projects. You do need access to board design tools and how to use them. Then you still have the problem that started this thread. -- The suespammers.org mail server is located in California. So are all my other mailboxes. Please do not send unsolicited bulk e-mail or unsolicited commercial e-mail to my suespammers.org address or any of my other addresses. These are my opinions, not necessarily my employer's. I hate spam.Article: 64046
Actually, if you accept a few restrictions, you can do it all in the FPGA with very little outside electronics. I've got good success with 10BASE-T http://www.fpga4fun.com/10BASE-T.html Jean "Mike Treseler" <mike_treseler@comcast.net> wrote in message news:45SdnSfgV7V3_kaiRVn-tw@comcast.com... > Martin wrote: > > > Why to buy a lincese for several thousand dollar for an ethernet MAC > > core and there is also an external PHY chip on the board? > > If you want to do ethernet you > need both a MAC and PHY. > > The MAC is a CPU to PHY interface. > Some CPUs have it built in and a few > PHYs have it built in. Unlike the PHY, > a MAC is purely digital and can be > designed into an FPGA. > > If you are making thousands of > boards, or have space constraints, > a MAC core might make sense. > If you are just making a few hundred, > stick to commercial parts. > > -- Mike Treseler >Article: 64047
Hi! I've bought a lot of XC2018 (yes I know, antic pieces), but they were very-veyr cheap, I've had no heart not to get them :) I'm looking for its complete datasheet, but I wasn't able to find it anywhere on the net... Has somebody got some point where to get it from, or maybe has a pdf ?... Many thanx Sandor JagerArticle: 64048
(snip question about ethernet in FPGA) Jean Nicolle wrote: > Actually, if you accept a few restrictions, you can do it all in the FPGA > with very little outside electronics. > I've got good success with 10BASE-T > http://www.fpga4fun.com/10BASE-T.html Do you need a PLL to do it? I thought it would, but maybe not. For 100baseTX you need three voltage levels. Maybe two outputs and appropriate resistors would work. Detecting three voltages on input will be hard, though. You still need the transformer, which usually doesn't come in an FPGA. -- glenArticle: 64049
Hi! i'm new to processor based FPGAs and in need of detils about it . What work is goin on these FPGAs .. Could anybody help me in it. I wanna know the link where from i can buy the whole development system for VertexII (XILINX) and for how much ..
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