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Rahul Khanna wrote: > Xilinx seems to have launched a new architecture - ASMBL. There is no > information except a news article. Can we have more info??? Is anyone > from Xilinx Listening???? There was an earlier thread on this. I did find the PDF on the Xilinx web site that was a little clearer, as it had (virtual?) die photos. ( Web info has gone Engineering -> Marketing -> web Publishing, whilst the PDF has only had Engineering -> Marketing 'content removal':) Info so far shows some good mechanical ideas for lowering the cost of creating new die mixtures. The Real Test will be the Volumes/NRE cost numbers, but they are flag waving mainly at the ASIC customers, and remember Xilinx do not have a HardCopy flow like Altera. One aspect of the Xilinx approach, is it allows Hard IP, AND keeps _some_ FPGA fabric - again, nice if you are big enough to 'get the stripes you want spun' :) -jgArticle: 64126
On Wed, 17 Dec 2003 17:52:18 +0000, Gus Baldauf wrote: > B. Joshua Rosen wrote: > >> Should work fine, I'm using Mandrake 9.2. > > I get the following error when I run the GUI setup. > > [root@quark cdrom]# ./setup > Wind/U Error (294): Unable to install Wind/U ini file (/mnt/cdrom/data/WindU). > See the Wind/U manual for more details on the ".WindU" file and the "WINDU" > environment variable. > Wind/U X-toolkit Error: wuDisplay: Can't open display > > > ************ setup done! *************** > > -Gus Try running as root when you do the install.Article: 64127
Somebody from Xilinx is always listening :-) The purpose of that press release was to create interest, exitement, and suspense. Obviously, it did succeed. I know lots of technical details, but I cannot tell. For good reasons, Marketing is in charge of releasing information. Please be patient, "you will be richly rewarded"! It is still an FPGA, to be configured by the customer. We are not entering the ASIC business... ( We just want to capture more of its $$$s ) Peter Alfke Rahul Khanna wrote: > Xilinx seems to have launched a new architecture - ASMBL. There is no > information except a news article. Can we have more info??? Is anyone > from Xilinx Listening????Article: 64128
B. Joshua Rosen wrote: > Try running as root when you do the install. I was running as root. The first time logged in as me then did a su to root in a command window. The second time, I logged out, and re-logged in as root. Same problem though. -GusArticle: 64129
B. Joshua Rosen wrote: > Should work fine, I'm using Mandrake 9.2. Couldn't get the setup program to run under Fedora 1. But it is running under Redhat Enterprise WS 3. -GusArticle: 64130
Hi folks,
I'm getting tired of commenting large blocks of VHDL code by hand.
Anyone know of any Vim scripts that can comment/un-comment a VHDL
block?
A cursory Google search brings up either nothing or way too much stuff
to sift through depending on my search terms ("vhdl vim comment").
-- Pete
Article: 64131Gus Baldauf wrote: > B. Joshua Rosen wrote: > >> Should work fine, I'm using Mandrake 9.2. > > > I get the following error when I run the GUI setup. > > [root@quark cdrom]# ./setup > Wind/U Error (294): Unable to install Wind/U ini file > (/mnt/cdrom/data/WindU). > See the Wind/U manual for more details on the ".WindU" file and the "WINDU" > environment variable. > Wind/U X-toolkit Error: wuDisplay: Can't open display You haven't set the $DISPLAY environment variable to point to a valid X server. something like "export DISPLAY=myxserver:0.0" where myxserver is the name of the computer that is running the X display. JohnArticle: 64132
"Amontec Team, Laurent Gauch" <laurent.gauch@amontecDELETEALLCAPS.com> wrote in message news:<3fe06c60$1@news.vsnet.ch>... > Hi all, > > Is that possible to invert a signal in the Xilinx .ucf file (thinking an > input or output signal on a PAD)? > if yes, which syntax? > > Thanks in advance, > > Laurent Gauch > www.amontec.com > > ------------ And now a word from our sponsor --------------------- > For a secure high performance FTP using SSL/TLS encryption > upgrade to SurgeFTP > ---- See http://netwinsite.com/sponsor/sponsor_surgeftp.htm ---- It is not possible with the .ucf You have to manually Edit the Floor Planner. But i am not sure, is there any way to do this editing with scripts .. (command line) -MuthuArticle: 64133
"Amontec Team, Laurent Gauch" <laurent.gauch@amontecDELETEALLCAPS.com> wrote in message news:<3fe06c60$1@news.vsnet.ch>... > Hi all, > > Is that possible to invert a signal in the Xilinx .ucf file (thinking an > input or output signal on a PAD)? > if yes, which syntax? No AnttiArticle: 64134
On 17 Dec 2003 20:16:14 -0800, petersommerfeld@hotmail.com (Peter
Sommerfeld) wrote:
>Hi folks,
>
>I'm getting tired of commenting large blocks of VHDL code by hand.
>
>Anyone know of any Vim scripts that can comment/un-comment a VHDL
>block?
>
>A cursory Google search brings up either nothing or way too much stuff
>to sift through depending on my search terms ("vhdl vim comment").
>From Hamish Moffatt:
"Commenting lines. Visual select the block required and type ,c
vmap ,c :s/^/--/
vmap ,d :s/^--//
Here's the Verilog equivalent:
"Commenting lines. Visual select the block required and type ,c
vmap ,c :s/^/\/\//
vmap ,d :s/^\/\///
Hmmm. These lines had an escape after the last character, but that
won't appear in this post. You could probably substitute '<CR>'
(without the quotes) instead.
Add the lines to the appropriate file type plugin file.
Regards,
Allan.
Article: 64135John Williams wrote: > Gus Baldauf wrote: > >> B. Joshua Rosen wrote: >> >>> Should work fine, I'm using Mandrake 9.2. >> >> >> >> I get the following error when I run the GUI setup. >> >> [root@quark cdrom]# ./setup >> Wind/U Error (294): Unable to install Wind/U ini file >> (/mnt/cdrom/data/WindU). >> See the Wind/U manual for more details on the ".WindU" file and the >> "WINDU" >> environment variable. >> Wind/U X-toolkit Error: wuDisplay: Can't open display > > > You haven't set the $DISPLAY environment variable to point to a valid X > server. > > something like "export DISPLAY=myxserver:0.0" > > where myxserver is the name of the computer that is running the X display. > > John > I am getting a glibc error when tryin to install under Fedora. Does anyone know a way around that? WilburArticle: 64136
Is there anybody who has experience at interfacing a WishBone IP core to a CoreConnect bus. Specifically the design of a bridge ? regards, TomArticle: 64137
Thanks a lot.I'm a beginner. I always use Schematic Editor because sometimes the vhdl file is hard to synthesize. Can you tell me which one is better,the schematic-Based design or HDL-based design? Can you recommend the type of fpga with a built-in multiplier?And how much it will cost?Article: 64138
Peter Alfke <Peter.Alfke@xilinx.com> wrote in message news:<3FE0DA9D.A27E7E4F@xilinx.com>... > Somebody from Xilinx is always listening :-) > The purpose of that press release was to create interest, exitement, and > suspense. > Obviously, it did succeed. > I know lots of technical details, but I cannot tell. For good reasons, > Marketing is in charge of releasing information. Please be patient, "you > will be richly rewarded"! > > It is still an FPGA, to be configured by the customer. We are not > entering the ASIC business... ( We just want to capture more of its $$$s > ) > > Peter Alfke > > Rahul Khanna wrote: > > > Xilinx seems to have launched a new architecture - ASMBL. There is no > > information except a news article. Can we have more info??? Is anyone > > from Xilinx Listening???? Looks like mixed jelly+peanut butter sandwich to me. Yum yum. Use as much of each as desired. ;) johnjaksonATusaDOTcomArticle: 64139
Dears Can anybody help me in realizing below Mathlab code to VHDL This is just a deceptive one, Tried in both DSPBuilder or SystemGenerator. If not possible by tool ,can anybody help me in hinting in Converting this to VHDL. Have many doubt's in DSPBuilder How to insert the FOR loop in DSP Builder and Variable and assignment's realized form it. Thanks in advance. Satish ---------mathlab code------------- % Inputs : Signal : 256 Samples, 16 bits each % constants Any value may be assigned to them for time being % XP : 256 * 16 Bits () % YP : 256 * 16 Bits % A % B % C % Rmin % Rmax % dR % D % Array : array 65536*16 or block RAM fftSig = fftshift(fft(fftshift(signal)),512)); for k = 1:256, for k2 = 1:256 tst =sqrt(( XP (k2)-A).^2+ (YP(k)-B)^2 +C^2); if (tst > Rmin & tst < Rmax-dR); IL = (tst –Rmin)/dR+1; Ind = floor (IL); Q =IL-Ind; px = fftSig(Ind)+Q .*… (fftSig(Ind+1)-fftSig(Ind)); INDEX = k + (k2 – 1)*256; ARRAY(INDEX)= ARRAY(INDEX) +px.*exp(-j*D*tst); % j= sqrt(-1) End End end --------------------------------------------Article: 64140
unexpectedvalue@yahoo.com (avalanche effect) wrote in message news:<1dcb9a53.0312170953.1b9e2e6c@posting.google.com>... > Just changing the Subject: to what is should have been ... > > > > > Googling web & usenet didn't provide answer or pointers - so here it > > goes: > > > > We have a fully tested design on fat Xilinx FPGA. Must go to ASIC, > > 0.18 or better. Relatively simple design, 3 clock domains, 300K gates. > > The only interface is USB, so very low pin count. If the foundry > > doesn't have USB phy in standard lib, we'll interface external phy. > > > > The question is - how long does it take - how many months ? We will > > farm that out, but I need some realistic idea about time between > > giving cash and working FPGA code to this outsourcing entity until we > > get first chips in sample quantities. > > > > I fully understand that each project is different, but feel > > uncomfortable with sales' quotes - I'd like to hear real experiences. > > > > And, BTW, are fabs busy these days or are they in mood for deals ? Check out Lightspeed and Flextronics. Lightspeed has a good story on their website clearly chasing after Xilinx architectures but I have no personal experience of either (yet). Apart from block rams, the IP is the big gotcha here. Lightspeed only customizes 2 layers of metal so it should be quick. johnjaksonATusaDOTcomArticle: 64141
Peter Sommerfeld wrote:
> Hi folks,
>
> I'm getting tired of commenting large blocks of VHDL code by hand.
>
> Anyone know of any Vim scripts that can comment/un-comment a VHDL
> block?
>
> A cursory Google search brings up either nothing or way too much stuff
> to sift through depending on my search terms ("vhdl vim comment").
>
> -- Pete
Try Emacs if you can. It has a very comfortable VHDL electric mode.
If you write -- at the beginning of a line and then press Enter, the
next line will also be commented.
--
Dietl Herwig
I am Murphy of Borg: Anything that can be assimilated will be.
Article: 64142Hi all, I want to export my design in XPS to Project Navigator but when the design is in XMDSTUB mode and not in Executable Mode. I have exported and opened the design with Project Navigator but when I download the bitstream to the FPGA I cannot connect with MicroBlaze via XMD. Does anybody know if is needed to add to the project any other file in the Project Navigator? I have tried adding "executable.elf" file with no success. Thanks in advance, Arkaitz.Article: 64143
Wilbur Harvey wrote: > I am getting a glibc error when tryin to install under Fedora. Does > anyone know a way around that? Have you set the environment variable "LD_ASSUME_KERNEL=2.4.1"? -GusArticle: 64144
Hello, have problem to access following web site: http://www.fpga-faq.com Know that it worked in the past, now following error occures (using IE 6.0): HTTP-Fehler 403 - Verboten Internet Explorer When using Mozilla 1.41 on MS or Linux machine we get following message: Forbidden You don't have permission to access / on this server. Access to all other web-sites we tested was OK, no such message in any way. Does http://www.fpga-faq.com still exist? Has anybody (had) the same problems? Any turn-around? with best regards, Peter Seng ############################# SENG digitale Systeme GmbH Im Bruckwasen 35 D 73037 Göppingen Germany tel +7161-75245 fax +7161-72965 eMail p.seng@seng.de net http://www.seng.de #############################Article: 64145
Hello All,
I'd like to know if the generally held advice that Distributed
Arithmetic (DA) filters are the "best" way to implement FIR filters on
an FPGA still holds good when one uses a Virtex-][.
In my application, I require a 256-tap filter which takes in
18-bit samples at 50 MSPS and decimates it down to 10 MSPS (coeffs are
16-bit). I use an XC2V3000. Currently, we don't have the hardware
required to synthesize the complete design (not enough memory), so
I've synthesized just the filter with a simple testbench. It turns out
that MAC FIR filters require far less resources than a DA-FIR one with
an equivalent spec. Could this be due to Virtex-]['s multipliers or is
this some quirk I'm not taking into account?
Thanks in advance.
-Jim.
Article: 64146Hello Peter, I have no problem accessing this site (IE 6.0). greetings, Kay "Peter Seng" <NOSPAM@seng.de> schrieb im Newsbeitrag news:brsfs5$8ag$1@online.de... > Hello, > > have problem to access following web site: > > http://www.fpga-faq.com > > > Know that it worked in the past, now following error occures (using IE 6.0): > > HTTP-Fehler 403 - Verboten > Internet Explorer > > > When using Mozilla 1.41 on MS or Linux machine we get following message: > > Forbidden > You don't have permission to access / on this server. > > > Access to all other web-sites we tested was OK, no such message in any way. > > Does http://www.fpga-faq.com still exist? > Has anybody (had) the same problems? > Any turn-around? > > > with best regards, > > Peter Seng > > > ############################# > SENG digitale Systeme GmbH > Im Bruckwasen 35 > D 73037 Göppingen > Germany > tel +7161-75245 > fax +7161-72965 > eMail p.seng@seng.de > net http://www.seng.de > ############################# > > >Article: 64147
hi all, I have to design a VHDL CRC-32 rtl macro cell (100BASE-T framing) for my tiny MAC design. I have to place my macro in a small spartan-3 where each Flip-Flips are precious. Is that possible to place a part of my CRC-32 in a LUT based shift register (feature of virtex to spartan-3). Since CRC-32 = x32 + x26 + x23 + x22 + x16 + x12 + x11 + x10 + x8 + x7 + x5 + x4 + x2 + x + 1, is that possible to do the job with LUTs based shift register. I know a lut only has 1 output, but is that possible to do partial shifts, like x31<-x30<-x29<-x28<-x27 in the same LUT ? Thanks for all Laurent Gauch www.amontec.com ____________________________________ Universal JTAG emulator solutions Rapid Prototyping solutionsArticle: 64148
Same error here (IE 6.0 + all patches, working from home): -- HTTP Error 403 - Forbidden Possibly someone applied 'optimum security' to their www directory tree :( I would try to contact the webmaster at fpga-faq.com.... Regards, MaEs "Kay Schubert" <kaytastroph@gmx.de> wrote in message news:3fe1c600$1@news.uni-rostock.de... > Hello Peter, > > I have no problem accessing this site (IE 6.0). > > greetings, > Kay > > > "Peter Seng" <NOSPAM@seng.de> schrieb im Newsbeitrag > news:brsfs5$8ag$1@online.de... > > Hello, > > > > have problem to access following web site: > > > > http://www.fpga-faq.com > > > > > > Know that it worked in the past, now following error occures (using IE > 6.0): > > > > HTTP-Fehler 403 - Verboten > > Internet Explorer > > > > > > When using Mozilla 1.41 on MS or Linux machine we get following message: > > > > Forbidden > > You don't have permission to access / on this server. > > > > > > Access to all other web-sites we tested was OK, no such message in any > way. > > > > Does http://www.fpga-faq.com still exist? > > Has anybody (had) the same problems? > > Any turn-around? > > > > > > with best regards, > > > > Peter Seng > > > > > > ############################# > > SENG digitale Systeme GmbH > > Im Bruckwasen 35 > > D 73037 Göppingen > > Germany > > tel +7161-75245 > > fax +7161-72965 > > eMail p.seng@seng.de > > net http://www.seng.de > > ############################# > > > > > > > >Article: 64149
> If you write -- at the beginning of a line and then press Enter, the > next line will also be commented. Not to start an emacs vs. vim war, but a properly set-up vhdl plug-in in vim will do this as well. -- Pierre-Olivier -- to email me directly, remove all _N0SP4M_ from my address --
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