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Patrick MacGregor <patrickmacgregor@comcast.net> wrote: : Apparently you didn't know that Cyclone and Spartan 3 are contemporaries? : Both are new products just being released, and squarely aimed at low-cost : markets. Both were introduced to the public about the same time, to much : fanfare and to ambitious pricing and availability schedules. Cyclone was announced Sep 2002, Spartan April 2003. When where Cyclone available from distributors? Bye -- Uwe Bonnes bon@elektron.ikp.physik.tu-darmstadt.de Institut fuer Kernphysik Schlossgartenstrasse 9 64289 Darmstadt --------- Tel. 06151 162516 -------- Fax. 06151 164321 ----------Article: 64226
Read this: http://www.national.com/an/AN/AN-1085.pdf -2.7V spikes for 200 ns "Masoud Naderi" <naderimisc@yahoo.com> wrote in message news:2ba3bbea.0312210846.3ed95f90@posting.google.com... > Hi, > I measured ground voltage difference between two side of cable, it was > very small (<0.1V). However I like to install a low impedance( againt > high frequency noises) cable between two racks, but I have not > acceptable reasons for this! > please guide me on this. > regards. > > > "tbx135" <tbx135@msn.com> wrote in message news:<%DtEb.42912$yp5.14836@newssvr31.news.prodigy.com>... > > This sounds like a grounding problem, whose LVDS drivers are you using? > > > > "Masoud Naderi" <naderimisc@yahoo.com> wrote in message > > news:2ba3bbea.0312152232.5d87d9d2@posting.google.com... > > > Hi, > > > Our LVDS Drivers failed when their power supply starts(it has soft > > > start feature). On some boards only positive output or input of > > > differential side failed (probably because of high current sourcing in > > > failure mode). > > > I checked power suppply yesterday and found some negative (-2.7v) but > > > very narrow (200ns) spikes on power supply rail. I think it is one of > > > the problems. LVDS drivers are from TI and spikes below -0.5 damage > > > them. I look for more problem, e.g. grounding and ... > > > > > > here are some shematic of our system: > > > > > > LVDS+/- <-............3meter twisted-pair cable...............-> > > > LVDS+/- > > > GND ----------------------------------------------------------> GND > > > > > > regards > > >Article: 64227
Xilinx has done this before with delivery dates...Nothing new, and yep, the big customers get first dibs on everything. Spartan III is not on ship hold and the typical ramp-ups that I saw all the way back to the 4K family are issues again. Now I design a dual foot-print (if I can) or a integration path to the wonderful new part promised to me by our vendor. So be patient kids, Santa will show up with the goodies! The distributers are relaying bullshit stories told to them by Xilinx, who, always get there with the parts eventually.Article: 64228
>Let me set the record straight on the Cyclone front. Altera delivered That's why I'm using A-brand :-) Also I'm getting happy that Altera started monitoring this group. -- JerryArticle: 64229
> Apparently you didn't know that Cyclone and Spartan 3 are contemporaries? > Both are new products just being released, and squarely aimed at low-cost > markets. Your dictionary must have a different definition of 'contemporary' than mine. Cyclone samples were available last February. > Altera is building a good track record regarding what they say and > what they actually deliver. Not perfect, as shown by their recent > backpeddling on some Stratix termination features, but still very, very > respectable. I wouldn't argue with this. The thread was about availability of devices which are _currently_ being released and you said you use Altera devices because you can get devices which have been out for nearly a year. The same argument could be used for Xilinx becasue SpartanIIs are freely available. NialArticle: 64230
I assume you want the VHDL to synthesize, if you just want to simulate in VHDL use the real data type and translate line for line. I also assume that for some reason you know you want custom hardware rather than running on some general purpose computer after translaing to C (or whatever). If you want to build hardware then your problem is more than just tranlating code, first you need a hardware architecture (this might be why you are stalled). Some things to think about: 1) fft, sqrt, and exp, what algorithms will you use for these? You might find fft IP, but for the others you probably just have to do the work. 2) What is you required through put? how much silicon can you afford? These might tell you if you want to unroll the loops. As an aside unrolling would (I think) turn the sqrt and exp to constants, and zero hardware, but you would have a *really* deep pipeline, start to think about a few million registers (256*265*16 at a minimum). 3) What is the actual nature of the input in the real world, is it just 256 words, or a stream or words, or blocks of 256 words? This will infuuence your choice of architecture 4) Hardware is usually clocked, be prepared to think about where to put registers and why. (I assume Accel Chip will do this for you) OK, now enter your architecture in what ever method make you happy, VHDL in a text editor, Altera/Xilinx blocks in Simulink, and so on. Remember: programs = algorithms + data structures. Well you have an algorithm, but you need a hardware structure. > > satishkmys@yahoo.com (Satish K) wrote in message news:<380e8c67.0312180513.36368710@posting.google.com>... > > > Dears > > > > > > Can anybody help me in realizing below Mathlab code to VHDL > > > This is just a deceptive one, Tried in both DSPBuilder or > > > SystemGenerator. > > > > > > If not possible by tool ,can anybody help me in hinting in Converting > > > this to VHDL. > > > > > > Have many doubt's in DSPBuilder > > > How to insert the FOR loop in DSP Builder and Variable and > > > assignment's realized form it. > > > Thanks in advance. > > > Satish > > > > > > ---------mathlab code------------- > > > > > > % Inputs : Signal : 256 Samples, 16 bits each > > > % constants Any value may be assigned to them for time being > > > % XP : 256 * 16 Bits () > > > % YP : 256 * 16 Bits > > > % A > > > % B > > > % C > > > % Rmin > > > % Rmax > > > % dR > > > % D > > > > > > > > > % Array : array 65536*16 or block RAM > > > > > > fftSig = fftshift(fft(fftshift(signal)),512)); > > > > > > for k = 1:256, > > > for k2 = 1:256 > > > tst =sqrt(( XP (k2)-A).^2+ (YP(k)-B)^2 +C^2); > > > if (tst > Rmin & tst < Rmax-dR); > > > IL = (tst ?Rmin)/dR+1; > > > Ind = floor (IL); > > > Q =IL-Ind; > > > px = fftSig(Ind)+Q .*? > > > (fftSig(Ind+1)-fftSig(Ind)); > > > INDEX = k + (k2 ? 1)*256; > > > ARRAY(INDEX)= ARRAY(INDEX) +px.*exp(-j*D*tst); % j= sqrt(-1) > > > End > > > End > > > end > > > --------------------------------------------Article: 64231
"Farhan" wrote: > Is there anyone who have ideas that what sort of DSP or telecom > applications we an implement on Vertex II Pro .... OK, so you got beat over the head for posting a dumb question. Let's see if we can pull it out of the dive. What's your context? Who are "we" in your question? Are you students trying to figure out what kind of a project you can do? Are you a hobbyists? Do you work for a company and you are just getting started with FPGA's? Do you have any experience with FPGA's at all? Are you a hardware engineers? Software engineers? VII Pro's are very powerful chips. There's a huge range of designs that could be handled with the various members of that family. The more benign answer to your question is: Yes, of course, lots of people have ideas on what can be implemented on a VII Pro. Your specific context is what might reveal wheter or not they are the appropriate choice. -- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ Martin Euredjian To send private email: 0_0_0_0_@pacbell.net where "0_0_0_0_" = "martineu"Article: 64232
All, I am trying to implement a design in a Xilinx Spartan II FPGA, where I desire to use Block Ram as internal memory. I have run my design through simulation, where everything works fine. However, after synthesis and programming the FPGA, the system acts as if the RAM wasn't there. Is there something I'm missing? I've ensured that I am accessing the memory synchronously. Other than that, I'm stumped. I wouldn't think that timing is an issue (24Mhz main clock). Any ideas? Thanks, Chuck GalesArticle: 64233
Look at the EDF through a reader. Make sure it's not an empty component. You should also see this in transcript. "Chuck Gales" <cgales@_NOSPAM_nc.rr.com> wrote in message news:pan.2003.12.21.22.25.24.447595@_NOSPAM_nc.rr.com... > All, > I am trying to implement a design in a Xilinx Spartan II FPGA, where I > desire to use Block Ram as internal memory. I have run my design through > simulation, where everything works fine. However, after synthesis and > programming the FPGA, the system acts as if the RAM wasn't there. > Is there something I'm missing? I've ensured that I am accessing the > memory synchronously. Other than that, I'm stumped. I wouldn't think > that timing is an issue (24Mhz main clock). > Any ideas? > > Thanks, > > Chuck GalesArticle: 64234
[1] Here is some verilog sample code for IBUFG for LVPECL :
IBUFG_LVPECL buf_000_p (.I(pad_sys_clk_100mhz_p),
.O(sys_clk_100mhz) );
IBUFG_LVPECL buf_000_n (.I(pad_sys_clk_100mhz_n), .O() );
[2] Generally, take a look at the lib.pdf in the installed directory
C:\xilinx\doc\usenglish\docs\lib. This is the perfect document to
check which Xilinx primitives are available in each family. Also,
contains examples for instantiation, as well as associated .ucf
references.
--
Regards,
John Retta
Owner and Designer
Retta Technical Consulting Inc.
email : jretta@rtc-inc.com
web : www.rtc-inc.com
"Warine" <xk_ch@163.com> wrote in message
news:7124b232.0312200615.4dc0e37a@posting.google.com...
> I try to use differential clock pin with component "ibufgds", but ise5.1i
> reports error:"SpartanIIE doesn't support symbol ibufgds". The online
> documentation of ise5.1i says "ibufgds" is N/A in SpartanIIE. How can I
> use differential clock pin of SpartanIIE?
>
> Thanks
> Warine
Article: 64235The other respondant had the correct idea. Lots of times outputs signals from one logic function to another might be misnamed, and hence the source block might be optimized away. Problem is that the offending problem may be several layers past the block which has been eliminated, and for some reason the synthesis tools are not as clear as they used to be where the problem is located. The simulator is usually a good place to isolate these problems, although it sounds like you have tracked the data paths already. Check the .mrp report in your synthesis directory, and make sure the number of block rams are what you expect. If I have 100 synthesis runs for a design over 2 months, I check this file every run. -- Regards, John Retta Owner and Designer Retta Technical Consulting Inc. email : jretta@rtc-inc.com web : www.rtc-inc.com "Chuck Gales" <cgales@_NOSPAM_nc.rr.com> wrote in message news:pan.2003.12.21.22.25.24.447595@_NOSPAM_nc.rr.com... > All, > I am trying to implement a design in a Xilinx Spartan II FPGA, where I > desire to use Block Ram as internal memory. I have run my design through > simulation, where everything works fine. However, after synthesis and > programming the FPGA, the system acts as if the RAM wasn't there. > Is there something I'm missing? I've ensured that I am accessing the > memory synchronously. Other than that, I'm stumped. I wouldn't think > that timing is an issue (24Mhz main clock). > Any ideas? > > Thanks, > > Chuck GalesArticle: 64236
This may be sheer laziness, but how do I find out the stepping of a
V2?
I had worked out a design where I ran a MAC-based filter at 130 MHz, I
hope my V2's multipliers (-5 grade) can take it. I'm not looking at
very large precision, so I wont need multiple passes through the
multipliers.
-Jim.
Ray Andraka <ray@andraka.com> wrote in message news:<3FE34730.C68AB68@andraka.com>...
> Ah yes, without placement, the DA filters, especially with parallel bits don't fare well with the place and route
> tools. I've got a design I'm putting the finishing touches on right now that has DA filters implemented in a 2V3000-4
> (stepping 0). It has 30 bit coefficients, and in some places up to 40 bits arithmetic. I have no problem getting to
> to run at a 160 MHz clock in the -4 part. The areas I have had timing difficulties are in routing to-from the brams
> that are used as delay queues, mostly because I was too lazy to place them and the placer does a lousy job placing
> brams. Anyway, in this case, using multipliers would have required a bigger part. The multipliers in the stepping 0
> devices can't be clocked at 160 MHz, plus due to the data widths I'd need to use four multiplies to complete each
> multiplication. In this design, the DA approach was a clear winner.
>
> There is a data ordering quirk with the decimating MAC filter. You have a similar quirk with a DA filter if you are
> sending multiple channels thorugh the filter. Nothing a bit of ingenuity won't fix.
>
Article: 64237> > Googling web & usenet didn't provide answer or pointers - so here it > > goes: > > > > We have a fully tested design on fat Xilinx FPGA. Must go to ASIC, > > 0.18 or better. Relatively simple design, 3 clock domains, 300K gates. > > The only interface is USB, so very low pin count. If the foundry > > doesn't have USB phy in standard lib, we'll interface external phy. > > > > The question is - how long does it take - how many months ? We will > > farm that out, but I need some realistic idea about time between > > giving cash and working FPGA code to this outsourcing entity until we > > get first chips in sample quantities. > > > > I fully understand that each project is different, but feel > > uncomfortable with sales' quotes - I'd like to hear real experiences. > > > > And, BTW, are fabs busy these days or are they in mood for deals ? One option for a low-risk ASIC conversion is to convert the design to Stratix, then use Altera's HardCopy conversion to an ASIC. It does mean you have to do an FPGA conversion, but that's easy to test immediately because you can try the FPGA right away. Then the ASIC conversion (HardCopy) is relatively easy, since you use the same synthesis & placement tools as you did for the FPGA, and all the tricky IP blocks like RAMs are the same in the HardCopy array as they are in the FPGA. So it's a two-step conversion process, but it lowers your risk. Vaughn AlteraArticle: 64238
jaxlau@yahoo.com (Jacques athow) wrote in message news:<acc717b2.0312150350.29f7dd9e@posting.google.com>... > I wanted to know which particular software from altera give support, > in terms of synthesis, P&R and downloading to this chip. Is the ALTERA > Max + Plus II suitable to program those chip? > > And also, it seems that the 10K50E part is an obsolete part that has > been replaced by the 10K50S. Is there any difference between them, in > terms of implementation and bitstream compatibility? > > Thanks for any help! > happy holidays Hi Jacques, Max + Plus II will work with the 10K family. So will Altera's newer CAD system, Quartus. Quartus is more powerful and supports all Altera's newer families, and achieves better fitting & speed for the 10K family than Max + Plus II does, on average. Also, Max + Plus II is not really being extended anymore -- it is an older CAD system we support for customers who are used to it, but it is not being enhanced in significant ways anymore. So I would recommend you use Quartus. VaughnArticle: 64239
shardendu@verizon.net (a2zasics) wrote in message news:<1c97c9ba.0312081405.1013564b@posting.google.com>... > Hi, > I have an Altera FPGA, which shows hold violation on an input pin. The > first FLOP is positive edge triggered and in IOB. To get rid of the > roughly 2 ns margin in hold, i put -3ns phase shift in clock output of > PLL that clocks the input register. Apparently this was ignored in > hold time calculation. Can someone point out why ? A negative shift in > clock should have made hold time better in this case. > > Shardendu Hi Shardendu, Which Altera FPGA are you using? You are right that shifting your clock backward should help the hold problem. It's hard to say what's going on here without seeing your design -- if you send it to me, or a small test case showing the problem behaviour, I can have someone look at it. One thing to check: make sure you've set a Th = 0 constraint on this register if that's the constraint you want met. Without a constraint like that, Quartus won't be trying to ensure you get a 0 or negative hold time. Vaughn AlteraArticle: 64240
Jim George wrote: > I had worked out a design where I ran a MAC-based filter at 130 MHz, I > hope my V2's multipliers (-5 grade) can take it. You can do well over 180MHz with the multipliers (registered version) in a -5. You have to layout the in/outs precisely and force very specific routing via timing constraints. Check out XAPP636 http://direct.xilinx.com/bvdocs/appnotes/xapp636.pdf -- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ Martin Euredjian To send private email: 0_0_0_0_@pacbell.net where "0_0_0_0_" = "martineu"Article: 64241
I just got done reading a through a couple of recent threads on the subject of "the best machine" to build for Xilinx tools. Last week I had a conversation the head a a design group who said that "getting hyperthreading systems for my engineers made a huge difference in performance". I'm looking to replace a 1.8GHz P4 with the latest and greatest and I find myself confused between hyperthreading and dual processor boxes as two distinct options at (maybe) different ends of the scale. Also, Xeon vs. P4? Sorry to stirr-up a slightly different version of a recent thread. -- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ Martin Euredjian To send private email: 0_0_0_0_@pacbell.net where "0_0_0_0_" = "martineu"Article: 64242
On Mon, 22 Dec 2003 10:26:20 GMT, "Martin Euredjian" <0_0_0_0_@pacbell.net> wrote: >I just got done reading a through a couple of recent threads on the subject >of "the best machine" to build for Xilinx tools. Last week I had a >conversation the head a a design group who said that "getting hyperthreading >systems for my engineers made a huge difference in performance". > >I'm looking to replace a 1.8GHz P4 with the latest and greatest and I find >myself confused between hyperthreading and dual processor boxes as two >distinct options at (maybe) different ends of the scale. Also, Xeon vs. P4? > >Sorry to stirr-up a slightly different version of a recent thread. We have a dual processor box here with hyperthreading (i.e. 2 processors, each capable of running 2 threads at the same time) that we use for running xilinx software. I don't notice any great difference in speed when hyperthreading is switched on or off. I have it switched *off* at the moment, because that is supposed to be faster for the single threaded apps we are running (at most two apps at a time). The benefit of hyperthreading would be much more significant if there was only a single processor, or if there were lots of threads running. Note that hyperthreading doesn't work with win2k; you need XP (or SMP Linux). Regards, Allan.Article: 64243
On Mon, 22 Dec 2003 04:51:48 +0000, John Retta wrote: > The other respondant had the correct idea. Lots of times outputs signals > from one logic function to another might be misnamed, and hence the source > block might be optimized away. Problem is that the offending problem may > be several layers past the block which has been eliminated, and for some > reason the synthesis tools are not as clear as they used to be where the > problem is located. > > The simulator is usually a good place to isolate these problems, although > it sounds like you have tracked the data paths already. > > Check the .mrp report in your synthesis directory, and make sure the > number of block rams are what you expect. If I have 100 synthesis runs > for a design over 2 months, I check this file every run. Looking at the .mrp report, I see the 4 block rams as expected. Also, the post-synthesis HDL model functions correctly, so it seems that everything is being synthesized correctly. There doesn't seem to be any critical warnings or errors about the Block Ram. I do receive the following warning: WARNING:Xst:1772 - You have explicitly defined initial contents for this RAM, which are currently ignored when the RAM is implemented with LUT resources, leading to incorrect circuit behavior. Changing the RAM description so that it is read synchronously will allow implementation on block RAM resources for which we provide full initial contents support. I am not really sure why this warning is received, since the ram is designed with RAMB_S4 primitives and accessed synchronously. Could this lead to something? ChuckArticle: 64244
"Philip Freidin" <philip@fliptronics.com> schrieb im Newsbeitrag news:jnv3uv01f53q4reievis7nnnqubqtphb8v@4ax.com... > On Thu, 18 Dec 2003 16:07:33 +0100, "Peter Seng" <NOSPAM@seng.de> wrote: > >Hello, > > > >have problem to access following web site: > > > >http://www.fpga-faq.com > > > >Know that it worked in the past, now following error occures (using IE 6.0): > > Hello Peter and others, > > The problem with www.fpga-faq.com is ME. I am the owner and webmaster and > maintainer for this site. > > I am sorry to say it has nothing to do with which browser you are using, > it is my lack of experience in handling web access abuse. > > Currently I am implementing some fairly draconian access controls on the site > due to my lack of experience in doing it more nicely. > > A little history: I created this site a few years ago and have maintained > it and paid for it with my own money. As you know, it is vendor neutral, > and has no advertising, popups or other trash. Sort of a charity project. > > In October and November 2003, someone using 2 IP addresses attacked the > site and in a matter of 1 or 2 days, early in both months, managed to use > more than the total bandwidth allowance for the whole months (20 GB per month) > This lead to some very high excess bandwidth charges, that were about > 10 times my monthly costs. (normal bandwidth for a whole month is about > 10 to 12 GB) > > While researching the problem, I found that there were multiple other > webcrawler type accesses that were not comming from known search engines. > Google, Inkotomi, Yahoo, Altavista, AskJeeves together represent about 97% > of all referrer traffic. In particular, some of these crawlers are > deliberately masking their identity. > > Most of this high bandwidth traffic is coming through DHCP IP management, > and so the IP address changes within various blocks. > > I have now started blocking IP addresses, and you have been unfortunately > caught up in this. > > Although I have enabled the IP address that you used earlier today, > I believe your IP is dynamic, and so this may not have helped you. > (your IP was 80.145.86.184, gatewayed through online.de) > > If there is someone who is very knowledgeable about Apache web servers, > the .htaccess files, and the rewriting rules creation, I would appreciate > some help. > > My other alternative would be to use a service with higher bandwidth > limits, but to support that I would have to have advertising or some > other way to fund the change. > > I am glad that this was a service that was useful for you, and really > sorry it isn't working for you currently. I am actively trying to find > a solution to this problem. > > ======== > > Separately, for those of you still using the Xilinx gateway to this > news group, could you please change over to using the Google Groups > gateway. Both are free, but the Xilinx one is still turning nice text > posts into HTML, which then wastes a few hours of my time each month > cleaning up the mess. > > > All the best for the Holliday Season! > > > > > =================== > Philip Freidin > philip@fliptronics.com > Host for WWW.FPGA-FAQ.COM Hello Philip, thanks for answer. I´m not experienced in Web-Hosting too, hope there´ll be a solution in future... Good idea to make the web-page available and just block the archive. Merry Christmass And A Happy New Year! Peter Seng ############################# SENG digitale Systeme GmbH Im Bruckwasen 35 D 73037 Göppingen Germany tel +7161-75245 fax +7161-72965 eMail p.seng@seng.de net http://www.seng.de #############################Article: 64245
Hyperthreading is a take-off on the parallel processing direction utilizing the numerous execution units on the die. I believe it was cost-effective as well. The advantages are savings in real-estate on the board over a multiple chip architecture. Utilization by applications at present are scarce. I hoping Intel develops this further as on-chip parallel processing would be (what I believe) the best way to over-come speed and power concerns.Article: 64246
> WARNING:Xst:1772 - You have explicitly defined initial contents for this > RAM, which are currently ignored when the RAM is implemented with LUT > resources, leading to incorrect circuit behavior. Changing the RAM > description so that it is read synchronously will allow implementation on > block RAM resources for which we provide full initial contents support. > > I am not really sure why this warning is received, since the ram is > designed with RAMB_S4 primitives and accessed synchronously. > > Could this lead to something? > > Chuck The Libraries guide, page 1481 talks about the primitive RAMB4_Sn, which is what I think you meant. According to your message, XST does not think you are using the Block RAM resource. It is using a LUT instead. Did you use the coregen tool to make this? Spartan II Block Ram uses a .coe to initialize contents. Are you using this as well?Article: 64247
Check this one out too. http://toolbox.xilinx.com/docsan/xilinx4/data/docs/sim/vtex11.html My guess is that you behaviorally changed this and XST now is instantiating a LUT version of the memory. That would be a new one on me...Article: 64248
ISE 6.2i will support the Parallel 4 cable on Linux. Uwe Bonnes wrote: >Rudolf Usselmann <russelmann@hotmail.com> wrote: >: I just found out that ISE 6.1 for Linux does not support >: the Parallel Cable 4 (both products from Xilinx ! ). > >: Does anybody know of a tools that will allow me to use >: the Parallel Cable 4 under Linux ? (All I need is JTAG >: download and verify). > >As Download Cable uses a WinDriver driver and WinDriver is also available on >Linux, I thought ISE 6.1 for Linux would support Parallel Cable 4 for Linux >too. Sad to hear that it is not the case. >http://www.xilinx.com/xlnx/xebiz/html/cable_compar_chart.htm >also doesn't mention Linux for "ISE 6.1 for Linux" > >If Xilinx would look at the Linux Parport/ppdev API, it should be easy for >them to write a driver in a short time. > >For now you can have a look at NAXJP >(http://www.nahitech.com/nahitafu/naxjp/naxjp-e.html), which supports some >devices. Nahitafu's idea to use the bit file for programming seema also to >consider. > >Bye > >Article: 64249
On Mon, 22 Dec 2003 21:48:05 +1100, Allan Herriman wrote: > On Mon, 22 Dec 2003 10:26:20 GMT, "Martin Euredjian" > <0_0_0_0_@pacbell.net> wrote: > >>I just got done reading a through a couple of recent threads on the subject >>of "the best machine" to build for Xilinx tools. Last week I had a >>conversation the head a a design group who said that "getting hyperthreading >>systems for my engineers made a huge difference in performance". >> >>I'm looking to replace a 1.8GHz P4 with the latest and greatest and I find >>myself confused between hyperthreading and dual processor boxes as two >>distinct options at (maybe) different ends of the scale. Also, Xeon vs. P4? >> >>Sorry to stirr-up a slightly different version of a recent thread. > > We have a dual processor box here with hyperthreading (i.e. 2 > processors, each capable of running 2 threads at the same time) that > we use for running xilinx software. > > I don't notice any great difference in speed when hyperthreading is > switched on or off. I have it switched *off* at the moment, because > that is supposed to be faster for the single threaded apps we are > running (at most two apps at a time). > > The benefit of hyperthreading would be much more significant if there > was only a single processor, or if there were lots of threads running. > > Note that hyperthreading doesn't work with win2k; you need XP (or SMP > Linux). > > Regards, > Allan. Dual processors are very useful, hyperthreading in it's current incarnation on the P4 isn't. I have a dual Xeon system, I did a lot of benchmarking when I got it and found that hyperthreading improved the throughput slightly (about 10%) while hurting single thread performance by about 25%. It's not clear why hyperthreading works so badly on the P4, it could be a hardware issue, when hyperthreading is on the number of registers available to a single thread is halved as is the cache size. It's also prossible that the 2.4.x scheduler doesn't do a good job on hyperthreaded systems. It's possible that hyperthreading will work better on 2.6 kernels, I haven't tried 2.6 yet so I don't know. In the long run dual Opterons should do better than dual Xeons because each Opteron has it's own memory system so the total available memory bandwidth of a dual Opteron system is twice that of a dual Xeon. However memory access in an Opteron system is non-uniform (NUMA), specifically access to RAM on the other processor is much slower than access to local RAM. The 2.6 kernel is supposed to do a good job with NUMA systems, chances are the 2.4 kernel is sub-optimal in this area so it's possible that a Dual Opteron system won't live up to it's potential with a current distribution. I have minimal experience with Opterons so I'm not really qualified to speak about their current performance except to say that even with the 2.4 kernel it's competitive with the the Xeon (the dual Opteron system that I tried was roughly equal to a dual 3GHz Xeon when doing a big make -j 2).
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