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> http://www.altera.com/support/software/eda_quartus2/glossary/def_cam.html This feature is only available in APEX, Excalibur, and Mercury. - Paul Leventis Altera Corp.Article: 61651
-----BEGIN PGP SIGNED MESSAGE----- Hash: SHA1 i am searching for an alternative for Xilinx programming software, and i found the http://www.nahitech.com/nahitafu/naxjp/naxjp-e.html very useful. the only thing the software can not do, is to programm the Write / Read protect flags. Does anybody here know a datasheet for my Xilinx CPLD XC95144XL , so i can expand the software ? thx. franz -----BEGIN PGP SIGNATURE----- Version: PGPfreeware 7.0.3 for non-commercial use <http://www.pgp.com> iQA/AwUBP4P6ERbHVw21GxJvEQI8GACgzoMq27hVWhhl9RUfTqQ4+Hz2yogAoK0L W1xLEtK82w/H/syadS6ASo+k =yjgA -----END PGP SIGNATURE-----Article: 61652
"Tim" <tim@rockylogic.com.nooospam.com> wrote in message news:<blvdot$3f4$1$8302bc10@news.demon.co.uk>... > Martin Euredjian wrote: > > > > At the risk of sounding stupid. I can't find an EDIF (old ".edn")file > > anywhere and NGD2EDIF doesn't seem to be supported any more (running > > 6.1i). Where do I look? I used NGD2VER to create a simulation model. > > It clearly shows one instance of the macro and two instantiations. > > However, all placement info is gone, as this is a simulation model. > > Another reason why I try to persuade my customers to buy a > copy of Synplicity. I guess you are using the X tool which > bypasses EDIF. Bummer. I also prefer Synplicity, but you can use NGC2EDIF to look at the output of XST. http://www.fpga-faq.com/archives/58175.html#58181 BrianArticle: 61653
Simon, Synplify does not give you the option of a edif output file for Apex devices. If it does, I certainly don't know about it. Bob Mike Treseler <mike.treseler@flukenetworks.com> wrote in message news:<3F82F013.5000007@flukenetworks.com>... > Bob wrote: > > > I re-synthesized the design again in Synplify and got the same result > > as before so there is definitely some problem in the flow between the > > two tools. It certainly looks like I'm back to the drawing board > > design wise. > > > > If you can think of anything else, I would be very grateful. > > Maybe you can eliminate the flow between the tools. > Try bypassing Synplify and process your source files > directly with Quartus synthesis. > > -- Mike TreselerArticle: 61654
Andres, I've written two responses, one assuming you want a CAM (that is, something that you give an entry of 16-bits to and it tells you whether that entry is in one of the 32 slots of the CAM), the other assuming you can get away with a cache. *** If you really do need a CAM *** CAMs are expensive to implement. You need to look at ALL the data in your cache at once in order to find a match (in a single cycle) and hence using a memory is not a great fit for this task. You're stuck implementing your CAM in logic if you need single-cycle access. With 32 entries of 16 bits each, this means 32x16 = 480 LEs just for the registers. But it's not as bad as it seems -- the LUTs in these LEs will still be used (automatically) by Quartus for related logic if such logic is available, or unrelated logic if your design is getting full. I'd also worry about the explosion in the amount of logic required for comparison if you are doing single-cycle matching. One technique you can use to half or further reduce time & comparison hardware and still use a RAM: use a wider RAM. You can get two entries/cycle just by using a 16x32 RAM (32-bits wide) which maps into a single M4K block in Cyclone. Or go up to an 8x64 or 4x128 RAM. This way you are retrieving multiple entries/cycle. Note: Just use the lpm_ram megafunction. Quartus will automatically make use of the right combination of M4K blocks to implement the RAM you need "behind your back". If you expect a lot of misses and would like misses to come back quickly, you could store your data differently. For example, use a 4x128 RAM and instead of storing 8 entries per address, store the first 4-bits of all 32 entries in the 1st address, the next 4-bits in the 2nd adress, etc. In each clock cycle you are comparing 4-bits of every entry to 4-bits of the target word. But this way you get an early exit on a miss. I'm no CAM expert and I'm sure there'll be a bunch of other ideas that come up... *** If you are looking for a cache *** Jonathan gives a nice description of direct-mapped and N-way set associative caching. I'll just add a few points and ideas. As a rule of thumb, increasing cache size yields better results (in a microprocessor) than increasing associativity. In selecting the cache design for your system, you need to take into account the memory access patterns, the speed you need to run your system clock at, tolerable cache latency, etc. Switching from a direct-mapped (i.e. 1-way associative) to 2- or 4-way set associative cache will mean that you require more logic for performing reads & writes, and depending on the speed your clock is running at, this may limit the speed of your system. Often you must run software emulations of a system to determine what the best cache is -- I'd suggest trying 1-way, 2-way and 4-way set associative caches of various sizes and comparing the increase in efficiency (i.e. # of clocks required per instruction on average) of your system across simulated, real-world data that it will handle. Then compare this to the relative clock speed that those different systems will run at (which will require implementing both a direct-mapped and N-way associative cache in HDL). Also, note that making a cache deeper is nearly free in Cyclone if you aren't using your memory blocks for other features. You get a 128x36 RAM for the same price as a 32x36 RAM -- so you might as well make a 128-entry direct mapped cache. Or you can stitch multiple RAMs together (automatically through lpm_ram) to create a deeper cache. Regards, Paul Leventis Altera Corp.Article: 61655
In article <3f8335fc$1$28122$afc38c87@news.optusnet.com.au>,
"Arthur Sharp" <arthur@nospam.com> writes:
|
|> The problem is that, in my setup script, it sets the variable WUHOME as
|> /media/cdrom/data and then it fails, not surprisingly since
|> /media/cdrom/data is empty !!!
The shell trace shows the same behavior for "my" version... But I think I know
why it fails: If I try to start the setup as root, I get the same error. It
works as a "regular" user... The cause seems to be a problem with the
X-server access of the windu-stuff.
--
Georg Acher, acher@in.tum.de
http://wwwbode.in.tum.de/~acher
"Oh no, not again !" The bowl of petunias
Article: 61656Yes. You can factorize 128 as 64*2 and use a radix-4 FFT to do two 64 point FFTs followed by a two-point FFT ( butterfly ). You can follow it with a 3-point FFT to get 192. Sandeep stenasc@yahoo.com (Bob) wrote in message news:<20540d3a.0310080012.1a857848@posting.google.com>... > Hello again, > > Can a radix-4 fft be used to construct any type of radix-2 fft. e.g. > can I manipulate a 64 pt radix-4 fft to give me a 128 pt radix-2 fft ? > If so, is the radix-2 fft of any use in dsp as it usually results in > larger and slower ffts than the radix-4 version. > > > As always thanks for all replies. > > Bob CarterArticle: 61657
Yes, like that one. I forgot I had a link to it. I went and updated all
the links on the links page this morning. There were a number of them that
had new homes, Thanks for reminding me and bringing it to my attention.
Martin Thompson wrote:
> Like this one? I rememebred seeing this mentioned a few weeks ago - a
> quick google and I found a link to it... from andraka.com of all
> places :-) [ Ray, you might want to update the link ]
>
> http://www.rockylogic.com/freebies/freebies.html
> Scroll down to "Locking Logic to a Single Xilinx Virtex LUT"
>
> Cheers,
> Martin
> --
> martin.j.thompson@trw.com
> TRW Conekt, Solihull, UK
> http://www.trw.com/conekt
--
--Ray Andraka, P.E.
President, the Andraka Consulting Group, Inc.
401/884-7930 Fax 401/884-7950
email ray@andraka.com
http://www.andraka.com
"They that give up essential liberty to obtain a little
temporary safety deserve neither liberty nor safety."
-Benjamin Franklin, 1759
Article: 61658banktrade2002@yahoo.com (Emile) writes: > Can someone suggest a project/application that would call for an > XC2V6000-4BF957C? Thanks. Sorry, need speedgrade -6. Homann -- Magnus Homann, M.Sc. CS & E d0asta@dtek.chalmers.seArticle: 61659
Hi Antti, I've done a flash loader but I don't know which file do I have to store in flash in order to enable to execute it. I've proved storing the "executable.elf" file which contains the crt0.o initialization code linked and then I jump to that address from a program stored in the Block RAMS, but as I supposed it doesn't work. So may be I'm wrong but what I have in mind is to have a program stored in flash and then store a simple program in the Block RAMs where there is only a branch to the flash base address. What do you think about this and how would it be done? Thanks a lot, Arkaitz. antti@case2000.com (Antti Lukats) wrote in message news:<80a3aea5.0309160942.23beb3dd@posting.google.com>... > you create a small flash loader that you use to program your flash, > then you run your programs from flash. optionally you may copy to sram > but it in your case I think it doesnt make sense. > > the flash loader is not a problem, but for programs that are then executed > from flash you need to use custom linker script and optionally copy > some segments to sram, also you should use sram for stack and heap, > as the blockrams get low for that too. > > if you have not done that before it will take you approx 2 weeks to get > fully it runnging and set up. > > antti > > > > agaztelu@ikerlan.es (Arkaitz) wrote in message news:<b79e7ab9.0309160241.3eef5362@posting.google.com>... > > Hi all, > > > > I'm trying to design a Microblaze system which uses an external SRAM > > as instruction memory. I'm using the V2MB1000 board from Insight Memec > > with P160 Communication module. > > > > The SRAM is conected to Microblaze through an external memory > > controller conected to the Instruction side OPB bus. > > The thing is that I don't know how to save my "executable.elf" file to > > the external SRAM. > > I've seen other microprocessors that firstly they copy the program > > from flash or another Read Only storage device to a faster memory, > > such as SRAM. They use a boot program, stored in FLASH, to do this. > > > > But in my system I don't know neither how to save it to the FLASH > > because my program is too large and it can't be stored in the Block > > RAMs. > > > > I'll very grateful if someone could help me. > > > > Thanks a lot. > > > > Arkaitz.Article: 61660
Brian, You are absolutely correct in everything you say*. Please do not bother to reply or acknowledge, as I am not worthy of your attention. Austin *Note: "customer is always right"Article: 61661
I've developed a couple of debuggers that run on Win98 and Win95 that let you look at (and modify) PCI config registers as well as peek and poke locations in the different BAR address spaces. Take a look at: http://www.probo.com/debugger.htm The original version, DBG.EXE, has a built-in Forth interpreter that allows you to write sophisticated test scripts/programs without having to learn how to map memory in the X86 architecture. Unfortunately, Forth is like Pig-Latin to most people, so the newer version of the code has an internal C interpeter to handle test scripts/programs. The newer code is called (surprise) CDBG. The original DBG gets little support or attention at this point. If you use it and find a bug, I may or may not look into the problem. CDBG get more attention from me. I'll probably look at re-produceable bugs that are reported to me. I already know that the C interpreter tends to have occasional problems recovering from syntax errors and accesses to pointers out-of-range. Both tools have been VERY useful in helping me debug PCI cards. We also have Linux and Win2k versions of CDBG, but these aren't for public consumption yet. John Providenza Bassman59a@yahoo.com (Andy Peters) wrote in message news:<9a2c3a75.0310070910.62f902a9@posting.google.com>... > irum4@yahoo.com (irum4) wrote in message news:<bae769a6.0310070210.68f12baa@posting.google.com>... > > H. Peter Anvin <hpa@zytor.com> wrote in message news:<blsls6$n8a$1@cesium.transmeta.com>... > > > Followup to: <bae769a6.0310060635.580b510c@posting.google.com> > > > By author: irum4@yahoo.com (irum4) > > > In newsgroup: comp.arch.fpga > > > > > > > > > > Check through *all* the bits in the configuration space header to make > > > sure you match the specification. > > > > > > -hpa > > Vendor ID & Device ID 0007524d (0x00 Device/Vendor ID) > > Command &Status 02000187 (0x04 Command/Status) > > 04800000 (0x08 Rev ID, Class Code) > > 00008000 (0x0c Cache line, Lat timer, Hdr, BIST) > > 0000bc01 (0x10 BAR0) > > f4400008 (0x14 BAR1) > > 00000000 (0x18 BAR2) > > 00000000 (0x1c BAR3) > > 00000000 (0x20 BAR4) > > 00000000 (0x24 BAR5) > > 00000000 (0x28 Cardbus CIS ptr) > > 091e0000 (0x2c Subsystem/Subvendor ID) > > 00000000 (0x30 Exp ROM base) > > 00000000 (0x34 Cap. Ptr.) > > 00000000 (0x38 reserved) > > 00000103 (0x3c interrupt, grant, lat) > > > Um, > > You've got completely stupid values for BAR0 and BAR1. Go re-read the PCI spec. > > --aArticle: 61662
Hello folks, Found a load of archived posts on this topic. I was wondering what the current thoughts are on what is ultimately faster: (a) dedicated 18x18 multipliers (b) 18x18 pipelined multiplier in slice logic Also, are there any advantages/disadvantages you can think of between the two options other than the following: (1) If all dedicated multipliers are used, you have no choice but to use slice logic (2) Power considerations? Thanks for your time, KenArticle: 61663
The drivers for XP are different than the drivers for 98. If you put 3
boards in and it works how you want it then the boards and the hardware
design work. If you put in more boards and some don't work then you have a
driver problem. I can almost guarantee that you will need a new driver for
XP.
If you need any consulting let me know...
Steve
"irum4" <irum4@yahoo.com> wrote in message
news:bae769a6.0310060635.580b510c@posting.google.com...
> I have developed the PCI-device for which it is necessary 128 bytes of
> ports of input-output, 512 Kb of memory and one interrupt.
> When I install 4 devices simultaneously, BIOS allocates for them
> necessary resources, windows 98 allocates resources only for 3
> devices.
> And Windows XP at all it does not want to be loaded ("Blue screen"
> before installation of drivers).
Article: 61664Andy Peters <Bassman59a@yahoo.com> wrote in message news:9a2c3a75.0310070910.62f902a9@posting.google.com... > > > Check through *all* the bits in the configuration space header to make > > > sure you match the specification. > > > > > > -hpa > > Vendor ID & Device ID 0007524d (0x00 Device/Vendor ID) > > Command &Status 02000187 (0x04 Command/Status) > > 04800000 (0x08 Rev ID, Class Code) > > 00008000 (0x0c Cache line, Lat timer, Hdr, BIST) > > 0000bc01 (0x10 BAR0) > > f4400008 (0x14 BAR1) > Um, > You've got completely stupid values for BAR0 and BAR1. Go re-read the PCI spec. > --a _Are_ these completely stupid if the host has performed the memory mapping configuration? BAR0 is IO space mapped to 0xBC00 BAR1 is memory space which is pre-fetchable from 0xF4400000 to 0xF4800000 ? Nial Stewart ------------------------------------------------ Nial Stewart Developments Ltd FPGA and High Speed Digital Design www.nialstewartdevelopments.co.ukArticle: 61665
There is probably a difference in the net delay for CLK0 and CLK180 which applies a bias to your pos-to-neg and neg-to-pos domain transitions. If you have a poor quality clock with significant jitter, the transitions between those two domains can be marginalized further. Using posedge and negedge of one clock gives you consistent net delay for the single clock reducing the skew in the two time periods. Using the DLL to provide the clock *will* correct for duty cycle unless you tell it otherwise. This reduces the worries of poor duty cycle for the incoming clock. The Xilinx timing analysis *will* include the estimates for the different clock net delays but - until version 6.1 of the tools - did not allow you to account for input jitter. One of the new features in the just-released v6.1 tools is the ability to proviide a jitter spec. At least that's what I've read - I haven't worked with it yet. If your input clock was clean, the tools should have already accounted for everything. Check your clock quality to measure the jitter. What's most important is the spread after 1-3 clock edges, I would imagine, given the delay nature of the DLL which has no VCO. If the clock isn't great and you can measure the spread, check into the jitter constraint with the new tools; you might get better results. And then there's always the initialization issues.... Do you have an explicit reset driving all your registers? My coding style tends to rely on power-up states with explicit INITs used to force the power-up logic where a don't-care will cause problems. When changing the code, registers without the INIT sometimes change power-up polarity leading me to discover they *weren't* don't-care values. Good luck sleuthing your mystery. "John Providenza" <johnp3+nospam@probo.com> wrote in message news:349ef8f4.0310071641.4608fe05@posting.google.com... > I'm working on a design that's using multiple DCMs along > with DDR i/o registers. The main input clock is 500MHz > going into a DCM with the CLKIN_DIVIDE_BY_2 flag set > so it's immediataly cut down to 250MHz. The DCMs used in > the design also have CLKOUT_PHASE_SHIFT=VARIABLE. > > To drive my DDR i/o flops, I'm currently using both the CLK0 and > CLK180 pins (running at 250MHz). > > The original designer flowed the DDR data though the chip using > both clock edges, ie, the incoming "posedge" data went down a > "posedge" data pipeline to flow back out the DDR output. The > incoming "negedge" data went down a "negedge" pipeline. The > original design did NOT use CLK0 and CLK180 for these two > data paths. Instead, the designer used "posedge" and "negedge" > in the Verilog. The major problem comes in the control and > data signals that cross the two domains. Because of the potential > duty cycle degradation, the P&R tools don't achieve timing > closure consistently. > > As an experiment, I changed the design to use CLK0 and CLK180 for > the internal flops. I was: > a) pleased when the P&R timing was better > b) surprised when the design no longer worked. > I figured I screwed up converting the pos/negedge vs CLK0/CLK180 > conversions, so I tripple checked the design and didn't find > anything. I backed up to a older working version, made the changes > again being VERY careful in my conversion. Again, no luck. Timing > number look good, the design doesn't work. > > Is there something odd in the phasing between the the posedges of > CLK0 and CLK180? > > Anyone else run into something like this? > > Thanks, > > John ProvidenzaArticle: 61666
In article <bm1b5h$352$1@dennis.cc.strath.ac.uk>, Ken <aeu96186_MENOWANTSPAM@yahoo.co.uk> wrote: > >Hello folks, > >Found a load of archived posts on this topic. > >I was wondering what the current thoughts are on what is ultimately faster: > >(a) dedicated 18x18 multipliers >(b) 18x18 pipelined multiplier in slice logic > >Also, are there any advantages/disadvantages you can think of between the >two options other than the following: > >(1) >If all dedicated multipliers are used, you have no choice but to use slice >logic >(2) >Power considerations? 3: Use of the BlockRAMs. Since the BlockRAMs and multipliers share interconnect, there are limits on when they can be used simultaneously. 4: Pipelined, throughput-optimized performance. The fixed multipliers are unpipelined or single-stage, a LUT multiplier can be much more finely pipelined (higher thorughput). -- Nicholas C. Weaver nweaver@cs.berkeley.eduArticle: 61667
Kevin Kilzer wrote: > When you write VHDL (or Verilog for that matter), do you visualize a > schematic with wires, gates, flops, latches, muxes, etc., or do you > use some other way of thinking about it? Generally, no. If the function is easily described in gates and FFs, it seems most concise to describe it as a schematic, and then either convert it to VHDL or feed it to the XST tools. For many things, I find that VHDL leads to endless pages of mind-numbing text, where a schematic is just a couple of sheets of easily absorbed signal flow. One place that it was so obvious to use VHDL was a set of 48-bit binary to grey code and grey code to binary translators. With the for loop, these compacted down to about 5 lines of code, each! So, these functions became VHDL symbols on my schematic. But, you HAVE to keep in mind that what you get, in terms of actual logic, is not what you specify in a schematic! The boolean function, from the inputs and the outputs will match, but anything you do to control signal timing in the combinatorial structure will disappear. I needed to delay some signals, and just threw in some extra gates. Of course, this had no effect on the boolean functions from input to output, and so were optimized away. So, finally, I realized I needed to bring signals off-chip, through an external RC, and back in to do what I wanted. If what you are doing is more purely mathematical, such as ALUs, registers, buses, and calculations being performed, then VHDL (or the HDL of your choice) may be vastly more organized than a schematic. JonArticle: 61668
Hi group! Please any one could provide answers to these: 1) Are the dedicated clock pins (GCLKx) of spartan2 [XC2S150, Vccint=2.5V and Vcco=3.3V]also 5V tolerant? If yes, then do we need to select LVTTL for these clock pins also? 2) Can the Xilinx ISE tool meet all pin location constarints with 100%guarantee? or a failure may occur like in case of some other constraints? Is pin locking affected by some other constraints we might be using in the design? Regards RiderArticle: 61669
> > > Hi all i am new in the group, i am a italian student of computer science and > > i have hobbies for electronics, too... so i have using PIC, St6/7 > > microcontroller, etc.. now my dream is develop some circuit with fpga (or > > similar) and VHLD language. I have just a bit studing (only teorically) VHDL > > in my university, but now i would REALLY program some chip for develop some > > simple and medium project. > > I have not money (and i don't want :-) ) to buy some original developing > > system, so i would home build some free "programmer" (in-circuit JTAG ???) > > how i have do in pass for PIC / St6/7 programmers :-) > > > > You'd be better off on comp.arch.fpga, for the actual hardware > questions - I've crossposted to there and set the followups to go > there also. > Ok, now i am here :-)) > Regarding programming hardware, Altera have the Byteblaster schematics > downloadable from their site, in the Byteblaster datasheet. I can;t > recall if Xilinx have similar. Ok thank i have found ByteblasterMV's datasheet (http://www.altera.com/literature/ds/dsbytemv.pdf), is it correctly ? I have found also a PCB and more at http://c.combaret.free.fr/projects.html and i that it can interest at somebody... and i have found a old article "Build your own ByteBlaster" from old mirror of "FreeCore Library" at http://opencollector.org/history/freecore/What%20Altera%20didn't%20tell%20you.htm but i am also interessed to Xilix cpld and fpga so somebody know if exist some free programmer like type for Altera chips ? Thank you very much ALL > > > Thank you very much to all friends, and sorry for my very bad and poor > > english language :-) > > > > It's better than my Italian! ahahahah :-) ciao ciao :-) > > Cheers, > Martin > > -- > martin.j.thompson@trw.com > TRW Conekt, Solihull, UK > http://www.trw.com/conektArticle: 61670
Rider, 1) Answer 11313 which refers you to vtt002.pdf states that IO inputs are 5V tolerant for LVTTL or PCI standard inputs. 2) Sorry that I can not answer the second question (not a tool guru). But I suspect that all constraints are not exclusive, and that they do interact. Austin rider wrote: > Hi group! > > Please any one could provide answers to these: > > 1) Are the dedicated clock pins (GCLKx) of spartan2 [XC2S150, > Vccint=2.5V and Vcco=3.3V]also 5V tolerant? If yes, then do we need to > select LVTTL for these clock pins also? > > 2) Can the Xilinx ISE tool meet all pin location constarints with > 100%guarantee? or a failure may occur like in case of some other > constraints? Is pin locking affected by some other constraints we > might be using in the design? > > Regards > RiderArticle: 61671
If I have a 500MHz input clock feeding into two DCMs in a Virtex-II with the CLKIN_DIVIDE_BY_2 option set on both of them.... The CLK0 output of each of them should be 250MHz, but it seems like they could come up 180 degrees out of phase. Is there any way to have the CLK0 outputs of the two DCMs come up "in phase" without playing tricks with the CLKFB signals between the two of them? Thanks John ProvidenzaArticle: 61672
rider wrote: >Hi group! > >Please any one could provide answers to these: > >1) Are the dedicated clock pins (GCLKx) of spartan2 [XC2S150, >Vccint=2.5V and Vcco=3.3V]also 5V tolerant? If yes, then do we need to >select LVTTL for these clock pins also? > >2) Can the Xilinx ISE tool meet all pin location constarints with >100%guarantee? > I can't make any guarantees, but I have never seen problems routing Spartan2 devices, even with all pins locked. Most customers do lock down their pins before running place and route. > or a failure may occur like in case of some other >constraints? Is pin locking affected by some other constraints we >might be using in the design? > There are 2 areas I can think of that may interract. First would be if you try to use a global clock buffer inside the FPGA and don't constraint the input to the appropriate pin. Second would be if you have really tight timing constraints that are difficult, or impossible to meet based on where the IOs are located. In this case, the design usually routes, but may not meet timing. Steve > > >Regards >Rider > >Article: 61673
Followup to: <3F83932E.16B23BC6@andraka.com>
By author: Ray Andraka <ray@andraka.com>
In newsgroup: comp.arch.fpga
>
> The first method gives you structure but no handles for naming or placing the
> LUTs. The second is one I use for many of my library macros, as it permits
> attachment of an RLOC placement attribute so you can get control over placement.
> It does however result in a large library of small combinatorial functions which
> can become awkward to maintain. The third is generally too hard to use and
> maintain without a good INIT string generation function, however it does not
> require a large library of 2,3 and 4 input functions. It is hardly usable
> without the boolean to INIT function however.
>
Here is a simple Perl script that produces the appropriate LUT bit
pattern for a 4-input LUT given any arbitrary boolean expression
involving "0", "1", "a", "b", "c", "d". The operators are the stanard
C/Perl ~ | ^ & -- the booleanizing operators including ?: and ! should
not be used. The extension to 5-input LUTs should be obvious.
This should be easily tweakable to produce any particular syntax
desired.
Posted mostly as an example.
-hpa
#!/usr/bin/perl
$e = join(' ', @ARGV);
$e =~ s/1/\(\$one\)/g;
$e =~ s/a/\(\$a\)/g;
$e =~ s/b/\(\$b\)/g;
$e =~ s/c/\(\$c\)/g;
$e =~ s/d/\(\$d\)/g;
$one = 0xffff;
$a = 0xaaaa;
$b = 0xcccc;
$c = 0xf0f0;
$d = 0xff00;
printf "%04x\n", eval($e) & $one;
--
<hpa@transmeta.com> at work, <hpa@zytor.com> in private!
If you send me mail in HTML format I will assume it's spam.
"Unix gives you enough rope to shoot yourself in the foot."
Architectures needed: ia64 m68k mips64 ppc ppc64 s390 s390x sh v850 x86-64
Article: 61674Followup to: <3f84344a$0$10982$fa0fcedb@lovejoy.zen.co.uk> By author: "Nial Stewart" <nial@spamno.nialstewart.co.uk> In newsgroup: comp.arch.fpga > > _Are_ these completely stupid if the host has performed the > memory mapping configuration? > > BAR0 is IO space mapped to 0xBC00 > > BAR1 is memory space which is pre-fetchable from > 0xF4400000 to 0xF4800000 > It's actually impossible to know without knowing what the powerup values are and which bits are read/write. Just posting a snapshot in time is pretty useless -- you need to go and check the proper semantics of all your bits. -hpa -- <hpa@transmeta.com> at work, <hpa@zytor.com> in private! If you send me mail in HTML format I will assume it's spam. "Unix gives you enough rope to shoot yourself in the foot." Architectures needed: ia64 m68k mips64 ppc ppc64 s390 s390x sh v850 x86-64
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