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Hi, Does Xilinx XST 6.x support RTL-synthesis of Verilog-2001? This document http://toolbox.xilinx.com/docsan/xilinx5/data/docs/xst/xst0083_11.html shows that the older version, XST 5.x, has partial support for Verilog 2001. I was wondering if the support is better in the newer version of ISE. In particular, I'm interested in knowing if 'generate' works, and whether arrays of instances work. The latter was actually added to the language in 1995, but XST 5.x doesn't seem to support it. Regards, Allan.Article: 61201
Uwe Bonnes wrote: > Aart van Beuzekom <aart@westcontrol.dontspamme.com> wrote: > : Uwe Bonnes wrote: > > :> Aart van Beuzekom <aart@westcontrol.dontspamme.com> wrote: > ... > :> It has been discussed before. Try www.deja.com to search this group for old > :> answers. > :> > :> Bye > > : Hi Uwe, > > : Thanks for four response. Fortunately, I checked this newsgroup's > : archive before posting. The problem is that it isn't exactly pattern > : matching I want, but counting the number of errors (at the other end of > : a poor communication link) in a bitstream, compared to an expected > : pattern. Something that for example can be used to find a kind of > > The second hit on deja in a search for "fpga counting ones" gives: > > >>Re: Counting the number of ones present ... >>comp.lang.verilog - 8 Jul 2002 by John_H - View Thread (10 articles) > > > http://groups.google.com/groups?hl=en&lr=&ie=UTF-8&oe=UTF-8&threadm=3D29BF6F.C2CA3906%40mail.com&rnum=2&prev=/groups%3Fq%3Dfpga%2Bcounting%2Bones%26hl%3Den%26lr%3D%26ie%3DUTF-8%26oe%3DUTF-8%26start%3D0%26sa%3DN > > The 6th hit is > Re: Count 1's algorithm... > ... To count 16 ones you would need 5 CLBs and have one ... you have to do it and how many > bits you are counting. ... with a fanin and fanout of 2. The FPGA LUTs generally ... > comp.arch.fpga - 4 Feb 2000 by Dragon - View Thread (11 articles) > > Hope this helps > Hi Uwe, OK, I didn't even know that newsgroup existed, I'll check it. AartArticle: 61202
Aart van Beuzekom wrote: > Uwe Bonnes wrote: > >> Aart van Beuzekom <aart@westcontrol.dontspamme.com> wrote: >> : Uwe Bonnes wrote: >> >> :> Aart van Beuzekom <aart@westcontrol.dontspamme.com> wrote: >> ... >> :> It has been discussed before. Try www.deja.com to search this group >> for old >> :> answers. >> :> :> Bye >> >> : Hi Uwe, >> >> : Thanks for four response. Fortunately, I checked this newsgroup's : >> archive before posting. The problem is that it isn't exactly pattern : >> matching I want, but counting the number of errors (at the other end >> of : a poor communication link) in a bitstream, compared to an >> expected : pattern. Something that for example can be used to find a >> kind of >> The second hit on deja in a search for "fpga counting ones" gives: >> >> >>> Re: Counting the number of ones present ... >>> comp.lang.verilog - 8 Jul 2002 by John_H - View Thread (10 articles) >> >> >> >> http://groups.google.com/groups?hl=en&lr=&ie=UTF-8&oe=UTF-8&threadm=3D29BF6F.C2CA3906%40mail.com&rnum=2&prev=/groups%3Fq%3Dfpga%2Bcounting%2Bones%26hl%3Den%26lr%3D%26ie%3DUTF-8%26oe%3DUTF-8%26start%3D0%26sa%3DN >> >> >> The 6th hit is >> Re: Count 1's algorithm... >> ... To count 16 ones you would need 5 CLBs and have one ... you have >> to do it and how many >> bits you are counting. ... with a fanin and fanout of 2. The FPGA LUTs >> generally ... >> comp.arch.fpga - 4 Feb 2000 by Dragon - View Thread (11 articles) >> >> Hope this helps >> > Hi Uwe, > > OK, I didn't even know that newsgroup existed, I'll check it. > > Aart > Thanks to all for the reponse! AartArticle: 61203
"John_H" <johnhandwork@mail.com> wrote in message news:<L5Zcb.13$Cr.9485@news-west.eli.net>...
> If your syntax does work, you can see the pullup in the FPGA Editor for your
> Placed & Routed design. Find one of the IOBs, double click on the IOB and
> you'll get a pop-up for just that cell. Included are checkboxes for some of
> the IOB options including logic standard, fast/slow, and pullup. If the
> pullup isn't indicated *there* it isn't in your finalized design.
What is "FPGA Editor"? I tried with Floorplanner ("View/Edit Placed
Design") but if I double click the iob no pupup is opened.
Which tool I need to use?
thanks
Article: 61204Hi, is there anyone out there who has some experience with the lcd module of the v2p4 memec board with virtex 2 pro fpga on it ? I am trying to get the lcd working by writing only c++, no vhdl. I am using the opb_gpio pins to control the lcd module. I have another design where the lcd module works fine with vhdl. When I measure the voltage of the pins on the lcd module of the vhdl design and compare them with the voltage of the lcd module of the c++ design, the values are exactely the same. Except that the lcd module with the vdhl works and the c++ design doesn't. TomArticle: 61205
Hello > I have found many information about file formats (MCS,TEK,EXO,..). But I want a file which >contains only the pure bitstream which I can store in my flash and send bytewise to the FPGA >during configuration. > > Which tool must I use to get from the *.bit file such a file? In the meantime I found what I'm looking for. It was an option from BitGen. Thanks Reiner Abl _____________________________________________________________________ Reiner Abl IQ-Mobil GmbH 82515 Wolfratshausen www.iqmobil.de GermanyArticle: 61206
Stephen Williams <spamtrap@icarus.com> writes: > Petter Gustad wrote: > > "Martin Euredjian" <0_0_0_0_@pacbell.net> writes: > > > >>Is there a way to have more than one computer work on compiling a > >>design? > > The Solaris version of par (Xilinx place and route tool) can do > > multiple iterations on multiple hosts (using the -m option to par). > > Hey, the Linux versionhas that too. I can use that to make an > extra process on the local machine in order to put a dual processor > to use? I'm glad to hear that this is supported in the Linux version. Unfortunately I haven't received mine yet. The trick (at least on the Solaris version) is to write the same host name twice (or whatever number of procesesses you want to run) in the host file you pass to PaR, but with a different combination of upper and lower case letters: zener zeneR will then create two processes on the host zener. Petter -- A: Because it messes up the order in which people normally read text. Q: Why is top-posting such a bad thing? A: Top-posting. Q: What is the most annoying thing on usenet and in e-mail?Article: 61207
Hello, has anybody ever used the configuration clause in designs synthesized with XST? I have a top-module that hides another moduleX (with a component module_component) that contains a clause like for all : module_component use entity work.module_1(implementation); in the declarative part of the architecture. Module_component implements the functionality of moduleX. After synthesizing module_1 ... module_n the synthesis of top-module generates a black box for moduleX. When I change the clause to use another module_n for module_component XST doesn't recognize that change. (I run the incremental design flow where changes are indicated by a refresh of the design in low level synthesis) Any suggestions are appreciated. Thanks in advance. ChristianArticle: 61208
is there a nallatech ballynuey driver for win2k/ winxp ?Article: 61209
> -------------------- > > > Without seeing your code it is not possible to make an exact diagnosis > > (maybe I couldn't even if I did see it), but I do have suggestions. > > Any signal that is an input to the FPGA synchronous logic should be > > internally synchronized with the logic's clock using 2 d flip-flops. > > The bus data need not be synchronized in this manner if the transfer > > logic (handshake) is synchronized. The read operation should have > > some sort of handshake to ensure that the output data is stable before > > it is read and that the FPGA logic "knows" when new data is requested. > > Does PCI protocol involve a handshake? If so, have you implemented > > it on the FPGA side? > > > > A typical handshake would be: The reader asserts data_request; the > > FPGA logic puts the data on the bus and asserts data_ready. The > > reader sees data_ready, reads the data, and unasserts data_request > > (this lets the FPGA logic know that the data has been read and it > > unasserts data_ready and). There are a number of variations on this, > > but without some sort of handshake it is quite likely that there will > > be missed data, multiple reads of the same data, etc. > > > > Charles > ------------------------------------------------------------------- > Isacc Msg: Here is the Case Statement which I am using, in this you will see > different signal which I am using in differnt process which I haven't > included . > > > process2: process (CLK_2X) > begin > if RISING_EDGE(CLK_2X) then > state <= next_state; > else > Null; > end if; > end process process1; > process2 : process > (state,LOCKED,CLK_2X,SR_ADDR_IO,SR_DATA_IO,SR_IRD,SR_IWR,SR_IVCS_V3) > begin > case state is > when s1 => > paritycheck <= '0'; > k <= 0; > next_state <= s2; > when s2 => > if LOCKED = '1' then > -- LED_V3 <= LED_V3_int; > STAT_V3 <= STAT_V3_int; > -- Inputs > -- SR_ADDR_IO_int <= SR_ADDR_IO; > -- SR_DATA_IO_int <= SR_DATA_IO; > -- SR_IRD_int <= SR_IRD; > -- SR_IWR_int <= SR_IWR; > SR_IVCS_V3_int <= SR_IVCS_V3; > next_state <= s3; else > Null; > end if; > > when s3 => > if SR_IVCS_V3 = '0' then > SR_DATA_IO <= "ZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZ"; > if SR_IWR = '0' then > if SR_ADDR_IO = "000000" then > channelbit1 <= SR_DATA_IO(2 downto 0) ; > next_state <= s32; > else > next_state <= s3; > end if ; > else > Null; > end if ; > else > Null; > end if; > when s32 => > if SR_IVCS_V3 = '0' then > SR_DATA_IO <= "ZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZ"; > if SR_IWR = '0' then > if SR_ADDR_IO = "000001" then > channelbit2 <= SR_DATA_IO(2 downto 0) ; > next_state <= s33; > else > next_state <= s32; > end if ; > else > Null; > end if ; > else > Null; > end if; > when s33 => > if SR_IVCS_V3 = '0' then > SR_DATA_IO <= "ZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZ"; > if SR_IWR = '0' then > if SR_ADDR_IO = "000010" then > channelbit3 <= SR_DATA_IO(2 downto 0) ; > next_state <= s34; > else > next_state <= s33; > end if ; > else > Null; > end if ; > else > Null; > end if; > when s34 => > if SR_IVCS_V3 = '0' then > SR_DATA_IO <= "ZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZ"; > if SR_IWR = '0' then > if SR_ADDR_IO = "000011" then > channelbit4 <= SR_DATA_IO(2 downto 0) ; > next_state <= s35; > else > next_state <= s34; > end if ; > else > Null; > end if ; > else > Null; > end if; > > when s35 => > if SR_IVCS_V3 = '0' then > SR_DATA_IO <= "ZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZ"; > if SR_IWR = '0' then > if SR_ADDR_IO <= "000100" then > channelbit5 <= SR_DATA_IO(2 downto 0) ; > next_state <= s36; > else > next_state <= s35; > end if ; > else > Null; > end if ; > else > Null; > end if; > when s36 => > if SR_IVCS_V3 = '0' then > SR_DATA_IO <= "ZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZ"; > if SR_IWR = '0' then > if SR_ADDR_IO = "000101" then > channelbit6 <= SR_DATA_IO(2 downto 0) ; > next_state <= s37; > else > next_state <= s36; > end if ; > else > Null; > end if ; > else > Null; > end if; > > when s37 => > if SR_IVCS_V3 = '0' then > SR_DATA_IO <= "ZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZ"; > if SR_IWR = '0' then > if SR_ADDR_IO = "000110" then > channelbit7 <= SR_DATA_IO(2 downto 0) ; > next_state <= s38; > else > next_state <= s37; > end if ; > else > Null; > end if ; > else > Null; > end if; > when s38 => > if SR_IVCS_V3 = '0' then > SR_DATA_IO <= "ZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZ"; > if SR_IWR = '0' then > if SR_ADDR_IO = "000111" then > channelbit8 <= SR_DATA_IO(2 downto 0) ; > next_state <= s39; > else > next_state <= s38; > end if ; > else > Null; > end if ; > else > Null; > end if; > > when s39 => > if SR_IVCS_V3 = '0' then > SR_DATA_IO <= "ZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZ"; > if SR_IWR = '0' then > if SR_ADDR_IO = "001000" then > channelbit9 <= SR_DATA_IO(2 downto 0) ; > next_state <= s310; > else > next_state <= s39; > end if ; > else > Null; > end if ; > else > Null; > end if; > when s310 => > > if SR_IVCS_V3 = '0' then > SR_DATA_IO <= "ZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZ"; > if SR_IWR = '0' then > if SR_ADDR_IO = "001001" then > channelbit10 <= SR_DATA_IO(2 downto 0) ; > next_state <= s311; > else > next_state <= s310; > end if ; > else > Null; > end if ; > else > Null; > end if; > when s311 => > if SR_IVCS_V3 = '0' then > SR_DATA_IO <= "ZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZ"; > if SR_IWR = '0' then > if SR_ADDR_IO = "001010" then > channelbit11 <= SR_DATA_IO(2 downto 0) ; > next_state <= s312; > else > next_state <= s311; > end if ; > else > Null; > end if ; > else > Null; > end if ; > when s312 => > if SR_IVCS_V3 = '0' then > SR_DATA_IO <= "ZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZ"; > if SR_IWR = '0' then > if SR_ADDR_IO = "001011" then > channelbit12 <= SR_DATA_IO(2 downto 0) ; > LED_V3(2 downto 0) <= channelbit11; > next_state <= s4; > else > next_state <= s312; > end if ; > else > Null; > end if ; > else > Null; > end if; > > when s4 => > k <= k + 1; > next_state <= s5; > when s5 => > if remainder = 0 then > k <= 0; > next_state <= s6 ; > paritycheck <= '1'; > else > next_state <= s4 ; > k<= k+1; > end if ; > when s6 => > if SR_IVCS_V3 = '0' then > if SR_IRD = '0' then > -- if remainder = 0 then > if SR_ADDR_IO = "001100" then > SR_DATA_IO (11 downto 0)<= eb_hat_bits (0 to 11); > SR_DATA_IO (31 downto 12) <= "00000000000000000000"; > elsif SR_ADDR_IO = "001101" then > next_state <= s1; > end if; > -- end if; > else > Null; > end if; > else > Null; > end if ; > when others => > Null; > end case; > end process process2;Article: 61210
"SneakerNet" <nospam@nospam.org> wrote in message news:HI2eb.162954$JA5.4020112@news.xtra.co.nz... > Hi Guys > > I know someone of you have helped me in my replies regarding USB > Implementation before. > I downloaded the USB Core (referred to as the Japanese version). The beauty > of this core is that no hardware is required. Just need to connect the D+ > and D- of the USB cable to pins of the FPGA. > > The facts.. > I changed the code around so that it has a altera pll running and producing > a 48Mhz clock for the usb. > I connected some of the output pins to the leds to see what's going on. > I uploaded the program and connected the usb cable to the pins and to the PC > (and added some circuitry like 3 extra resistors). > and Behold, the program on the FPGA actually does something. I know it's > working because when i connect/disconnect the usb calbe, the lights on fpga > change their pattern for a small amount of time.. > > However I can't test the actual communication. The reason being, when I > connect the usb cable to the PC, the PC recognizes a new USB device is > attached (as win2k shows in the system try all the usb devices.), however is > unrcognised as VALID drivers are not installed. > > What I need is some help/tips on how i can install a driver for this > product. The fpga has been configured so that it recognises a vendor ID of > C91 and product ID of 2001. I have tried playing around with .inf files, but > win2k rejects all of them and uses the standard c:\winnt\inf\usb.inf file. > > I'm so close to getting this thing to work. > > Pls help/advice > Regards > > Try http://www.jungo.com/products.html#driver_tools They have a demo version that looks really easy to make drivers. I played with it but not on a real device. Let us know if it works! -ColinArticle: 61211
prashantj@usa.net (Prashant) wrote in message news:<ea62e09.0309271630.62d832fe@posting.google.com>...
> Hi,
>
> I'm trying to implement a bidirectional bus in my code. (VHDL,
> APEX20K1500E). But I'm having some trouble which brought me to ask the
> question :
>
> How do I specify the direction signal while using a bidirectional bus
> ? I dont find myself setting any enable signals when using the
> bidirectional bus. I would appreciate it if someone could explain how
> this works.
>
> Thanks,
> Prashant
Hi prashant,
All that you should know when the paricular pin is to act as input
& when as output.The use a control signal like "oe" which i have in my
following code .
Here "sda" is my bidirectional pin.
Intenally I copy it to signal "out_sda" & use.While driving the pin
"sda" i copy "int_sda" to "sda".this control is determined by the
signal "oe".
process(oe,sda)
begin
if (oe = '1') then
out_sda <= sda;
else
out_sda <= '0';
end if;
end process;
process(oe,int_sda)
begin
if (oe = '0') then
sda <= int_sda;
else
sda <= 'Z';
end if;
end process;
However the most important thing is there must not be a open loop
between "int_sda" & "out_sda" ie.,in electrical terms there must be a
closed loop for this to work.
Bye
Article: 61212Kevin Kilzer <kkilzer.remove.this@mindspring.com> wrote in message news:<dh2invss3jbj7j0ovr8n89urk7or73lh5b@4ax.com>... > On Tue, 30 Sep 2003 03:13:34 -0000, hmurray@suespammers.org (Hal > Murray) wrote: > > >>Is there any way to estimate the bit error rate of a data bus that > >>passes through a Xilinx FPGA? I have input gates, the block RAM, and > >>output gates involved in the system, and I would like to predict the > >>error rate of data passing through. > <snip> > >If your design is clean, the error rate from everything short of > >cosmic rays should be 0. Or at least low enough so that it > >is very very hard to measure. > > > >Note that "clean" includes the logic and power supply and SI > >on the input and output sides. > > Then why do DRAM memory systems include a CRC or parity bit? > Certainly there is some non-zero probability that a latch will miss or > a gate will experience a random noise spike? > > If what you say is true, the BER of a disk drive will be entirely the > fault of a noisy head, and not the deserializer, cache or bus drivers? Considering that you specificly mentioned "input gates, block RAM, and output gates" in your original posting, Hal's response was correct. Now, if you'd actually mentioned DRAM and disk drives, I'm sure Hal's response would have been different. MarcArticle: 61213
You also need the Sun virtual machine plugin for your web browser. I had this exact problem when I installed 6.1 and I also had the Runtime environment, however I had to also download and install the virtual machine plugin for my web browser before the help would work. Regards, James "MM" <mbmsv@yahoo.com> wrote in message news:blb0n2$a58mq$1@ID-204311.news.uni-berlin.de... > I have just installed Webpack 6.1 on an XP system from the full 188MB > installation and applied the service pack 1. Installation went smooth, but > the help doesn't work. When I click on "ISE Help Contents" IE opens but with > its left pane empty, so I can't browse. It seems that something is wrong > with Java and the Xilinx knowledge base in fact points to this issue, > however I have the Sun Java Runtime Environment installed as recommended. > > That's not all however. The Online documentation (pdf) doesn't open at all! > I compared this installation with ISE5.2 and it seems that pdf files are > completely missing! Same thing can be said about the tutorials. They are > missing too! > > Does anyone know what is going on here? Is it supposed to be this way? > > Thanks, > /Mikhail > >Article: 61214
"James Williams" <james@williams-eng.com> wrote in message news:blc1lo$81o9$1@news3.infoave.net... > You also need the Sun virtual machine plugin for your web browser. > > I had this exact problem when I installed 6.1 and I also had the Runtime > environment, however I had to also download and install the virtual machine > plugin for my web browser before the help would work. I believe I do have the plugin, but it still doesn't work... Maybe I have a wrong plugin?.. Do you remember where you got it from? And what about the pdf part and the tutorials? Do you have them working? Thanks, /MikhailArticle: 61215
I would like to know which logic analyzers others are using in the industry. What make and model logic analyzer do you use and what are your likes / dislikes about it? Is anyone using an analyzer not made by Agilent or Tektronix, and are you happy with it? I am specifically looking at stand alone (or host PC based) type analyzers and not the type that are cores like Xilinx's ChipScope (I am fully aware of the benefits that ChipScope provides). Some of the other features that I am looking at are timing / state analysis, complex triggering (on patterns, etc), LVPECL and TTL levels, clock rates of 200MHz, high memory depth (128K or more), portability, user friendly GUI, data export capabilities, etc. Is there equipment (manufacturer) that I need to avoid? Thanks for your help! ThomArticle: 61216
I got the VM from sun. My pdf's will open without a problem. Go to sun and look for the Virtual machine plugin for IE or Netscape. Regards, James "MM" <mbmsv@yahoo.com> wrote in message news:blc2q3$ajice$1@ID-204311.news.uni-berlin.de... > "James Williams" <james@williams-eng.com> wrote in message > news:blc1lo$81o9$1@news3.infoave.net... > > You also need the Sun virtual machine plugin for your web browser. > > > > I had this exact problem when I installed 6.1 and I also had the Runtime > > environment, however I had to also download and install the virtual > machine > > plugin for my web browser before the help would work. > > I believe I do have the plugin, but it still doesn't work... Maybe I have a > wrong plugin?.. Do you remember where you got it from? And what about the > pdf part and the tutorials? Do you have them working? > > Thanks, > /Mikhail > >Article: 61217
Kevin, If the design has the proper amount of timing slack, and the clock for the design has well behaved jitter, then the error rate is 0. If there is inadequate slack in the timing, and the clock jitter is unbounded, then the error rate is non-zero. At some point, the error rate becomes so small that other things are likely to occur before an error is noticed/logged/reported. Like a power loss. Or a circuit failure somewhere (not in the FPGA). Jitter is often modeled with gaussian distributions, but actual oscillators do not have infinite energy, so they don't actually have unbounded "tails" where the jitter value keeps increasing indefinitely as the probability decreases (true random jitter). Bit errors also almost never occur at a rate, but rather occur in clumps, or bursts, and are therefore not random at all. A channel with dribbling bit errors is broken, and should get fixed or have error correction added on top of it. Check out the articles on the tech Xclusives pages on jitter, timing, and slack. Soft errors from cosmic rays are well understood (at least by us), so you can also take these into account (if an error every ~1000 years is important in your application - which it is for many today). Check out the article on this on the Xillinx website: "1000 Years Between Single Event Upsets" on the tech Xclusives pages. By the way, we recently put the 90 nm Spartan 3 in the neutron beam, and we are gratified (and delighted) that it has ~30% smaller cross section than the 150 nm technology (ie it will be upset less frequently!). (Presented at MAPLD this last month. For a copy of the presentation, contact your FAE.) Austin Kevin Kilzer wrote: > Is there any way to estimate the bit error rate of a data bus that > passes through a Xilinx FPGA? I have input gates, the block RAM, and > output gates involved in the system, and I would like to predict the > error rate of data passing through. > > KevinArticle: 61218
Xilinx ISE - the not-free version of the tools - has the FPGA Editor, listed
inter the "Place & Route" section of the design implementation as "View/Edit
Routed Desing (FPGA Editor)."
I hear WebPack doesn't have this tool which gives the low-level visibility
an engineer might want in order to understand how the tools are implementing
the design.
The "Pad Report" is the third item on my Place & Route list.
Double-clicking there produced a file that's ready to import to a
spreadsheet. It's not terribly readable in the ISE window (includes
delimiters, not spaces) but does include Pullup/PullDown information.
"Max" <cialdi@firenze.net> wrote in message
news:8e077568.0309292328.40ee6482@posting.google.com...
> "John_H" <johnhandwork@mail.com> wrote in message
news:<L5Zcb.13$Cr.9485@news-west.eli.net>...
>
> > If your syntax does work, you can see the pullup in the FPGA Editor for
your
> > Placed & Routed design. Find one of the IOBs, double click on the IOB
and
> > you'll get a pop-up for just that cell. Included are checkboxes for
some of
> > the IOB options including logic standard, fast/slow, and pullup. If the
> > pullup isn't indicated *there* it isn't in your finalized design.
> What is "FPGA Editor"? I tried with Floorplanner ("View/Edit Placed
> Design") but if I double click the iob no pupup is opened.
> Which tool I need to use?
>
> thanks
Article: 61220
Hi folks,
Been checking the archives for an answer to this one without much luck...
What does doubling the clock rate of a design on an FPGA do to the power
consumption (in general - I am just looking for a rule of thumb here..)?
If you need some assumptions to answer:
Assume:
critical path is a 25-bit carry chain in an adder.
a highly pipelined design occupying most of the device.
Not sure what else would be useful assumptions-wise - please feel free to
add your own! :-)
Also, if I double my clock rate and reduce my hardware by half due to
sharing hardware over 2 clock cycles, obviously the reduced hardware will
reduce power consumotion and the increased clock will increase power
consumption, question is, which is the overriding factor? (the clock I
guess?).
Again, just looking for a rule of thumb.
Cheers,
Ken
Article: 61221Thank for replying to my post. To answer your first question I want to mate an optical or wireless communication interface to the Celoxica RC100 boards. Set up so far is as follows: Camera -> Celoxica Board -> Ribbon Cable -> Celoxica Board -> Monitor The Ribbon cable is connected to the Celoxica boards using the expansion header on the celoxica boards. This expansion header allows digital communition in and out of the FPGA on the Celoxica board. The data on the ribbon cable ha a bus width of 32 (i.e. is 32 bits wide) and and the data changes every 100 ns (10 MHz). All I want to do is remove the ribbon cable and replace it with an optical or wireless communication system (preferably a wireless system). So system would be: Camera -> Celoxica Board -> Wireless transmitter -> Receiver -> Celoxica board -> Monitor One board and the transmitter would be at one end of a room, the other board and receiver at other end of room. The transmission range is to be small e.g. max of 5-8 meters. The data rate is fairly high so not sure if a wireless system would be up to the task. Hope this has clarified my situation. "Patrick MacGregor" <patrickmacgregor@comcast.net> wrote in message news:<Vc6dncJWbLocWOWiXTWJhg@comcast.com>... > Can you explain a bit more? Are you planning on looking to replace the > Celoxica boards with something else, or do you want to mate the Celoxica > boards to some optical or wireless transmission system? If so, how would > you want to transfer data to/from the optical or wireless interface boards? > > > "Patrick Twomey" <patrickt@rennes.ucc.ie> wrote in message > news:1d183274.0309290336.5aa14a7c@posting.google.com... > > I am trying to connect two FPGA development boards together. The boards in > > question are two Celoxica RC100 development boards. Video in is from an > analog > > camera. The video data is converted to digital and stored on > > SRAM. There is an expansion header for inter-connectivity. On the other > board > > video out to a monitor occurs after reading data from the SRAM on this > board. > > Have connected to two boards via a ribbon cable connected to the expansion > > headers. Want to replace this cable with wireless or optical transmission. > Is > > there any development boards available for this. The pixel clock is 10 MHz > and > > there are at least 16 bits per pixel (32 aftere error correction > encoding). > > Access to a 80 MHz on board clock is > > available. Any help would be much appreciated.Article: 61222
In article <blc9hh$p70$1@dennis.cc.strath.ac.uk>, Ken <aeu96186_MENOWANTSPAM@yahoo.co.uk> wrote: > >Hi folks, > >Been checking the archives for an answer to this one without much luck... > >What does doubling the clock rate of a design on an FPGA do to the power >consumption (in general - I am just looking for a rule of thumb here..)? Back o the envelope.. Dynamic Power = CV^2F. Static Power = Constant... Since you aren't scaling the voltage, if you double the frequency, what happens to the dynamic power? And given that the leaking (static) power isn't half- the power dissipation yet. >Also, if I double my clock rate and reduce my hardware by half due to >sharing hardware over 2 clock cycles, obviously the reduced hardware will >reduce power consumotion and the increased clock will increase power >consumption, question is, which is the overriding factor? (the clock I >guess?). Static vs Dynamic. Also, logic which changes burns power, so such interleaving will probably reduce bit-history effects, upping power. -- Nicholas C. Weaver nweaver@cs.berkeley.eduArticle: 61223
I Have used the modular design with handel C to create full and partial bitstreams for the Celoxiaca RC1000 and it works. Unfortunately i dont know how to download my designs on the Celoxica board. Does anyone have experience on using partial bitstream on the RC1000 board with Virtex 2000 E ? In the past i used JBits to download partial bitstreams on the RC1000 with Virtex 1000. Since JBits does not support Virtex E, i will like to know which functions to use and how to use them. I will highly appreciate it, if i could have a small example. eople told me at celoxica to use their SetSelectMapChanel funtion. But nobody could tell me there how to use this function. I implemented a function to read my bitstream in a buffer and then to downlod the content of the buffer using DMA functions together with the SetSelectMapChannel. Now i have a new problem: I'm able to downlod a first bistream. Whenever i try to download a new bitstream, the first remain inside and i cannot reconfigure the device with a new bitstream. Can someone knows where the problem could be? Kind Regards Christophe BobdaArticle: 61224
Hi all: I was using a Digilent 2DE + DIO1 (Spartan2E) with the Free ISE WebPack 5.2, with no problems. I have just downloaded the new WebPack 6.1 and everything runs well until iMPACT tries to automatically configure the BoundaryScan chain. The Digilent D2E is programmed thru a parallel cable connected to LPT1: and worked OK under WebPack 5.2 Comparing 5.2 with 6.1, we have found that 5.2 said --------------------------------------------------- Connecting to cable (Parallel Port - LPT1). Checking cable driver. Driver windrvr.sys version = 5.0.5.1. LPT base address = 0378h. ... --------------------------------------------------- but 6.1 says --------------------------------------------------- LPT base address = 0B78h. --------------------------------------------------- and finally says "communications with the cable could not be stablished. Check cable and power" Has anybody found the same problem and any workaround? Thanks in advance -javier
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