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The massive parallelism is considered as the main advantage of of FPGAs. Meantime, the bottleneck of modern systems is a memory performance. How do I benefit in e.g. image processing using wide low speed FPGA over hi-speed running CPU when image is located in SRAM? Today more and more FPGAs are equipped with embedded RAM. How can FPGA benefit from the concurrent processing having to serialize memory access?Article: 62101
In article <3f92b7c1$1_1@news.estpak.ee>, Valentin Tihomirov <valentin@abelectron.com> wrote: >The massive parallelism is considered as the main advantage of of FPGAs. >Meantime, the bottleneck of modern systems is a memory performance. How do I >benefit in e.g. image processing using wide low speed FPGA over hi-speed >running CPU when image is located in SRAM? Today more and more FPGAs are >equipped with embedded RAM. How can FPGA benefit from the concurrent >processing having to serialize memory access? What do you mean by "memory performance?" Latency for sequential access? Latency for parallel accesses? Throughput for a single stream? THroughput for multiple streams sharing memory? THroughput for multiple streams from independant memories? -- Nicholas C. Weaver nweaver@cs.berkeley.eduArticle: 62102
Hey Lorenzo, It is incredible that in response to an inquiry about technical workshops you found it appropriate to insult some countries (in fact whole regions!; even continents!!), and state little else. Way to approach the problem ! Ljubisa Bajic ATI Technologies --- My opinions do not represent those of my employers --- "Lorenzo Lutti" <lorenzo.lutti@DOHtiscalinet.it> wrote in message news:<O6Hcb.347818$lK4.11111238@twister1.libero.it>... > "Valeria Dal Monte" <aaa@bbb.it> ha scritto nel messaggio > news:9qkbb.335067$Ny5.10649409@twister2.libero.it... > > > Some days ago Xilinx did workshops in many european > > states. > > Why Italy was excluded? > > Well, if you think that some multinationals put Italy into their SEMEA > division (South Europe, Middle Europe and Africa), you can guess. We are > considered just like Bulgaria or Libia and, with all the respect for > these countries, I think we could deserve a little more.Article: 62103
> Does anybody familiar with a development board containing an FPGA with Sun picojava. > > 10x You can use any board that comes with a large FPGA. Have you tried to synthesize the picoJava? I would be interested how large it will be (when configured for lowest arrea). Martin ---------------------------------------------- JOP - a Java Processor core for FPGAs: http://www.jopdesign.com/Article: 62104
"Ljubisa Bajic" <eternal_nan@yahoo.com> ha scritto nel messaggio news:9b0afb2c.0310190955.aa5708d@posting.google.com... > It is incredible that in response to an inquiry about > technical workshops you found it appropriate to insult > some countries (in fact whole regions!; even > continents!!), Insult?! I have simply said that some multinationals consider Italy (from a *business* point of view) just like countries that are objectively far less industrialized than us. Italy is in the G8, Libia and Poland aren't even in the G20. When I say we "deserve" better, I mean that we could have a lot more technological resources to invest in FPGA world. This is a fact, not an offense. I didn't mean to insult anyone! If I did so, I apologize to whoever could have been offended. Probably the guilt is my bad english, I'm not able to express all my thoughts exactly. :) -- LorenzoArticle: 62105
Georg Acher <acher@in.tum.de> wrote: : In article <bmp871$22k$1@news.storm.ca>, : "jakab tanko" <jtanko@ics-ltd.com> writes: : |> Anybody having similar problems? : Me too. A design for a 2S200 which needs to run at 130MHz (5.1 achieved ~133MHz : without floorplaning) is slowed down with 6.1 to about 110MHz. "High effort" etc. : does not help at all. Looking at the timinganalyzer output, it seems that MAP : ignores the first carry chain block and uses regular logic and routing instead, : thus stealing about 2ns :-( Perhaps send your code to Xilinx for inclusion in their regression test suite. However after the VLGINCDIR happening ( it was broken until 5.2 and is broken again in 6.1) I wonder if there is any... Bye -- Uwe Bonnes bon@elektron.ikp.physik.tu-darmstadt.de Institut fuer Kernphysik Schlossgartenstrasse 9 64289 Darmstadt --------- Tel. 06151 162516 -------- Fax. 06151 164321 ----------Article: 62106
I'm a student working an a Altera EPXA1F484C1 FPGA, and I'm having some
problems I hope someone can help me with.
1. Is there a way to tell Quartus that the project I'm compiling is ment as
a "internal" building block, meaning that the pins isn't actual device pins,
but "internal pins"? I'm wondering since I have several "internal blocks"
with 128 bits in and out, and Quartus stops my compilings complaining that
the device I'm compiling for has to few pins for my design.
2. I get stuck-at errors...and I have no idea why. I get this warning:
"Warning: No clock transition on AESRoundSP-
2:inst|lpm_dff0:inst5|lpm_ff:lpm_ff_component|dffs[127] register"
And this continues for all 128 flipflops. But they are clocked by the
"master clock". I have not created a clock signal, but the clock is named
clk, and then Quartus should assume that the signal is a clock, right?
Anyway, Quartus compiles my design without errors, but the summary tells me
that I'm not using any LEs or any memory bits...
The AESRoundSP-2 is a building block in a larger design, but does not
compile "on its own" because it uses too many pins and memory bits. Can this
cause the weird error in (2)?
Article: 62107Hi Arkaitz, arkaitz wrote: > > Does anybody know why? Am I doing something wrong? Have you actually connected the OPB to the instruction side of the microblaze, as well as the data side...? Since you can verify the contents of the external ram (as data reads), that's the only possible explanation I can think of... In MHS, it should look like this (in microblaze section): BUS_INTERFACE DOPB = d_opb_v20 # or whatever the bus instance is called BUS_INTERFACE IOPB = d_opb_v20 # same bus, EDK will create an arbiter Regards, JohnArticle: 62108
There is a way to tell Quartus that certain pins are not actual pins, and they should not count towards the I/O count. You do that my marking them with the Assignment called Virtual Pins. Follow these steps. 1. Compile the design through Analysis and Synthesis. 2. Open the Assignment Editor. 3. Select the Logic Options Button on the top. 4. Enter the pin name you want under Destination Name. 5. Select the Logic Option under Option. 5. Set the Value to On. When you compile the design it should reduce the number of primary inputs/outputs by the number of virtual pins. ---------------------------------------------------------------------------- --------------------------------- Quartus can infer clocks by analyzing signals which directly drive the clock input of registers. However to make a frequency assignment to a clock signal you first need to define Step A. A New Clock Setting using the Assignment->Timing Settings->Clocks->New Clock Settings. The next step is to assign this clock setting to a clock signal. You do this by: Step B: 1. Compile the design through Analysis and Synthesis. 2. Open the Assignment Editor. 3. Select the Timing Button on the top. 4. Enter the pin name you want under Destination Name. 5. Select the Clock Settings under Option. 5. Set the Value to the name of the setting you created in Step A. In general when you see an error message, you can click on the message and hit F1 for help, to see the Cause and Possible Actions that you can take. - Subroto Datta Altera Corp. "Panic" <panic74@hotmail.com> wrote in message news:8rEkb.32199$os2.467326@news2.e.nsc.no... > > I'm a student working an a Altera EPXA1F484C1 FPGA, and I'm having some > problems I hope someone can help me with. > > 1. Is there a way to tell Quartus that the project I'm compiling is ment as > a "internal" building block, meaning that the pins isn't actual device pins, > but "internal pins"? I'm wondering since I have several "internal blocks" > with 128 bits in and out, and Quartus stops my compilings complaining that > the device I'm compiling for has to few pins for my design. > > 2. I get stuck-at errors...and I have no idea why. I get this warning: > "Warning: No clock transition on AESRoundSP- > 2:inst|lpm_dff0:inst5|lpm_ff:lpm_ff_component|dffs[127] register" > And this continues for all 128 flipflops. But they are clocked by the > "master clock". I have not created a clock signal, but the clock is named > clk, and then Quartus should assume that the signal is a clock, right? > Anyway, Quartus compiles my design without errors, but the summary tells me > that I'm not using any LEs or any memory bits... > > The AESRoundSP-2 is a building block in a larger design, but does not > compile "on its own" because it uses too many pins and memory bits. Can this > cause the weird error in (2)? > >Article: 62109
Hi all, I've been going over the structure of the Virtex CLBs and something has me a little confused. The LUTs/function generators appear to have no clock, so I assume they act a normal logic gates. That is, inputs F/G are "processed" immediately and glitches are possible as with any array of logic gates. If there is no clock, why are there setup and hold time specifications (relative to the clk) for the F and G inputs?? If there was to be a setup time for a slice I would have thought it would be defined with repsect to the output flip flop - something like delay through LUT + setup of output FF however flip flop and LUT setup times are listed seperately. Any clarification will be much appreciated. KlodArticle: 62110
Are you sure? I look into the datasheet of Multiplier Generator V6.0, did not see anything about submodules "Anil Khanna" <anil_khanna@mentor.com> 写入消息新闻 :3f923e9f$1@solnews.wv.mentorg.com... > Thanks for the reply. > > However, I am not using the Xilinx Coregen! > Anyways, I figured out the answer to this question and now I have another Q. > > The handbook claims that there are certain submodules (of the MULT18X18S) > available for use. These are submodules like MULT4X4 etc. How does one get > access to this and what is the primitive name? > > Anil > > > "Peng Cong" <pc_dragon@sohu.com> wrote in message > news:bmqfru$j8h$1@news.yaako.com... > > If you use Xilinx IP Core > > A - 6 bit B - 6 bit B- 12 bit > > is enough > > > > "Anil Khanna" <anil_khanna@mentor.com> 写入消息新闻 > > :3f906a1c$1@solnews.wv.mentorg.com... > > > I am trying to construct a 6x6 signed multiplier using the Virtex II > block > > > multipliers. I know that the V-II multipliers are inherently a 2's > > > complement signed multiplier. However, my question is - by how much > should > > I > > > sign-extend the inputs? > > > > > > Example: > > > Input A - 6 bit > > > Input B - 6 bit > > > Output B- 12 bit > > > > > > Should I connect the remaining ports of the multiplier input (A(7:18)) > to > > > A(6) or just A(7:12) to A(6)? The handbook suggests that the > > sign-extension > > > of the inputs is done till the width of the output. Is this enough or > > should > > > I do it till the physical width of the multiplier? > > > > > > Thanks > > > > > > Anil > > > > > > > > > > > >Article: 62111
I forgot to add that calculating delay through LUT + setup of output FF does not give the listed setup times for the F and G inputs. Thanks Kload wrote: > Hi all, > > I've been going over the structure of the Virtex CLBs and something has > me a little confused. The LUTs/function generators appear to have no > clock, so I assume they act a normal logic gates. That is, inputs F/G > are "processed" immediately and glitches are possible as with any array > of logic gates. > > If there is no clock, why are there setup and hold time specifications > (relative to the clk) for the F and G inputs?? If there was to be a > setup time for a slice I would have thought it would be defined with > repsect to the output flip flop - something like > > delay through LUT + setup of output FF > > however flip flop and LUT setup times are listed seperately. > > Any clarification will be much appreciated. > > Klod > > >Article: 62112
I actually found the bugs in 4.2 to be show stoppers, where 5.2 at least
is sufficient to get the job done. I've also had better results
achieiving tight timing with 5.2 than with 4.2. I haven't evaluated 6.1
yet (mid project). I'm only talking about the tools from translate on
however. I use synplicity for synthesis, so I haven't compared XST for
recent xilinx versions.
Marc Guardiani wrote:
> jakab tanko wrote:
>
> > In my humble oppinion the best software from Xilinx was 4.2,
> > it's all downhill from there;
>
> I agree. 4.2 had bugs, but it was possible to work around them. Trying
> to compile the same project under 5.x and 6.x is a disaster. The bugs
> are so bad that it won't even synthesize.
--
--Ray Andraka, P.E.
President, the Andraka Consulting Group, Inc.
401/884-7930 Fax 401/884-7950
email ray@andraka.com
http://www.andraka.com
"They that give up essential liberty to obtain a little
temporary safety deserve neither liberty nor safety."
-Benjamin Franklin, 1759
Article: 62113Hello guys, I have been implementing a high speed controller for USB 2.0 communication on Xilinx VirtexII FPGA, which interfaces to USB bus through Philips ISP1581 device. I don't know how to go about it as I'm a very new to USB stuffs. I have got a choice of using MicroBlaze softcore microprocessor, but currently, I'm encountering lots of trouble downloading it onto the FPGA using already written C-code for ISP1581 device. So, I would be grateful if you could be able to give me some suggestions or directions on how to go about it. I wonder, if USB 2.0 core is available for ISP1581 device. Thanks, OmArticle: 62114
> What do you mean by "memory performance?" Latency for sequential > access? Latency for parallel accesses? Throughput for a single > stream? THroughput for multiple streams sharing memory? THroughput > for multiple streams from independant memories? I don't think it matters. He just saying that FPGAs provide such an abundance of functional units that memory performance (however you call it -- the ability for a given system to provide data to the function units) is limiting. He's got a 10,000 pound gorilla and he's trying to feed it bananas with a teaspoon. JakeArticle: 62115
"Valentin Tihomirov" <valentin@abelectron.com> wrote in message news:<3f92b7c1$1_1@news.estpak.ee>... > The massive parallelism is considered as the main advantage of of FPGAs. > Meantime, the bottleneck of modern systems is a memory performance. How do I > benefit in e.g. image processing using wide low speed FPGA over hi-speed > running CPU when image is located in SRAM? Today more and more FPGAs are > equipped with embedded RAM. How can FPGA benefit from the concurrent > processing having to serialize memory access? Good question, Valentin. I personally think you'll see a lot more use being made of the on-chip embedded RAM as 'cache' memory than previously. Of course, FPGAs are applied to so many problems that this use may never be applicable and it has already been applied in many situations. Bottom line is that the on-chip memory is going to be faster than off-chip memory. It's usefulness in keeping the FPGA's functional units supplied with data may come in the form of transforming it into a more useful cache structure. That may also mean that a larger part of an FPGA design will be relegated to the function of cache controller. Perhaps using block RAMs as L2-type cache and distributed local memory as an L1-type cache and trying to keep the external memory pipe as active as possible in the most efficient way depending on the functionality implemented. JakeArticle: 62116
I have a waveform simulation on Xilinx software that I am having trouble interpreting what is actually happening with it. My understanding is that it is a stopwatch with 3 push button inputs (start, stop, reset) that drive 4 Sev Seg displays (1/10sec, seconds, tens seconds, minutes). If anyone is interested in looking at the waveplot and giving me their interpretation and whether it may legitimately be made to a working bitstream, please email me. Regards DArticle: 62117
hi all, i am calculating the power consumption using xilinx xpower. For generating the VCD file i am not loading the SDF(Standard Delay Format) during VSIM. Will it affect the power calculation. thanks in advance.Article: 62118
gupt0009@flinders.edu.au (Om) wrote in message news:<b87a9948.0310191846.8a4d786@posting.google.com>... > Hello guys, > > I have been implementing a high speed controller for USB 2.0 > communication on Xilinx VirtexII FPGA, which interfaces to USB bus > through Philips ISP1581 device. I don't know how to go about it as I'm > a very new to USB stuffs. > > I have got a choice of using MicroBlaze softcore microprocessor, but > currently, I'm encountering lots of trouble downloading it onto the > FPGA using already written C-code for ISP1581 device. where is the problem? have you connected it successfully to microlaze PLB bus? > So, I would be grateful if you could be able to give me some > suggestions or directions on how to go about it. I wonder, if USB 2.0 > core is available for ISP1581 device. there is no need for USB core for ISP1581 as IS1581 is the core! you only need interfaces to ISP1581 to access from microblaze and posssible use DMAArticle: 62119
Xpost 2 cae and caf, no Fup. Hallo, "Geoffrey Mortimer" <me@privacy.net> wrote: > Anyone have any experience of BGA's (especially fine pitch types) in high > vibration environments? Is there a more appropriate newsgroup for this > topic? Actually that's a very hot topic as BGA seems to get usual in the world of FPGAs and ASICs. I know that our mechanical engineers allready research on this topic, as we are very likely to have some fine pitch BGA in a high vibration environment in future. I would guess, that you should ask in some mechanical newsgroups as well. A big problem using FBGA is the test, wether you connected all balls proberly [1], as you have no chance of easy visual inspection. bye Thomas [1] in a mechanical aspect. Of course you get a quick answer if one IO has no electrical connection. -- Don't answer to the email in from, use thomas[at]<domain above> for PM.Article: 62120
Thanks a lot John!! The problem what you've told me. I didn't have connected the to the IOPB. Regards, Arkaitz. John Williams <jwilliams@itee.uq.edu.au> wrote in message news:<3F9326D7.7030707@itee.uq.edu.au>... > Hi Arkaitz, > > arkaitz wrote: > > > > Does anybody know why? Am I doing something wrong? > > Have you actually connected the OPB to the instruction side of the > microblaze, as well as the data side...? > > Since you can verify the contents of the external ram (as data reads), > that's the only possible explanation I can think of... > > In MHS, it should look like this (in microblaze section): > > BUS_INTERFACE DOPB = d_opb_v20 # or whatever the bus instance is called > BUS_INTERFACE IOPB = d_opb_v20 # same bus, EDK will create an arbiter > > Regards, > > JohnArticle: 62121
Laurent,
I am using a Noritake Itron VFD module which has its own in glass
driving module and an Atmel Micro on the pcb which does all the hard
work. You have to send it some setup commands and then the data which is
fairly simple stuff. The problem I am finding, is that these modules
want to be set a load of commands once, and of course cpld/fpga runs off
a clock. So you have to right your code is such a way that the signal
which is clocking the data into the VFD is inhibited after the data has
been excepted.
After a good days work on it I have got a single character to be
displayed, progressing from this wont be that difficult although I thimk
that graphics may be out of the question.
In the end I hope to write a package which will have a number of
functions to make it easier for others to program this type of VFD
module. i.e. print("string", cursor_pos, font size)
For interest, here is the VFD I am using: GU254x32D-K610A4 -
www.noritake-itron.com
Thanks for your interest,
Matt
"Amontec Team, Laurent Gauch" <laurent.gauch@amontecDELETEALLCAPS.com>
wrote in message news:3f8fd4ef$1@news.vsnet.ch...
> Matt North wrote:
> > Hi all,
> >
> > I am currently working on a project in which i want to drive a dot
matrix
> > VFD using a CPLD - if anyone has any previous experience of this
> > and has got any tips i would be most gratefull.
> >
> > Thanks,
> > Matt
> >
> >
>
> Hi Matt,
>
> Using dot matrix, you have to multiplex the Row and give a command on
> the columns.
> It 'is itself very easy, but you have to make sure about the current
> specification of your dot led matrix. The most important thing is the
> compromize between the current of each led on one Row and the rom
> multiplexage.
> In normal use, you drive LED with static 10mA or 20mA, but in the dot
> matrix case you need to drive something between 50mA and 100mA dynamic
> PWM current by led.
> So, your CPLD CMOS specification will not be able to drive so much PWM
> current. You have to use line driver or MOS-FET N and P after your
CPLD.
>
> If you will play on 3.3V, you have to work with a transistor having a
> small Rds (Drain Source Resistor), not more 1.5 Ohm.
>
> We are doing a dot matrix module for our SPARTAN-3 rapid prototyping
> platform. I will receive the PCB in two weeks, I can send you a sample
> of our dot matrix board if you want.
>
> Let me know
>
> Laurent
> www.amontec.com
>
Article: 62122"jakab tanko" <jtanko@ics-ltd.com> writes: > Hi all, > > I have updated my Xilinx software to 6.1 a few days ago and it > looks like I am in for a ride; the design that worked well under > the previous version (5.2 with all service packs) wouldn't even > go through PAR anymore!! Been there - done that, PAR just crashes now! "Will be fixed in next service pack" is as far as I can get with 6.1, so its back to 5.2 for me! <snip> Cheers, Martin -- martin.j.thompson@trw.com TRW Conekt, Solihull, UK http://www.trw.com/conektArticle: 62123
Hi, so how can I write a process (within a testbench!) for a reset signal which should be asynchronous? Best regards Andr閟 V醶quez G&D Mike Treseler <mike.treseler@flukenetworks.com> wrote in message news:<3F9019AC.3010307@flukenetworks.com>... > Vazquez wrote: > > > process > > begin > > t_reset <= '1', '0' after 100 ns; > > wait; > > end process; > > > > I thought that is was a legal wait-statement when writing a testbench for functional > > simulation. > > The problem is that the wait is unconditional. > Even if the code were legal, you would never > get past the first loop of the process at 0 nS. > > -- Mike TreselerArticle: 62124
Hello Kload, maybe a look at the SRL16 feature of the LUT helps? Christian
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