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Virtex-II pro ML-300 Evaluation Platform For Sale Cheap! I have one piece of a brand new Xilinx Virtex-II pro ML-300 Evaluation Platform for sale. It is brand new and in the original factory box. Everything that came shrink wrapped is still sealed. It's never been opened or used. The part number is DO-V2P-ML300-USA. The Virtex-II ProT ML300 Evaluation Platform allows designers to investigate and experiment with features of the Virtex-II Pro FPGA. The Evaluation Platform is an ideal development platform for implementing designs using PowerPC 405 processors, Rocket I/O transceivers, IP cores, and other high performance Virtex-II Pro FPGA features.Xilinx sells this package direct for $4,695.00 each. Of course I will sell it for less than that! It comes complete with all the original documentation, factory warranty, manuals, Cables (Parallel IV, Ethernet, Fiber Optic, HSSDC2, etc.), 1GB IBM MicroDrive, ISE 5.1i (evaluation version) on CDROM's, Over 40 parameterizable IP cores, ChipScope Pro 5.1i (hardware debug tools) , Virtex-II Pro Development Kit (GNU tools, reference designs, etc.) , and the ML300 hardware platform. You can find it on Ebay at: http://cgi.ebay.com/ws/eBayISAPI.dll?ViewItem&item=2565456214&category=4663& rd=1 RudyArticle: 61976
In article <bpkjb.15757$ZH4.9173@twister.socal.rr.com>, Rudy Hartmann <rudy@rocktechnology.com> wrote: >Virtex-II pro ML-300 Evaluation Platform For Sale Cheap! Why are you selling? -- Nicholas C. Weaver nweaver@cs.berkeley.eduArticle: 61978
Before I close the door on this, I want to take one last look at using the SpartanXL for this socket. Right now there are several reasons not to use the part, but only one is a show stopper. That is the lack of an industrial temp part in the CS280 package. Looking at other lines, I see that there is nothing inherent about the package that precludes this. So what would it take for me to use a commercial temp part, say the XCS40XL-5CS280C and use it over an industrial temp range? If I scaled my timing requirements by say, 33%, would that give me enough margin over the industrial temp range? Of course the other issues are not trivial. List price is way up there, the lack of support in the ISE tools will require me to buy a $5000 synthesis tool, and I am still a little leary of designing in such an old part to a product line that may have a lifetime of 8 years. I recall working with one of these parts some 6 or 7 years ago. The toolset from Xilinx included synthesis, IIRC. Is that package no longer available? I see in the archives here that the quiescent current for the SpartanXL is very low, much lower than the data sheet number. But I can't find a clear statement about the startup current. The data sheet says 100 mA (which should not be a problem) but I wanted to know if this is much lower in current chips. -- Rick "rickman" Collins rick.collins@XYarius.com Ignore the reply address. To email me use the above address with the XY removed. Arius - A Signal Processing Solutions Company Specializing in DSP and FPGA design URL http://www.arius.com 4 King Ave 301-682-7772 Voice Frederick, MD 21701-3110 301-682-7666 FAXArticle: 61979
I rummaged around and found the old distribution of Foundation 1.5i that I had used to design with a 4000XL back in 1998 using VHDL. Will this package support the SpartanXL? I see that the version currently provided by Xilinx is ISE 4.2i. When was this package orginally released? -- Rick "rickman" Collins rick.collins@XYarius.com Ignore the reply address. To email me use the above address with the XY removed. Arius - A Signal Processing Solutions Company Specializing in DSP and FPGA design URL http://www.arius.com 4 King Ave 301-682-7772 Voice Frederick, MD 21701-3110 301-682-7666 FAXArticle: 61980
Hello: Altera Quartus II version 3.0 runs fine on RedHat Linux 9.0. If you are interested, I will post here how to do this. ----Article: 61981
library IEEE;
USE ieee.std_logic_1164.ALL;
ENTITY dte IS PORT ( rst,dcr,ri,cd,cts,rxd,data,clk: in std_logic;
dtr,start,rts,txd,out_dte: out std_logic);
END dte;
>>>>>> huge pile of VHDL removed by archive manager
END dte_arch;
can anyone please tell me what each part of the state machine is
doing? thank you very much....:)
Article: 61982
I did a similar 3 die design way back when (ca 1976) using TTL parts. It could easily be
done in a small CPLD and a short time with current tools.
Jim Granville wrote:
> Ray Andraka wrote:
> >
> >
> > Why seven segment LEDs though? It would be more appropriate to use 7 LEDs arranged
> > like the 'six' and 'one' sides of the die superimposed.
>
> Correct - and the design also does not have to have Mod 6 counting ->
> Decoder;
> it is possible to count directly in either 7 segment Font patterns, or
> in Ray's Dice-Font pattern.
>
> I have actually done a design that counts directly in 7
> segment Font patterns (0..9) - the student can explain why that
> might be a good idea.
>
> -jg
--
--Ray Andraka, P.E.
President, the Andraka Consulting Group, Inc.
401/884-7930 Fax 401/884-7950
email ray@andraka.com
http://www.andraka.com
"They that give up essential liberty to obtain a little
temporary safety deserve neither liberty nor safety."
-Benjamin Franklin, 1759
Article: 61983
As long as you discard all the bits for each illegal value it is uniform. Some
reason I was thinking the OP was looking at discarding a bit until the right
one came in. Must have been before my coffee.
jetmarc wrote:
> > An LFSR output is only "random" for a single bit out per clock. The
> > remaining bits are delayed copies of the first bit. In order to use an
> > LFSR and really have a random stream of 3 bit numbers you'd need to clock
> > it 3x per die. If you go further to reject 'illegal' combinations, then
> > you are skewing the probabilities of the legal combinations so that they
> > are no longer uniform.
>
> I agree that you have to implement the full PRNG and not just use some
> bits of the LFSR, to get the full quality of the PRNG.
>
> However, rejecting illegal values is IMHO a "good" thing to do, meaning
> that it doesn't bias. After all, each and every output value of the
> PRNG is "unpredictable" (within the quality limits of the PRNG). Thus,
> rejecting all 0x6 and 0x7 doesn't reveal more information than that the
> final output won't ever be 0x6 or 0x7. Still, an attacker can't predict
> any output value, given that he couldn't predict them already before we
> added the reject circuit.
>
> It's a consequence of the lack of feedback into the PRNG. The PRNGs
> internal state is only changed through the intended means - by going
> from state n to n+1 (next value) etc. All cryptographic study that
> the PRNG design has received, inherently also applies to the
> combination of PRNG and rejection circuit.
>
> The only disadvantage of this method is that the execution time is not
> predictable. Although highly unprobable, the PRNG could output 0x6 / 0x7
> for a lot of cycles in sequence. Thus you don't know how long it takes
> to get an acceptable (legal) output. In this particular application
> (dice) however, I don't think that it will be a problem of significance.
>
> Marc
--
--Ray Andraka, P.E.
President, the Andraka Consulting Group, Inc.
401/884-7930 Fax 401/884-7950
email ray@andraka.com
http://www.andraka.com
"They that give up essential liberty to obtain a little
temporary safety deserve neither liberty nor safety."
-Benjamin Franklin, 1759
Article: 61984> Well, not really an adder. It is an XOR or XNOR combination of the terms in the Yeah adder isn't the best word, because the adders we normally think of have a carry chain. Modulo-2 addition has no carry, so it simplifies to an XOR.Article: 61985
Steve, I never gave a thought abt that, I think thats the possibility, Thank you RAm Steve Lass <lass@xilinx.com> wrote in message news:<3F8D7159.4070401@xilinx.com>... > ram wrote: > > >Hi all, > > I am interested in doing partial reconfiguration using Xilinx Virtex > >2 pro, i am having a HW AFX xilinx prototype baord. > >I tried the small bit manipulation method defined in Xilinx > >application note > >xapp290, with the simple example , Example 1 simple system desing from > >xilinx EDK examples web page. > >Ok , my desing is this, > > I am using PPC405, and uartlite and gpio with uart continiously > >writing some data in Hyper terminal and gpio is connected to four leds > >and writing '1' to it > >I tried to change the routing for the LEDs , I do have to mention > >here, my board has 8 user LEDS, i changed the routing from upper half > >to lower half and generated the partial bit stream. > > > The configuration frames are columns, so if the routing you are changing > is in the same column > as the PPC, UART, or any of their routing, they will probably stop. > > Steve > > >Everything goes well so far, but when i download this partial > >bitstream into FPGA, my uart stops putting out data, but LEDS gets > >rerouted and now the lower half LEDs o/p '1'. > >I would like to know wether what i am trying to do was right, also if > >anybody worked on small bit manipulations, I would appreciate their > >comments and advice. > >Thank you for the posting me a reply. > >bye > >Ram > > > >Article: 61987
> Well, I FINALLY finished my PhD. Congratulations! Sounds like you didn't have the luxary to concentrate solely on your PhD. You had to juggle a job and perhaps a family also? How was your dissertation defense? What was the topic? Congrats again, I'm sure you're glad to have it done with. Now you get to bust your butt getting tenure, if that's your route ;_) --VinhArticle: 61988
> I expected to see this entitled: "XAPP 998" or something similar... LOLArticle: 61989
> If your homework is too tough, ... > These lines were triggered by the endless dice discussion. Haha. I think some very busy students could use a Cliff Notes version of your poetry. Don't think they'd have time to read it.Article: 61990
"Vinh Pham" <a@a.a> wrote in message news:5jnjb.16952$ZH4.2178@twister.socal.rr.com... > > If your homework is too tough, > > These lines were triggered by the endless dice discussion. > > Haha. I think some very busy students could use a Cliff Notes version of > your poetry. Don't think they'd have time to read it. Some years ago, (before the web) they came out with Cliff Notes on CD-ROM, so convenient for directly copying into papers. I had thought then that it would be time for a system to quickly tell a grader that a paper was copied directly. Maybe even using FPGA hardware to do it! -- glenArticle: 61992
> Some years ago, (before the web) they came out with Cliff Notes on CD-ROM, > so convenient for directly copying into papers. I had thought then that it > would be time for a system to quickly tell a grader that a paper was copied > directly. Wouldn't it be funny if Cliff Notes was the company to provide such an app/service? Heh talk about creating your own market. > Maybe even using FPGA hardware to do it! Heh that sounds like a much better project than electric dice :_)Article: 61993
"SneakerNet" <nospam@nospam.org> wrote in message news:<x_hjb.179653$JA5.4501661@news.xtra.co.nz>... > "Antti Lukats" <antti@case2000.com> wrote in message > news:80a3aea5.0310150300.79f98bbd@posting.google.com... > > "SneakerNet" <nospam@nospam.org> wrote in message > news:<Qf%ib.178724$JA5.4476502@news.xtra.co.nz>... > > > Hi All > > > > > > Has anyone got this going fully (using the VB code from the site)? I'm [snip] 1 englsish translation please post or send per email antti@openchip.org 2 sorry if the japanese version doesnt work together with the VB code, I did not check for that, only assumed. Q: When you plugin the device windows does show a popup? Q: the leds on the hardware indicate what usb activity? Q: you connected (the japanese version) usb DP/DM directly to altera fpga? using opencores USB 1.1: it works out of box (for xilinx) you need to grab some additional cores from CVS then it is completer. opencores usb1.1 enumerates as usb device (with no microcontroller) but it does act as USB HID device so you can not use VB code to talk to it (at least without Windriver or something alike) if you have working hardware (connection from cyclone to usb connector) then you dont have to use USB11T1A just adopt the philio.v from japanese and connect it between the opencores PHY and usb connector. minor adoption may be required. if you made the japanese version to synthesize for altera is possible to get access to that modified code? hope it was of some help! anttiArticle: 61994
uselinux2000@yahoo.com (linux user) wrote in message news:<c02536de.0310151721.7d855d14@posting.google.com>... > Hello: > Altera Quartus II version 3.0 runs fine on RedHat Linux 9.0. > If you are interested, I will post here how to do this. > ---- Yes please. Sesh67Article: 61995
vhdl200@yahoo.com (vick) wrote: > TYPE state IS (st0,st1,st2,st3,st4,st5,st6,st7,st8,st9, > st10,st11,st12,st13,st14,st15,st16,st17,st18,st19, > st20,st21,st22,st23,st24,st25,st26,st27,st28,st29); Don't use state-machines that size with \=2^n defined states. Otherwise your systhesized logic won't be predictable without knowing details of the tool you use for synthesis. Especially structural equivalence will likely fail. > processdte: PROCESS (rst,dcr,ri,cd,cts,rxd,data,clk) Don't do ever mix clocked and combinatorial processes. Your simulation results may differ from the logic your synthesis tool generates. > can anyone please tell me what each part of the state machine is > doing? thank you very much....:) The first part (if rst=...end if) switchtes the state each clockcycle. The second part calculates the outputs and nextstate for each state your fsm is in. The output is a function of the actual state, the next state is a function of state and input. bye ThomasArticle: 61996
uselinux2000@yahoo.com (linux user) wrote in message news:<c02536de.0310151721.7d855d14@posting.google.com>... > Hello: > Altera Quartus II version 3.0 runs fine on RedHat Linux 9.0. > If you are interested, I will post here how to do this. > ---- Yes I am! Thank you very much, DAMCArticle: 61997
hi to all can anyone please explain to me how each line of the code work please.....
thank to all
:)
library IEEE;
USE ieee.std_logic_1164.ALL;
ENTITY dte IS PORT ( rst,dcr,ri,cd,cts,rxd,data,clk: in std_logic;
dtr,start,rts,txd,out_dte: out std_logic);
END dte;
ARCHITECTURE dte_arch OF dte IS
>>>>>> third time this fool posted a huge pile of VHDL. removed by archive manager
END dte_arch;
Article: 61998Hi, I am a graduate student at Stanford University, in the Department of electrical engineering. As part of an academic project, we are planning to set up a wireless test bed, where several wireless nodes would communicate with each other using some ad hoc protocol. We want these boards to be FPGA/PLD based. Are there any programmable wireless test boards (with RF module) in the market (say from Altera, Xilinx or any other company), which you think would be suited to this purpose. Any information shall be appreciated. Also, if you think that I have posted on the wrong newsgroup, please suggest a better place where I could post. Looking forward to your help. Best, Aditya ============================================================================ ~Peace~ Aditya Dua 81C, Escondido Village Ph.D. candidate Stanford, CA 94305 Department of Electrical Engineering http://www.stanford.edu/~dua -> GOD is real, unless explicitly declared integer. ============================================================================
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