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shengyu_shen@hotmail.com (ssy) wrote in message news:<f4a5f64f.0201062326.49223519@posting.google.com>... > nothing to worry about, I see about 100 such warning, but never happen anything > > cortyus <saority@hour.edu> wrote in message news:<ee740d8.-1@WebX.sUN8CHnE>... > > # WARNING: Simulation log file vsim.wlf is open by another ModelSim application or was not closed properly. > > # WARNING: Could not open log file vsim.wlf, using C:\TEMP\vsimw4.wlf instead. From what I have seen, this anomaly started to occur with the release of v5.5a. When I called Model Technologies about it, they said they needed a testcase to demonstrate the problem. I did not have a testcase that was not proprietary. I have found that once this message starts, the only way to get rid of the repeated warnings (after each restart -f), was to close down Modelsim, delete the vsim.wlf file in the working directory, and the vsimwX.wlf files in the "TEMP" directory. Hope this helps, NewmanArticle: 38151
Hello! I am looking for a good overview article concerning reliable systems with FPGAs. Pros and Cons of the usage of FPGAs, usage of cores etc. Partial reconfiguration may be a pro. Can anybody recommend me one? I would prefer one that is not too much aliased by one FPGA company. Thanks, MichaelArticle: 38152
--------------FFC60F3CBDD7E18073981589 Content-Type: text/plain; charset=us-ascii Content-Transfer-Encoding: 7bit Michael, Please consult the web site http://www.support.xilinx.com/, and search for everything on: triple redundancy. All of the information on TMR will then pop-up and allow you to review. This represents the best known methods for reliable and fault tolerant design in Xilinx FPGAs. If you also do a search using Google http://www.google.com/ for triple redundancy, SEU, or single event upsets, or single event errors, you will get a wealth of information. Comparing SRAM FPGA with anti fuse FPGA and ASICs is fairly easy by reviewing the anti fuse FPGA vendors' web sites, and the technical papers on SEUs on the web. There is some excellent information on the anit fuse FPGA websites. The result of all of that research will be that TMR is used by all vendors to obviate the effect of SEUs, as even ASICs and anti fuse logic FPGAs are disturbed by SEUs. I encourage anyone who is interested to take the time and do the searches and review the information. Austin Michael Boehnel wrote: > Hello! > > I am looking for a good overview article concerning reliable systems > with FPGAs. Pros and Cons of the usage of FPGAs, usage of cores etc. > Partial reconfiguration may be a pro. > > Can anybody recommend me one? > > I would prefer one that is not too much aliased by one FPGA company. > > Thanks, > > MichaelArticle: 38153
I am looking for PDH MUX (E2,E3) VHLD cores and any sync frame based device VHLD examples. Thanks. ----- Posted via NewsOne.Net: Free (anonymous) Usenet News via the Web ----- http://newsone.net/ -- Free reading and anonymous posting to 60,000+ groups NewsOne.Net prohibits users from posting spam. If this or other posts made through NewsOne.Net violate posting guidelines, email abuse@newsone.netArticle: 38154
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You mention you have compiled the libraries. If this is true, then it sounds like the problem you are seeing is you have not properly mapped the libraries to tell the simulator where the libraries exist on the system. You may do this from
the GUI using the pull-down menus but I will describe the commands on how to do this here since it is easier to describe.
Within the ModelSim simulator, change to the project directory if you are not already there:
cd <path_to_project>
Use the vmap command to tell the simulator where to find the required libraries:
vmap xilinxcorelib_ver <path_to_compiled_corgen_lib>
vmap unisims_ver <path_to_compiled_unisim_lib>
vmap simprims_ver <path_to_compiled_simprim_lib>
That should hopefully clear up the library and linking errors.
-- Brian
Orlls wrote:
> when i simulate with modelsim5.5e,it says:
> # testbench
> # vsim -lib work -t 1ps -L xilinxcorelib_ver -L unisims_ver -L simprims_ver -foreign {hdsInit f:/eda_tools/resources/downstream/modelsim/ModelSim_32Bit.dll} -pli f:/eda_tools/resources/downstream/modelsim/ModelSim_32Bit.dll testbench glbl
> # Loading f:/eda_tools/resources/downstream/modelsim/ModelSim_32Bit.dll
> # Loading work.testbench
>
> # ERROR: Could not open library xilinxcorelib_ver at xilinxcorelib_ver: No such file or directory
> # ERROR: Could not open library unisims_ver at unisims_ver: No such file or directory
> # ERROR: Could not open library simprims_ver at simprims_ver: No such file or directory
> # Loading work.NA_Message_Generate
> # ERROR: Could not open library xilinxcorelib_ver at xilinxcorelib_ver: No such file or directory
> # ERROR: Could not open library unisims_ver at unisims_ver: No such file or directory
> # ERROR: Could not open library simprims_ver at simprims_ver: No such file or directory
> # Loading work.NA_Message_Receive
> # ERROR: Could not open library xilinxcorelib_ver at xilinxcorelib_ver: No such file or directory
> # ERROR: Could not open library unisims_ver at unisims_ver: No such file or directory
> # ERROR: Could not open library simprims_ver at simprims_ver: No such file or directory
> # Loading work.na_fifo16_256
> # ERROR: Could not open library xilinxcorelib_ver at xilinxcorelib_ver: No such file or directory
> # ERROR: Could not open library unisims_ver at unisims_ver: No such file or directory
> # ERROR: Could not open library simprims_ver at simprims_ver: No such file or directory
> # Loading work.SYNC_FIFO_V3_0
> # ERROR: Could not open library xilinxcorelib_ver at xilinxcorelib_ver: No such file or directory
> # ERROR: Could not open library unisims_ver at unisims_ver: No such file or directory
> # ERROR: Could not open library simprims_ver at simprims_ver: No such file or directory
> # Loading work.MEM_BLK
> # Loading work.glbl
>
> after i compile xilinx lib,there is not simprims_ver/xilinxcorelib_ver /unisims_ver directory.why?
Article: 38155Jim Granville <jim.granville@designtools.co.nz> wrote in message news:<3C38A57A.2BBE@designtools.co.nz>... > Can you detail more on the 'high speed serial interface' ? It's actually several (up to 5). Each is a pretty standard SPI-like synchronous serial interface running at about 150 kbps. They are other boards that are on separate lines, not a shared bus (long story). Anyway if all could come into UARTs then it would be great because there's not that much traffic, maybe 256 bytes / second throughput. But without UARTs we have to bit-bang it and there's just not enough time to easily do more than 1 or 2 with the AVR. I suppose that we could go to something with a much faster clock rate and be able to manage bit-banging with very fast task switching but to my mind it's just easier to hang a UART on each one and be done with it. Obviously we can also go to a different microcontroller that has multiple UARTs, or use separate UART chips, or an FPGA, lots of choices. One of the tasks of this board will be to multiplex these disparate data streams onto 1 HSS interface like it should have been in the first place, so the next poor engineer who gets thrown into the middle of this mess won't have this to contend with. :) > It will ALWAYS be more expensive to do a uC in a SRAM FPGA, than as > a Std core. There is a HUGE silicon ratio between a configurable SRAM > FPGA, and a hard wired uC. FPGAs are more 'shrunk', but don't forget > to add the configuration memory. > > Even the FLASH C51's are edging under $1, with OTP and ROM one well > under $1 (volume) > > Where the uC SoftCore makes sense, is when the uC is a small portion of > the > LOGIC budget, and the FPGA was needed anyway, for other (significant) > tasks. > Then, 'it was there anyway' bean-counting can apply. Great, this is exactly the kind of ballpark cost info that I needed, since I don't know anything about FPGA at this point. Thanks again. BTW - about how much $$$ is the smallest FPGA that will run a 6805 or 8051 core? Is it like $10 or $100 or what? Thanks also for the link to your web page. I spent about 10 years working with 6805 and 6811 and finally about 5 years ago I had to abandon Motorola and to 8051 because I was tired of never being able to buy Motorola parts. In my opinion they REALLY dropped the ball by driving everybody away like that. Oh well, lesson learned, make sure that you have lots of sources. - StoutArticle: 38156
This is a multi-part message in MIME format. --------------F0D399E0384AED84AA60CF25 Content-Type: text/plain; charset=us-ascii Content-Transfer-Encoding: 7bit Antonio, What this message is telling you is that you are most likely connecting the clock signal to resources other than the clock pins of registers or latches in the design (i.e. feeding the clock into LUTs, D inputs of registers, etc.). This is generally not suggested because the clock routing resources (BUFGs) are designed to directly connect to the clock pins of the CLB and IOB registers but are not designed to connect to other resources in the chip. This does not mean it can be routed however you generally pay a hefty timing penalty for a data-path to hop onto the global routing network and then hop off it onto several local routes to get it to the desired desination. From what you decribe, this message could have occured from the derrived, divided clock depending on how you coded that however could also come from another source in the design where your decribe the clock as a part of a data path. My suggestion is, if you have DLL and global buffer resources free, to use the DLL to create the divided clock and see if that message goes away. Another suggestion would be to use a clock enable to "slow-down" the portion of your design you are currently using the clk_div_4 clock and that would keep all of your clocks in the same domain. I would also look over the code to see if you have coded the clock into any logic resources and if so, see if there is a better way to achieve your goals without using the clock for logic paths. If your timing is slow enough and you do not encounter timing issues from it, then you can get away with this warning message safely. I would be careful how you construct the divided clock if you are transferring data from one domain to the other because if you get the two out of phase enough, it will make timing very tricky. If you can get rid of that warning message and sync up the two clock domains, then timing analysis will certainly be far easier for your design. -- Brian Antonio wrote: > In my project I've two clocks : > 1) clk > 2) clk_div_4 obtained from clk > > synplify tells me that it inferred clk_div_n clock so he discover it, > but when I send the mapped design to Xilinx 4.1 SP3 after P&R I've the > message that clk_div_n is a clock net that use not dedicated > resources, I'm implementing on Xilinx XCV1000BG560-4, how I can solve > the problem and assign to clk_div_n dedicated resources ???Article: 38157
llossak wrote: > # WARNING: [TSCALE] - Module 'MEM_BLK' does not have a `timescale directive in effect, but previous modules do > # Region: /testbench/d/NA_U4/Na_U1/inst/memblk > # Loading work.NA_Message_Generate > # Loading work.glbl > > why? This is a stupid warning. Maybe MTI will add Yet Another Command-line Switch to turn it off? I'm of the not-so-humble opinion that you don't need timescales in your synthesizable sources -- there's no timing information in those sources, anyway. Of course, you need a timescale in your test benches. Otherwise, your simulator won't know how long #10 is. --aArticle: 38158
"satya" <satya@iwavesystems.net> schrieb im Newsbeitrag news:82741d43.0201070446.5e8f2ccd@posting.google.com... > Hi All, > I have a design that is to be implemented on XILINX Virtex2 FPGA.I > have a design that should work at 155Mhz internally.By using ISE4.1i I > am able to get around 100Mhz without applying timing constraints.My > doubt is that how much change in frequency(approximately) we can > achieve by applying timing constraints?.I am using Synopsis FPGA Hmm, I dont think you will get this increase of performance just by using timing constraints. I guess you will get ~25MHz, not more. > Express for synthesis.which synthesis tool will provide better > frequency results in 4.1i? > One more doubt is that,is constraint based implementation is a best > method of core implementation?? Why that? Applying timing constraints is always usefull and tell the tools how hard to try. This will not make the design faster than perfect possible, but can influence Place and Route times. To get the circuit working at higher frequencys there are many ways - use a faster chip - use a better HDL code / Schematic - use pipelining - use floorplaning - use cute design ;-) -- MfG FalkArticle: 38159
satya wrote: > Hi All, > I have a design that is to be implemented on XILINX Virtex2 FPGA.I > have a design that should work at 155Mhz internally.By using ISE4.1i I > am able to get around 100Mhz without applying timing constraints.My > doubt is that how much change in frequency(approximately) we can > achieve by applying timing constraints? This somewaht depends on what effort levels you were running the place and route tools with. If you are using the default levels (-ol 2) you can generally see a good improvement in timing with the inclusion of timing constraints. At the higher effort levels, you geneally see less of an improvement but generally do see an improvement none-the-less. These are general statements and rather vauge as you can see but it is difficult to make hard conlusions of this nature and my best advice is to try it out yourself and see what you get. Generally it does not take too much time to run a design through the software and that is the only way you can get the real answer to question. > .I am using Synopsis FPGA > Express for synthesis.which synthesis tool will provide better > frequency results in 4.1i? I am not going to make a claim that any one synthesis tool is better than another. It is not my place to do so and I will leave that up to others in this group to voice that opinion. What I can say is that no one synthesis is the best tool for all designs at all times. Different types of designs and coding styles may agree with one synthesis tool better than others so if you are not happy with the tool you are using and have access to another, then I would certainly try it. With that said, I would suggest trying the XST synthesis tool if you have access to it. The reason I suggest that is because it is included free with the ISE software and if you have it, you might as well try it to see if it works better for your design and your coding style than the synthesis tool you are already using. If it doesn't, then you all you have lost is a little time to try it out. > One more doubt is that,is constraint based implementation is a best > method of core implementation?? I would ceratinly suggest applying timing constarints if you know what your clock and chip frequencies are going to be. The Xilinx place and route tools generally work best with timing constraints and you generally see the best results in terms of performance when using them. I would suggets to keep them simple though. Constrain what needs to be constrained and do not constrain what doesn't. This generally means to put period constarints on your clocks and offsets on your I/O. If you have known false paths or multi-cycle paths, you can put TIGs and FROM:TOs on those to let the tools know to relax a bit there and perhaps give you better performance else where. The benefit you get from entering these timing constarints is not only a possible increase in performance, but it also eases timing analysis a great deal because if the design is fully and properly constrained, all you generally need to do is see if it all timing costraints passed or not. If not, the timing report will highlight which paths are failing for you. > Please clear my doubts.Also please point me to some good 4.1itutorials > for various options. In terms of adding timing constarints, I can point you to the http://suport.xilinx.com website and more specifically, the Techtips: Timing and Costraint section. In there you will see a link to a presentation called the 3.1i Timing Presentation at http://support.xilinx.com/support/techtips/documents/timing/presentation/timingcsts3_1i/index.htm This is a good straight forward overview of most all of the constraints availible to you. While this document is a good resource, I generally suggest for most people to just use the Constraints Editor to enter thier timing constraints. It is rather easy and straight-forward to use and most do not need to consult the documentation in order to properly constrain thier design. Between using the Constarints Editor and that presentation I pointed to, you should not have any problems entering your timing constarints and seeing how the tool reacts to them. At minimum, it will make timing analysis a whole lot easier you you however you will very likely see better perfomance in the process as well. Good luck, -- Brian > > I will be waiting for reply. > > Thanks and Regards > - satyaArticle: 38160
Andy Peters wrote: > llossak wrote: > > > # WARNING: [TSCALE] - Module 'MEM_BLK' does not have a `timescale directive in effect, but previous modules do > > # Region: /testbench/d/NA_U4/Na_U1/inst/memblk > > # Loading work.NA_Message_Generate > > # Loading work.glbl > > > > why? > > This is a stupid warning. Maybe MTI will add Yet Another Command-line > Switch to turn it off? This is true for all Verilog simulators I am aware of. I do not think this has to do with Modelsim so much as with the language itself. VHDL's precision is specified from the simulator and the unit resolution is implicitly specified with the value. Since with Verilog, this is specified with the `timescale, without it, neither is known in the code. This is fine if no modules in the design have it as it is implied as a "unit" but if some have it and some do not, then there can be an issue. > I'm of the not-so-humble opinion that you don't need timescales in your > synthesizable sources -- there's no timing information in those sources, > anyway. I think the issue here is syncing up the various code. If none of the modules contain a `timescale, then what you say is true and I do not think you would ever see this warning. If some but not all do, then you get some code in a "time domain" for lack of a better word, and some that are not. Unless all or none are specified, the simulator does not know how to sync them up and thus schedule the events. In Verilog #10 can mean wait 10 units, wait 10 pico seconds, wait 10 nanoseconds, wait 10 seconds, etc. Unless the `timescale is specified, the simulator has to infer that value in order to figure out the order of events and that is what the warning message is trying to inform you in an encryptic way. > Of course, you need a timescale in your test benches. Otherwise, your > simulator won't know how long #10 is. Actually, if you do not have any `timescales at all, it is assumed to be units. The problem only exists when you have some that are specied and some that are not. In general, it is always a good idea to include one in every piece of code and that way nothing is implied and therefore possibly get you into trouble later. Since all Xilinx UNISIM components contain `timescales, it kind of forces you to do this or bear the warning message if you instantiate any Xilinx primitives in your code in your front-end code. Needless to say, you should always have it for timing simulation. -- Brian > > > --aArticle: 38161
I have a FIR that can interpolate by M (64 in this case) and I wish to use this as a base filter to interpolate by any rational number (less than M). I plan to linearly interpolate between the two relevant output samples. That is, if my current phase is 2*pi * (3/128), I will linearly interpolate between arms 1 and 2 of the polyphase FIR (corresponding to phases 1/64 and 2/64) to get my result. Does anyone know how I can calculate how much noise is introduced by linear interpolation? p.s. Farrow won't work in this case. -KevinArticle: 38162
Stout wrote: > > Jim Granville <jim.granville@designtools.co.nz> wrote in message news:<3C38A57A.2BBE@designtools.co.nz>... > > > Can you detail more on the 'high speed serial interface' ? > > It's actually several (up to 5). Each is a pretty standard SPI-like > synchronous serial interface running at about 150 kbps. They are > other boards that are on separate lines, not a shared bus (long > story). Anyway if all could come into UARTs then it would be great > because there's not that much traffic, maybe 256 bytes / second > throughput. But without UARTs we have to bit-bang it and there's just > not enough time to easily do more than 1 or 2 with the AVR. I suppose > that we could go to something with a much faster clock rate and be > able to manage bit-banging with very fast task switching but to my > mind it's just easier to hang a UART on each one and be done with it. > Obviously we can also go to a different microcontroller that has > multiple UARTs, or use separate UART chips, or an FPGA, lots of > choices. > > One of the tasks of this board will be to multiplex these disparate > data streams onto 1 HSS interface like it should have been in the > first place, so the next poor engineer who gets thrown into the middle > of this mess won't have this to contend with. :) I'm a little lost. You say SPI, but then mention UARTS. These are all SLAVE devices ? Normal SPI has CLK, DataOUT, DataIN, and a ChipSelect. Common expand is by parallel of CLK,DI,SO, and individual Selects. In the simplest form, that's a single HW SPI port ( see T89C51RC2 etc), plus a HC138, or a simple PLD. If the chip select is missing, you can MUX the clock lines (etc) We have developed a BUS we call SPL, which raises the IQ of SPI system to closer to i2c, and is optimised for using PLDs as expansion IO. There are 2,3 and 4 wire variants. > > It will ALWAYS be more expensive to do a uC in a SRAM FPGA, than as > > a Std core. There is a HUGE silicon ratio between a configurable SRAM > > FPGA, and a hard wired uC. FPGAs are more 'shrunk', but don't forget > > to add the configuration memory. > > > > Even the FLASH C51's are edging under $1, with OTP and ROM one well > > under $1 (volume) > > > > Where the uC SoftCore makes sense, is when the uC is a small portion of > > the > > LOGIC budget, and the FPGA was needed anyway, for other (significant) > > tasks. > > Then, 'it was there anyway' bean-counting can apply. > > Great, this is exactly the kind of ballpark cost info that I needed, > since I don't know anything about FPGA at this point. Thanks again. > > BTW - about how much $$$ is the smallest FPGA that will run a 6805 or > 8051 core? Is it like $10 or $100 or what? The core is not such an issue as the CODE storage. Something like a T89C51RD2 has 64K Code and 2KEE,. If you run this off=chip, then a small FPGA will do, but the chip count has climbed, and EMC/EMS is much worse.... If it's on chip, you need a FPGA with sufficent BLOCK RAM, and in all FPGA or FPSLic solutions, it's a fairly 'hard ceiling' when you code goes above a certain size! > Thanks also for the link to your web page. I spent about 10 years > working with 6805 and 6811 and finally about 5 years ago I had to > abandon Motorola and to 8051 because I was tired of never being able > to buy Motorola parts. In my opinion they REALLY dropped the ball by > driving everybody away like that. Oh well, lesson learned, make sure > that you have lots of sources. > > - Stout - jgArticle: 38163
Does any one know how to implement I2C or SPI interfaces with FPGA.. I am trying to implement SPI/I2C or vice versa on FPGA. thanksArticle: 38164
satya wrote: > Hi All, > I have a design that is to be implemented on XILINX Virtex2 FPGA.I > have a design that should work at 155Mhz internally.By using ISE4.1i I > am able to get around 100Mhz without applying timing constraints.My > doubt is that how much change in frequency(approximately) we can > achieve by applying timing constraints?.I am using Synopsis FPGA > Express for synthesis.which synthesis tool will provide better > frequency results in 4.1i? > One more doubt is that,is constraint based implementation is a best > method of core implementation?? > Please clear my doubts.Also please point me to some good 4.1itutorials > for various options. > I will be waiting for reply. > > Thanks and Regards > - satya As others have pointed out using timing constraints will not necessarily get you through the eye of the timing needle. But at least PERIOD specs on you clocks are needed so that you can use the timing analyser to report which paths are failing to meet your 155MHz timing. Once you have that info then you at least know where to start applying Falk's list which can be summarised by ``If you want a fast implementation then either (i) do a fast design or (ii) buy an expensive part''. There are no magic bullets. Above all you need to understand what the synthesis tool is producing from the HDL contructs in your source and how to control it.Article: 38165
> I am looking for a good overview article concerning reliable systems > with FPGAs. Pros and Cons of the usage of FPGAs, usage of cores etc. > Partial reconfiguration may be a pro. The following link: http://klabs.org/ --IKArticle: 38166
>There's also some other odds and ends but the real requirement that is >pushing me towards new hardware is the interfaces. An 8051 is way slower than an 8515. If by luck you find one that features your interface, you will experience whole new problems. >OK that was easy. :) In the future we may want to implement a 6805 >core in order to replace another board (6805 based) and thus only have >to stock 1 part, just download different "personality" to make it look >like whatever legacy board it is replacing. I can't believe that an FPGA w/ 6805 softcore is more economic than a real 6805, in terms of board space, power consumption and price tag. >Since the original AT90S8515 board is not terribly expensive I'm >probably looking at a respin. I really like the idea of one common >board that we can configure as needed at production time (with 8051 or >6805 core) but I need to learn a whole lot more about costs, >capabilities, etc. in order to get close to making a case for it. Look at the Atmel AT94 FPSLIC series if you want to dream a little.. Marc.Article: 38167
ac-ic <bangea01@yahoo.com> wrote in message news:<ee74117.-1@WebX.sUN8CHnE>... > Does any one know how to implement I2C or SPI interfaces with FPGA.. I am trying to implement SPI/I2C or vice versa on FPGA. > > thanks Here is some information to get you started. A link to I2C information from Phillips http://www.semiconductors.philips.com/buses/i2c/facts/ A link to some opencores I2C IP http://www.opencores.org/projects/i2c/ A link to a Xilinx I2C App note http://xilinx.com/xapp/xapp333.pdf Hope it helps, NewmanArticle: 38168
I notice a 128bit comparator is a timing-cost path in a FPGA. For example, case1: A[127:0] == B[127:0] It takes around 5 logic level and 6ns in a VirtexII device. It's OK to meet our 125MHZ clock. case2: A[127:0] > B[127:0] It takes 64 logic levels and 14ns in the same device since a serie of carry chain is involved. It force me to serperate the comparing process into 2 64bits cycle and deadly degrade the performance. My question is why not (or how )the synthesis tools to do the compare with LUT like the case1 instead of carry chain? I believe a LUT can function as a comparator since no matter how complex the logic is it cares only the number of inputs. Although it will use more resources. Anybody?Article: 38169
yujun@huawei.com (Yu Jun) writes: > I notice a 128bit comparator is a timing-cost path in a FPGA. > > For example, > > case1: A[127:0] == B[127:0] > > It takes around 5 logic level and 6ns in a VirtexII device. It's OK to > meet our 125MHZ clock. > > case2: A[127:0] > B[127:0] > > It takes 64 logic levels and 14ns in the same device since a serie of > carry chain is involved. It force me to serperate the comparing > process into 2 64bits cycle and deadly degrade the performance. > > My question is why not (or how )the synthesis tools to do the > compare with LUT like the case1 instead of carry chain? I believe a > LUT can function as a comparator since no matter how complex the logic > is it cares only the number of inputs. Although it will use more > resources. A magnitude comparison is fundamentally a subtraction. The MSB output of the subractor, and the carry output, depend on EVERY input to the comparator. You could try using a carry-save or carry-select adder rather than a simple ripple carry adder, but I doubt that you'll improve the speed much since the carry chain is quite optimized.Article: 38170
ngdbuild -p xc9572-7-pc84 -uc re.ucf -dd .. c:\xilinx\active\projects\re\re.edf re.ngd Release 3.3.08i - ngdbuild D.27 Copyright (c) 1995-2000 Xilinx, Inc. All rights reserved. Command Line: ngdbuild -p xc9572-7-pc84 -uc re.ucf -dd .. c:\xilinx\active\projects\re\re.edf re.ngd Launcher: Executing edif2ngd "c:\xilinx\active\projects\re\re.edf" "C:\Xilinx\active\projects\re\xproj\ver1\re.ngo" Release 3.3.08i - edif2ngd D.27 Copyright (c) 1995-2000 Xilinx, Inc. All rights reserved. Writing the design to "C:/Xilinx/active/projects/re/xproj/ver1/re.ngo"... Reading NGO file "C:/Xilinx/active/projects/re/xproj/ver1/re.ngo" ... Reading component libraries for design expansion... Annotating constraints to design from file "re.ucf" ... Checking timing specifications ... Checking expanded design ... FATAL_ERROR:StaticFileParsers:Xml_Node.c:358:1.12.8.2 - Corrupt or missing Xml conversion files. Process will terminate. To resolve this error, please consult the Answers Database and other online resources at http://support.xilinx.comArticle: 38171
In article <651e62f3.0201071851.705fa51b@posting.google.com>, Yu Jun <yujun@huawei.com> wrote: >I notice a 128bit comparator is a timing-cost path in a FPGA. > >For example, > >case1: A[127:0] == B[127:0] > >It takes around 5 logic level and 6ns in a VirtexII device. It's OK to >meet our 125MHZ clock. > >case2: A[127:0] > B[127:0] In order to do that style of comparison in the most efficient manner, for unsigned, one performs A-B and sees the sign of the result. There is no real way to shortuct this. Unfortunatly, there is no way to do this in a single cycle > 125 MHz in the Virtex 2 part (according to their data sheets). So you are going to have to pipeline this into two stages. Probably a better break is NOT a 64 bit/64 bit break, but instead build a pipelined carry-select adder, with the first stage generating the lower 32 bit results and the partial sections for the upper 96 bits, and the second stage doing the muxing for the upper 96 bits. -- Nicholas C. Weaver nweaver@cs.berkeley.eduArticle: 38172
In article <qhpu4l7del.fsf@ruckus.brouhaha.com>, Eric Smith <eric-no-spam-for-me@brouhaha.com> wrote: >A magnitude comparison is fundamentally a subtraction. The MSB output >of the subractor, and the carry output, depend on EVERY input to the >comparator. You could try using a carry-save or carry-select adder >rather than a simple ripple carry adder, but I doubt that you'll >improve the speed much since the carry chain is quite optimized. I'd bet that the synthesis tools (looking at the Xilinx data sheets) are already producing a longer carry save or carry select adder, especially looking at the data from the Xilinx data sheets: http://www.xilinx.com/partinfo/ds031-3.pdf which says, for virtex2, a register->register 16 bit add can run at 230 Mhz, while a 64 bit is running at 115 MHz. -- Nicholas C. Weaver nweaver@cs.berkeley.eduArticle: 38173
yes ,i have added `timescale in my all verilog file with "include timescale .v",But this 'MEM_BLK' is generated by ISE4.1 coregen fifo include . here: /******************************************************************* * This file is owned and controlled by Xilinx and must be used * * solely for design, simulation, implementation and creation of * * design files limited to Xilinx devices or technologies. Use * * with non-Xilinx devices or technologies is expressly prohibited * * and immediately terminates your license. * * * * Xilinx products are not intended for use in life support * * appliances, devices, or systems. Use in such applications are * * expressly prohibited. * * * * Copyright (C) 2001, Xilinx, Inc. All Rights Reserved. * *******************************************************************/ // The synopsys directives "translate_off/translate_on" specified // below are supported by XST, FPGA Express, Exemplar and Synplicity // synthesis tools. Ensure they are correct for your synthesis tool(s). // You must compile the wrapper file na_fifo16_256.v when simulating // the core, na_fifo16_256. When compiling the wrapper file, be sure to // reference the XilinxCoreLib Verilog simulation library. For detailed // instructions, please refer to the "Coregen Users Guide". module na_fifo16_256 ( clk, sinit, din, wr_en, rd_en, dout, full, empty); // synthesis black_box input clk; input sinit; input [15 : 0] din; input wr_en; input rd_en; output [15 : 0] dout; output full; output empty; // synopsys translate_off SYNC_FIFO_V3_0 #( 1, // c_dcount_width 0, // c_enable_rlocs 0, // c_has_dcount 0, // c_has_rd_ack 0, // c_has_rd_err 0, // c_has_wr_ack 0, // c_has_wr_err 1, // c_memory_type 0, // c_ports_differ 1, // c_rd_ack_low 1, // c_rd_err_low 16, // c_read_data_width 256, // c_read_depth 16, // c_write_data_width 256, // c_write_depth 1, // c_wr_ack_low 1) // c_wr_err_low inst ( .CLK(clk), .SINIT(sinit), .DIN(din), .WR_EN(wr_en), .RD_EN(rd_en), .DOUT(dout), .FULL(full), .EMPTY(empty), .RD_ACK(), .WR_ACK(), .RD_ERR(), .WR_ERR(), .DATA_COUNT()); // synopsys translate_on // FPGA Express black box declaration // synopsys attribute fpga_dont_touch "true" // synthesis attribute fpga_dont_touch of na_fifo16_256 is "true" // XST black box declaration // box_type "black_box" // synthesis attribute box_type of na_fifo16_256 is "black_box" endmodule i find 'MEM_BLK' in $xilinx\verilog\src\xilinxcore_lib\ SYNC_FIFO_V3_0.v how do i add `timescale commands in 'MEM_BLK' ?Article: 38174
In article <a1du97$1msc$1@agate.berkeley.edu>, Nicholas Weaver <nweaver@CSUA.Berkeley.EDU> wrote: >In article <651e62f3.0201071851.705fa51b@posting.google.com>, >Yu Jun <yujun@huawei.com> wrote: >>I notice a 128bit comparator is a timing-cost path in a FPGA. >>case2: A[127:0] > B[127:0] > >In order to do that style of comparison in the most efficient manner, >for unsigned, one performs A-B and sees the sign of the result. There >is no real way to shortuct this. I suppose a carry-skip/generate-carry tree is essentially a subtraction, however, it can be optimized more efficiently. Starting with the MSB - if the bits differ, the result is ready: carry-skip is zero, and 'generate' depends on the condition. If the bits match, carry-skip is a logical one and the next bit pair contributes to the output. The logic can be arranged as two parallel trees, whose leaves are either sign bits of regular carry-propagate subtractions of chosen length, or 2N-variable 'and' functions. -- Problems 1) do NOT write a virus or a worm program "A.K.Dewdney, The New Turing Omnibus; Chapter 60: Computer viruses"
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