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> Well, we didn't do the latter. We did the former. And, when a student > asked about how to use the phase shifter clock input there was no answer. Perhaps a part of the registration process should require the students to email the teacher a list of their most important questions, or list what they're hoping to learn. Then the teacher can say, "No, you won't get what you want from my class, so save your money and time," or "Yes, I'll be able to answer that at the class. I look forward to seeing you there." Then the teacher can better prepare the class to suit the needs of the students. Good point about efficiency. Of course if you put 10 Virtex-II Pros in each of your products, you might have enough volume to get a dedicated FAE ;_) --VinhArticle: 61501
Hi, I need to synchronize an incoming 27MHz signal (50% duty cycle) with an internal clock running at 108Mhz (which is 27*4, but the signals do not have a known phase relationship). The target technology is Spartan II-E. Is a simple 2-stage DFF synchronizer a safe way to handle this ? (I remember a Xilinx article stating that metastability can be ignored for clock rates < 200MHz). Many thanks, Guy.Article: 61502
I don't think you can ever ignore metastability. It will get up and bite you if you do. Simon "Guy Eschemann" <geschemann@yahoo.fr> wrote in message news:b9f16a5b.0310060044.4f3f135@posting.google.com... > Hi, > I need to synchronize an incoming 27MHz signal (50% duty cycle) with > an internal clock running at 108Mhz (which is 27*4, but the signals do > not have a known phase relationship). The target technology is Spartan > II-E. > > Is a simple 2-stage DFF synchronizer a safe way to handle this ? (I > remember a Xilinx article stating that metastability can be ignored > for clock rates < 200MHz). > > Many thanks, > Guy.Article: 61503
Quick question, is your 27 MHz signal a single bit line or a bus? If it's a single bit, I was taught that 2 stage FFs was "good enough," but I think it depends on how you're planning to use that single bit line. Is it merely some sort of status flag thing? It's not a data stream is it? Now if your 27 MHz signal is a bus, then you should consider using an asynchronus fifo (which I think Coregen has a core for that, or if not, i'm sure there's a reference design on Xilinx's website). The problem with using 2 stage FFs with a bus is that some bits might go metastable, and get delayed one cycle, while others don't, so the bits on your bus get misaligned. For example, if you have a 4-bit bus that transitions from a 0x0 to an 0xF, on the 108 MHz side you might see it go from 0x0 to 0xE then finally to 0xF. One important thing to keep in mind is that even if you have two "seperate" "single bit" signals coming in, you might have to treat them as a bus if they are related to each other. Again, it depends on how you're planning to use them. --VinhArticle: 61504
I believe the aclr just clears the output latch. In a FIFO it will also reset the counters. This is as good as clearing the ram as the FIFO will only output data it has already stored. In a ram you will need a state machine to clear the entire memory... that is unless you can handle unwritten locations. You might, however, be able to set up the ram as dual port.. one port with the 1kx4 or whatever you want, the other set to maximum width.. say 256x16. This means it can be cleared in a minimum of 256 clocks instead of 1024. Am not sure about the Cyclone.. BUT with the Xilinx it is only the output latch of the ram that is cleared.. this means the ram always returns 0x00 until it is released.. but you can still write to it.. this means you can background clear it while appearing to be clear on the second port. Someone might be able to say if this is true for the Cyclone too but I believe from what I have read it is so. Simon "Vazquez" <andres.vazquez@gmx.de> wrote in message news:eee19a7a.0310052333.cb7e111@posting.google.com... > Hello Mr Leventis, > > you said that to clear memory I have to iterate through it and write 0s. > In Cyclone Devices there is the possibility to create FIFO and RAM structures > by using the MegaWizard Manager. By doing so there is a signal called 'aclr'. > What function does this signal have in > a) FIFOs > b) RAMs ? > Is the content of the memory set to 0 or only the surrounding registers? > > Thank you very much > > Kind regards > Andrés Vázquez > G&D System Development > > > "Paul Leventis" <paul.leventis@utoronto.ca> wrote in message news:<rgAeb.22504$lKj.10858@news04.bloor.is.net.cable.rogers.com>... > > Hi Andres, > > > > The problem isn't your "writing" signal -- it is the asynchronous clearing > > of the memory. Memories are not clearable -- if you want to clear your > > memory, you must do so by iterating through it and writing 0s. > > > > Regards, > > > > Paul Leventis > > Altera Corp. > > > > > > > > "Vazquez" <andres.vazquez@gmx.de> wrote in message > > news:eee19a7a.0310010044.249af36e@posting.google.com... > > > Dear Mr Leventis, > > > > > > thank you for your answer. > > > > > > The problem of the QuartusII-Software-Compiler seems to be > > > the recognition of RAM-structures. > > > The following source code is synthesized using memory bits > > > when the signal writing is not used. > > > When the signal writing is used then QuartusII tries to synthesize > > > it without any memory bits. > > > Where could be the problem in the use of the signal writing? > > > > > > Kind regards > > > Andrés > > > G&D System Development - FPGA design > > > > > > > > > ------------------------------------------------- > > > ------------------------------------------------- > > > LIBRARY ieee; > > > USE ieee.std_logic_1164.ALL; > > > > > > PACKAGE test_ram_package IS > > > > > > CONSTANT ram_width : INTEGER := 8; > > > CONSTANT ram_depth : INTEGER := 2048; > > > > > > TYPE word IS ARRAY(0 to ram_width - 1) of std_logic; > > > TYPE ram IS ARRAY(0 to ram_depth - 1) of word; > > > SUBTYPE address_vector IS INTEGER RANGE 0 to ram_depth - 1; > > > > > > CONSTANT xram_width : INTEGER := 12; > > > CONSTANT xram_depth : INTEGER := 16; > > > > > > TYPE xword IS ARRAY(0 to xram_width - 1) of std_logic; > > > TYPE xram IS ARRAY(0 to xram_depth - 1) of address_vector; > > > SUBTYPE xaddress_vector IS INTEGER RANGE 0 to xram_depth - 1; > > > > > > END test_ram_package; > > > > > > LIBRARY ieee; > > > USE ieee.std_logic_1164.ALL; > > > USE ieee.std_logic_arith.ALL; > > > USE ieee.std_logic_unsigned.ALL; > > > USE work.test_ram_package.ALL; > > > > > > > > > ENTITY test_inferred_ram IS > > > PORT > > > ( --reset : IN std_logic; > > > clock1 : IN std_logic; > > > clock2 : IN std_logic; > > > data : IN word; > > > write_address: IN address_vector; > > > read_address: IN xaddress_vector; > > > write_xaddress : IN xaddress_vector; > > > xdata : IN address_vector; > > > we : IN std_logic; > > > q : OUT word > > > ); > > > END test_inferred_ram; > > > > > > ARCHITECTURE rtl OF test_inferred_ram IS > > > > > > > > > SIGNAL ram_block : RAM; > > > SIGNAL xram_block : XRAM; > > > SIGNAL read_address_reg : xaddress_vector; > > > SIGNAL writing : std_logic; > > > > > > BEGIN > > > > > > PROCESS (clock1) > > > BEGIN > > > --IF reset='1' then > > > -- ram_block <= (others => (others=>'0')); > > > -- xram_block <= (others=>0); > > > -- writing <= '0'; > > > IF (clock1'event AND clock1 = '1') THEN > > > IF (we = '1' and writing='0') THEN > > > ram_block(write_address) <= data; > > > xram_block(write_xaddress) <= xdata; > > > writing <= '1'; > > > ELSIF (we='1' and writing='1') then > > > ram_block(write_address) <= data; > > > xram_block(write_xaddress) <= xdata; > > > writing <= '0'; > > > END IF; > > > END IF; > > > END PROCESS; > > > > > > PROCESS (clock2) > > > BEGIN > > > IF (clock2'event AND clock2 = '1') THEN > > > q <= ram_block(xram_block(read_address_reg)); > > > read_address_reg <= read_address; > > > END IF; > > > END PROCESS; > > > > > > END rtl;Article: 61505
> (I remember a Xilinx article stating that metastability can be ignored > for clock rates < 200MHz). It might be a good idea to see what situation that < 200 MHz thing applies to. Metastability can happen at any frequency. Say you have just a 1 Hz signal that you're resynching to just a 2 Hz clock. If the phase relationship is just right, your FFs can go metastable all the time. Besides, bugs caused by metastability are a pain to track down. If you're unlucky, they'll occur with the customer's equipment, but not with the one in your lab. Worse yet, when you pay to ship the customer's equipment back to your lab, the bug mysteriously disappears. Prevention is far more valuable than a cure, in this case. :_) --VinhArticle: 61506
naveen wrote: > Hi, > But if the host frequency is different from pci frequency we need > to keep asynchronous fifo, i guess. Am i true? In that case do we need > totally 4 fifos? Yes, asynchronous clocks complicate the design substantially, especially in view of metastability issues. But two buffers (one upstream and one downstream) should be sufficient. The only thing you have to take care for is to avoid deadlock-conditions during simultaneous access-attempts from both sides. > Also, can i get any document of implementation for host-pci bridge on > net? I searched but unable to find out. I don't know whether there is a documentation as such available. However, a host bridge is not some general thing as it's requirements depend heavily on the host bus. Consider to have a look inside the PCI-to-PCI bridge spec. There you might find important hints for general bridge design. > In case of configuration transactions in host-pci bridge how will be > the flow? Actually, there is no special requirement. The PCI spec (2.1s) specifies two modes for "normal" PC systems: A mode with a few control registers (easy to implement) and a mode with IO-mapping (a little bit more difficult). But generally it is left open how one implements a mechanism for generating those transactions. Regards, MarioArticle: 61507
hmurray@suespammers.org (Hal Murray) writes: > >I overuse the syn_keep attribute and I hate the idea of instantiating > >LUTs. My Carnot skills aren't exactly used regularly. > > Are Carnot skills needed? Not unless you're building a heat engine out of your FPGA... Homann -- Magnus Homann, M.Sc. CS & E d0asta@dtek.chalmers.seArticle: 61508
On Mon, 6 Oct 2003 09:27:25 +0200, "Morten Leikvoll" <m-leik@online.nospam> wrote: >My collegue and I discussed how our placer (xilinx's) handled going from 1x >clocks to 2x clocks and back. (These have of course common rising edge) > >For this example I use a 100Mhz clock and a 200Mhz clock: > >There are 3 ways of doing this: > >1 (based on the timing of the previous ff's output ) >2 (based on the input timing) >3 (based on the lowest delay of input and previous output) >How DOES the placer tool handle this? How about... 4. Based on your own explicit timing constraints, defined in the UCF file, applied to TIMEGRPs defined by you, to include all the domain-crossing signals? - BrianArticle: 61509
On Sun, 05 Oct 2003 17:52:58 GMT, "Martin Euredjian" <0_0_0_0_@pacbell.net> wrote: >"Paul Leventis" wrote: > >I appreciate your opinion. And thanks for jumping in. > >> I must say, as an FPGA software developer I disagree with most of what you >> have to say. Altera (and I'm sure Xilinx too) has 100's of sw engineers >> banging on the software at any given time. > >Somehow I have more faith in third parties doing a better job. >> Now, you can argue this means we've brought the software up to "adequate" >> levels. But then why would we be constantly adding new features and >> improving tool quality? We feel the competitive pressure -- even in a >> two-horse race you have to gallop as fast as you can. > >But you still only have two horses. How many people tried to build a >powered flying machine? People with lots of money and resources failed >miserably. Yet, a couple of bicycle makers hell-bent to make it happen did. As a couple of bicycle makers, we can tap into (for Xilinx anyway) pretty much every detail of the design with or without placement and routing information, using XDL format (is XDL still supported in the latest tool chain?), which is plain text and doesn't look too difficult to parse. Therefore the way is open to us to develop hierarchical floorplanning or advanced routing tools, using XDL format, converting between NCD and XDL to go to and from the Xilinx toolchain. The last little step, the fairly mechanical conversion of NCD to bitstream, remains under Xilinx control for reasons/excuses (according to POV) that have been discussed here before. But that's not the "interesting" part of the problem, where performance can be won or lost. So far, I haven't seen any great rush to use this facility, and (cough) haven't had/made/found any time to do so myself... - BrianArticle: 61510
"Brian Drummond" <brian@shapes.demon.co.uk> skrev i melding news:87m2ovk1sgk2acqt19s6udrbg8uu57adi4@4ax.com... > How about... > > 4. Based on your own explicit timing constraints, defined in the UCF > file, applied to TIMEGRPs defined by you, to include all the > domain-crossing signals? That was the solution, but still I'd like to know how it's done without manually placing the constraint.Article: 61511
Morten Leikvoll wrote:
> My collegue and I discussed how our placer (xilinx's) handled going from 1x
> clocks to 2x clocks and back. (These have of course common rising edge)
>
> For this example I use a 100Mhz clock and a 200Mhz clock:
>
> There are 3 ways of doing this:
>
> 1 (based on the timing of the previous ff's output ) Signals coming from 1x
> to 2x will be routed with max 10ns delay. This means that you can not tell
> wether the signal will appear at the 2x at the 5ns or 10ns rising 2x clock.
>
> 2 (based on the input timing) Signals coming from 2x to 1x will be routed
> with max 10ns delay. This means that the output can sometimes skip the first
> 1x edge.
>
> 3 (based on the lowest delay of input and previous output) This works, but
> my collegue claims this tool doesn't do it this way. Can anyone confirm this
> is the case?
>
> How DOES the placer tool handle this?
Howdy Morten,
Ask your colleague how would he would be able to guarantee the design to
work under all conditions if you have the situations described in
options 1 and 2. Especially if there is more than the bus taking part
in the domain crossing.
The answer, of course, is option 3. But you don't have to take my word,
or the word of anyone else. It is easy to set this up yourself in a
couple lines of code, run it through PAR, and then run timing analyzer
on it.
Have fun,
Marc
Article: 61512On 6 Oct 2003 01:44:54 -0700, geschemann@yahoo.fr (Guy Eschemann) wrote: >Hi, >I need to synchronize an incoming 27MHz signal (50% duty cycle) with >an internal clock running at 108Mhz (which is 27*4, but the signals do >not have a known phase relationship). The target technology is Spartan >II-E. See Vinh's response in regard to whether this 27MHz thing is one or more signals. For a better understanding on Metastability, I recommend: http://www.fpga-faq.com/FAQ_Pages/0017_Tell_me_about_metastables.htm >Is a simple 2-stage DFF synchronizer a safe way to handle this ? This MAY be sufficient. The primary requirement is that there be maximum possible slack time in the path between the two FFs that make up your synchronizer. At 108MHz, the cycle time is about 9.25ns. If the first FF has a clock to output delay of .5 ns, and the second FF has an input setup time of .5 ns, and the max delay of the routing between them is 1ns, then you have a slack of 7.25ns. A 3 stage synchronizer would effectively have double this slack time (2 x 7.25ns) , but would add another cycle of latency. If you don't control the routing delay, your efforts may be wasted. For example, if you set a the timespec to 9ns for this path, the current Xilinx router will stop optimizing the path as soon as it has met this requirement, and you will have a miserable synchronizer because the slack time will be far less than 7.25 ns. Maybe as little as .25ns . You need to set specific timespecs that cover this critical path, and set it far more aggressively than the clock frequency would indicate. I would recommend a target of 3 ns for the path, which if the spec is met, will give you at least 6 ns of slack. The most useful thing you can do to help the tools is to put placement constraints on the two FFs of the synchronizer, and place them in the same CLB. This makes it far easier to meet the aggressive timespec that you must also specify. >(I remember a Xilinx article stating that metastability can be ignored >for clock rates < 200MHz). This is NEVER (absolutely, categorically NEVER) true. (can you remember which article you saw this in? >Many thanks, >Guy. Well designed synchronizers are your friend! Philip Philip Freidin FliptronicsArticle: 61513
jon@beniston.com (Jon Beniston) wrote in message news:<e87b9ce8.0310030831.39ab6933@posting.google.com>... > Goran Bilski <goran@xilinx.com> wrote in message news:<blj44a$hht2@cliff.xsj.xilinx.com>... > > Hi, > > > > The register file is included in that number. > > > > Göran > > Thanks. One other question, is it a pure RTL design or does it > instantiate Xilinx specific primitives? Ditto for NIOS? it is 99.99 xilinx stuff inside, and its all encrypted files so you cant even see whats inside. NIOS is on demand generated by a large PERL framework called Europe, get Alter EPP (Embedded Processor Portfolio) and dig into the PERL sources if interested in deepinfo :) anttiArticle: 61515
It appears that Xilinx does not care to discuss their models. rickman <spamgoeshere4@yahoo.com> wrote in message news:<3F7B1765.D691F1C5@yahoo.com>... > lecroy wrote: > > > Look at the IBIS simulation at the output pin to see what the voltage excursions are, an be sure they stay > > > within the specifications sheet and user's guide. > > > > Well, not like Mr. Pease, I have always been a big user of simulation > > as one tool. Certainly, not the last tool and I don't see it > > replacing the VNA any time soon as a way to get the 'real' picture of > > what is going on. But the question I always have when some one throws > > out the simulation card is how good is your model. When Xilinx > > released the IBIS models for the S3, how much data was it based upon? > > Have they continued to update the model as parts are being tested? > > How much do you trust it? > > That is a *very* important question. We have seen the timing files go > through iteration after iteration of refinement. At what point can be > believe that the IBIS models will be stable? > > > > > If you have a specific waveform, you may email it to me directly, and I will get the "final word" from the > > > designers and technology groups. > > > > Do I have a specific waveform, no. I am asking a general question > > about the S3. Just how sensitive it really is and what precautions do > > I need to take to make it work. Because each layout is different, the > > loading can be anything if you consider all of the failure modes. > > -- > > Rick "rickman" Collins > > rick.collins@XYarius.com > Ignore the reply address. To email me use the above address with the XY > removed. > > Arius - A Signal Processing Solutions Company > Specializing in DSP and FPGA design URL http://www.arius.com > 4 King Ave 301-682-7772 Voice > Frederick, MD 21701-3110 301-682-7666 FAXArticle: 61516
Hi, I am trying to fit this particular design. I run Synplify Pro to map the device. In Synplify, with mapping logic to atoms turned on, the design won't fit so I disable mapping logic to atoms and can get the design to fit (63 % of device) onto the device....see log file from synplify below. However, when I try to place and route the device in Quartus III, it cannot fit. Quartus uses the same project directory as Synplify so it has access to all constraints and tcl files. Can anybody shed any light on this subject. I have used Synplify in conjunction with Quartus before and the resource useage results from both are nearly always about the same. Why the large discrepency ? Do I manually need to read in some tcl files or have I forgotten to switch on a particular option in Quartus ? As always, thanks for any help Bob Found clock clk with period 33.3333ns --------------------------------------- Resource Usage Report Final cell packing will be performed by Max+plus II. Please select a Logic synthesis style of "FAST" in Max+plus II. The following resource values are estimates. Design view:work.comms(comms_architecture) Selecting part ep20k1000efc33-1 Logic resources: 24440 ATOMs of 38400 (63%) Number of Nets: 190215 Number of Inputs: 1298480 Register bits: 14312 (4094 using enable) Latch bits: 8106 ESBs: 0 (0% of 160) I/O cells: 0 Details: AND2: 8298 INV1: 3879 MUX1: 5834 SYNLPM_LAT1: 16356 S_DFF: 10218 S_DFFE: 4113 XOR2: 291 apex20k_lcell: 77185 apex20k_lcell_ff: 19 false: 7 inv: 9189 true: 7 Number of Inputs on ATOMs: 1298480 Number of Nets: 190215 Writing .vqm output for Quartus Writing Cross reference file for Quartus to c:\comms_vhdl\rev_1\comms.xrf Mapper successful! Process took 7284.92 seconds realtime, 7284.92 seconds cputimeArticle: 61517
> > Two LUT's to look at two consecutive nibbles. > > One LUT to AND the output of the above with the next most significant bit > > (the ninth bit). > > That's it. Two levels. 24 LUT's. > > Is that what you wanted? > > Almost. The LUTs can't look at full nibbles. Since I need to make > sure all bits are equal to each other, there's a "smear." You can look at nibbles without the smear. If you know that all bits in each of the nibbles are equal you can select one bit for each nibble as a representant and check whether the nibbles are equal. for each byte: eq3210 <= '1' when data(3 downto 0) = "0000" or data(3 downto 0) = "1111" else '0'; eq7654 <= '1' when data(7 downto 4) = "0000" or data(7 downto 4) = "1111" else '0'; eq840 <= '1' when data(8)&data(4)&data(0) = "000" or data(8)&data(4)&data(0) = "111" else '0'; run_found <= eq3210 and eq7654 and eq840; That's three lut's and a carry chain or four luts in two levels of logic. Kolja SulimmaArticle: 61518
As Vinh says, once you have more than one related signal that you need to synchronize, the two flop method breaks down. Have look at the following tutorial/paper that describes various ways to handle asynchronous design. I've posted it before, but it never hurts to do so again... www.sunburst-design.com/papers/CummingsSNUG2001SJ_AsyncClk_rev1_1.pdf - Paul Leventis Altera Corp.Article: 61519
Bob,
I assume the first experiment was run with Quartus II 2.2 (the one where
it fit without atoms), and the second one was in Quartus II 3.0. As a rule
of thumb using the atom (vqm) netlist should give fairly close results in
the two versions of Quartus, assuming you are optimizing for area (lcell
count) or speed in both cases inside Quartus.
You may want to run one more experiment. Use the vqm netlist, and in Quartus
II 3.0
1. Set WYSIWYG Primitive resynthesis (aka atom resynthesis) to on. You can
do this from the Assignments->Settings->Compiler Settings->Netlist
Optimizations dialog. This will make Quartus take the vqm netlist, convert
it to a gate level netlist and synthesize it further.
2. Next set the Optimization Technique to Area. You can do this from the
Assignments->Settings->Default Logic Option Settings->Optimization
Technique - APEX20K/APEX20K... to Area.
3. Set Register Packing to off. You can do this from the
Assignments->Settings->Default Logic Option Settings->Auto Packed Register
Settings list box. Register Packing can sometimes hurt fiting in the APEX
architectures.
4.Compile this design with Quartus II 3.0 and check the results.
If this works turn off the setting in Step 1 and follow recompile the
design.
- Subroto Datta
Altera Corp.
"Bob" <stenasc@yahoo.com> wrote in message
news:20540d3a.0310060457.37847daf@posting.google.com...
> Hi,
>
> I am trying to fit this particular design. I run Synplify Pro to map
> the device.
> In Synplify, with mapping logic to atoms turned on, the design won't
> fit so I disable mapping logic to atoms and can get the design to fit
> (63 % of device)
> onto the device....see log file from synplify below.
>
> However, when I try to place and route the device in Quartus III, it
> cannot fit.
> Quartus uses the same project directory as Synplify so it has access
> to all constraints and tcl files. Can anybody shed any light on this
> subject. I have used Synplify in conjunction with Quartus before and
> the resource useage results
> from both are nearly always about the same. Why the large discrepency
> ?
>
> Do I manually need to read in some tcl files or have I forgotten to
> switch on
> a particular option in Quartus ?
>
> As always, thanks for any help
> Bob
>
>
>
>
>
>
> Found clock clk with period 33.3333ns
> ---------------------------------------
> Resource Usage Report
>
> Final cell packing will be performed by Max+plus II.
> Please select a Logic synthesis style of "FAST" in Max+plus II.
> The following resource values are estimates.
>
> Design view:work.comms(comms_architecture)
> Selecting part ep20k1000efc33-1
>
> Logic resources: 24440 ATOMs of 38400 (63%)
> Number of Nets: 190215
> Number of Inputs: 1298480
> Register bits: 14312 (4094 using enable)
> Latch bits: 8106
> ESBs: 0 (0% of 160)
> I/O cells: 0
>
> Details:
> AND2: 8298
> INV1: 3879
> MUX1: 5834
> SYNLPM_LAT1: 16356
> S_DFF: 10218
> S_DFFE: 4113
> XOR2: 291
> apex20k_lcell: 77185
> apex20k_lcell_ff: 19
> false: 7
> inv: 9189
> true: 7
>
> Number of Inputs on ATOMs: 1298480
> Number of Nets: 190215
>
> Writing .vqm output for Quartus
> Writing Cross reference file for Quartus to
> c:\comms_vhdl\rev_1\comms.xrf
> Mapper successful!
> Process took 7284.92 seconds realtime, 7284.92 seconds cputime
Article: 61520"Morten Leikvoll" <m-leik@online.nospam> wrote in message news:<5z9gb.28389$os2.397003@news2.e.nsc.no>... > I just started reading this thread.. Am I correct if you really want to > detect 9 EQUAL bits in a row from a stream? > Could you not do this just with a 4bits counter and a comparator/zero > detector? Correct, I need "equal" bits, either 9'h000 or 9'h1ff, starting from 0, 8, 16, ... 56. The input is 65 bits per clock with a fast clock, output from BlockRAM which was loaded at full width. Counters require more than one clock.Article: 61521
My 27 MHz signal is a single bit line, not a bus. Actually it is the clock line for an 8-bit video data stream. My problem is to synchronize this incoming data stream with the 108MHz system clock. I know I could be using an asynchronous FIFO for this, but this might be overkill. In order to save resources, wouldn't it be better to synchronize the 27 MHz clock with my system clock (2-stage pipeline should do the job), then use some logic to detect the appropriate edge and use the output of the edge detector as a clock enable signal for the input data FFs, which are clocked by the system clock ? Regards, Guy. "Vinh Pham" <a@a.a> wrote in message news:<ONagb.26378$Ak3.15511@twister.socal.rr.com>... > Quick question, is your 27 MHz signal a single bit line or a bus? > > If it's a single bit, I was taught that 2 stage FFs was "good enough," but I > think it depends on how you're planning to use that single bit line. Is it > merely some sort of status flag thing? It's not a data stream is it? > > Now if your 27 MHz signal is a bus, then you should consider using an > asynchronus fifo (which I think Coregen has a core for that, or if not, i'm > sure there's a reference design on Xilinx's website). The problem with > using 2 stage FFs with a bus is that some bits might go metastable, and get > delayed one cycle, while others don't, so the bits on your bus get > misaligned. For example, if you have a 4-bit bus that transitions from a > 0x0 to an 0xF, on the 108 MHz side you might see it go from 0x0 to 0xE then > finally to 0xF. > > One important thing to keep in mind is that even if you have two "seperate" > "single bit" signals coming in, you might have to treat them as a bus if > they are related to each other. Again, it depends on how you're planning to > use them. > > > --VinhArticle: 61522
I have developed the PCI-device for which it is necessary 128 bytes of
ports of input-output, 512 Kb of memory and one interrupt.
When I install 4 devices simultaneously, BIOS allocates for them
necessary resources, windows 98 allocates resources only for 3
devices.
And Windows XP at all it does not want to be loaded ("Blue screen"
before installation of drivers).
Article: 61523
Guy Eschemann wrote:
> My 27 MHz signal is a single bit line, not a bus.
> Actually it is the clock line for an 8-bit video data stream. My
> problem is to synchronize this incoming data stream with the 108MHz
> system clock.
>
> I know I could be using an asynchronous FIFO for this, but this might
> be overkill. In order to save resources, wouldn't it be better to
> synchronize the 27 MHz clock with my system clock (2-stage pipeline
> should do the job), then use some logic to detect the appropriate edge
> and use the output of the edge detector as a clock enable signal for
> the input data FFs, which are clocked by the system clock ?
At the risk of proposing something you've already thought of, is there
really no way to use the 108 MHz clock in the FPGA as the source of the
27 MHz clock that video data source uses, so that there is a known phase
relationship between the two? If you can swing that, they'll be in the
same domain and all you have to worry about is a non-varying setup time.
Marc
Article: 61524Theron, Martin, We have a number of folks actively researching this issue, The class mentioned turns out to be one of the most popular (from what the surveys from the attendees say), and the one that gets very high marks from the attendees also. The instructor has taught this (as well as other courses) for 6 years, and also gets very high marks in his reviews. It is extrememly important to us to discover what happened in this case, as it seems very unusual, and not in keeping with the survey results, and comments from other attendees. One bad review posted here does a lot of damage: and we are concerned especially when we have hundreds of glowing reviews for the same class/instructor! Austin "Theron Hicks (Terry)" wrote: > I agree with Martin! I can't speak for the classes, but the rest is definitely > true. I hope someone at Xilinx is listening. There is no doubt (at least in my > mind) that Xilinx has some great FPGAs, etc. The software seems to be fairly > well done, although it could use some improvement. The area of improvement is > in simple, useable documentation. If I need to check three or for different > areas for a full picture of what it taakes to get a job done, can you at least > create a link between the areas. Xilinx could save a bundle in tech support, if > they would just improve the documentation. It might even get them a few more > customers. It generally is not a good idea to PO the customer. (Usually Xilinx > does not do that.) > > Theron Hicks > > Martin Euredjian wrote: > > > Maybe so. Hart to tell at this point. Certainly the material in the book > > would open the door to very interesting and useful discussion of advanced > > topics, none of which were explored, some were recited, others skipped over. > > > > I think there are two groups within your company that might need a flame > > (not a match) lit under their chairs: web design and > > education/documentation. > > > > The website can be incredibly retarded and just not up to par with what good > > website design folks can do today. Sure, it's expensive to hire these heavy > > hitters, but Xilinx can afford it. > > > > I only have one sample of the education group's output and, as you learned, > > they didn't put on a good show as far as I am concerned. > > > > I think there are huge gaping holes in the available documentation and > > devices are getting increasingly more complex. I think there's a need to > > address this --by experts, not fresh grads-- and it's not being done. > > > > Some of these topics might include floorplanning, design optimization, > > timing optimization, FPGA Editor, design flow optimization and automation > > (XFLOW, scripting, command-line tricks, etc.). I'm not talking about being > > able to download a document describing the various available timing > > constraints, for example, but a practical, in-the-trenches set of docs > > treating these topics in order to support designers in both adopting and > > succesfully utilizing these devices in an already difficult marketplace. > > > > Within the next few months I'll probably have a need to hire a couple of > > FPGA/Embedded guys, and the realization that I can't seem to rely on even > > sending them to a manufacturer-provided course in order to enhance their > > ability to generate accurate designs that perform well is what triggered > > some of my concern. > > > > Still, this is not a Xilinx putdown but rather costructive criticism. I > > love the chips and will probably continue to use them for a long time. I > > have over half a dozen high-performance imaging products in the works and, > > at this point, all of them have Xilinx FPGA's in them. > > > > -- > > ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ > > Martin Euredjian > > > > To send private email: > > 0_0_0_0_@pacbell.net > > where > > "0_0_0_0_" = "martineu" > > > > "Austin Lesea" <Austin.Lesea@xilinx.com> wrote in message > > news:3F7DB8E8.A11339E0@xilinx.com... > > > Martin, > > > > > > I am sorry you had a bad experience. > > > > > > I will ask about it. I had heard from others that this particular course > > was a > > > good one (some of my own staff have taken it), so I am hoping that your > > > experience was not the course, but perhaps the instructor (still > > unfortunate, > > > and not acceptable). > > > > > > Austin > > > > > > Martin Euredjian wrote: > > > > > > > I recently took the "Advanced FPGA Implementation (v6)" Instructor-Led > > > > Course and came out of it with a fair bit of dissappointment. I don't > > want > > > > to engage in Xilinx-bashing but it bothers me that the course was simply > > not > > > > worthy of the title it was given. > > > > > > > > The only reason I might get something out of it will be because I will > > pour > > > > over the 500 page book on my own and experiment for many, many hours. > > The > > > > class boiled down to a bunch of slides (a very small subset of the book, > > > > maybe 20%) being read out loud with a degree of re-interpretation. The > > labs > > > > were based on an obscure design that was not introduced at all. So, all > > you > > > > could do in the alloted time was type from the book like a robot and > > move > > > > on. No real learning took place there. > > > > > > > > I took the course because, after a two-year effort --starting from > > scratch-- > > > > to learn FPGA's, I thought that an advanced course taught by an expert > > in > > > > the field would be a great way to take my skills up a notch or two. I > > > > needed to get to that proverbial last few percent and, frankly, I also > > felt > > > > stuck with regards to timing optimization, floorplanning and other > > advanced > > > > areas. I thought that an "advanced" course would be taught by a peer > > who'd > > > > offer the sort of insight that only comes from significant experience in > > the > > > > field and, yes, inside information. That is certainly not what > > happened. I > > > > can read slides just as well as the next guy. I don't need to pay > > $1,000, > > > > travel and burn two days' work to endure that experience. > > > > > > > > So, I wonder. Was this a fluke? Are the other coursed different, > > better, > > > > worst? Are Altera's courses better? It seems that Xilinx contracts out > > the > > > > trainig to a third party (a company called "Technically Speaking". I > > heard > > > > that Altera chooses to use insiders. Is this true? Does it make a > > > > difference? > > > > > > > > Thanks, > > > > > > > > -- > > > > ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ > > > > Martin Euredjian > > > > > > > > To send private email: > > > > 0_0_0_0_@pacbell.net > > > > where > > > > "0_0_0_0_" = "martineu" > > >
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