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> Which IC vendors supply MPEG1 or MPEG2 hardware chips? Many companies... LSI (http://www.lsilogic.com), National Semiconductor (www.national.com), Broadcom (www.broadcom.com), Zoran (www.zoran.com), are just a few. If you're just looking for a decoder-only (like a DVD-playback chipset or a HD-MPEG2 decoder), you can www.esstech.com, www.mediatek.com.tw, www.teralogic.com, www.mediamatics.com (I think they're part of National Semiconductor). I'm pretty sure a number of Japanese conglomerates make these things, but many only develop the chipsets for internal divisions, and don't sell them to third-parties. (Sony, Panasonic, Toshiba, NEC, come to mind...)Article: 50026
Where can I find low cost 3rd party Xilinx j-tag programmer? I have found low cost programmers for Altera, but not Xilinx. Does anyone know where I can find one that is compatible with Xilinx's DLC-7 programmer? Thanks, Ryan Frnaklin rfrank1234@aol.comArticle: 50027
Hello, I bought a Spartan-II 2S200 PCI (Develompent) Board from Insight Memec. Initaially I have discussed with them to develop on 2S200-PQ208 chip but they delivered me a board based on 2S200-FG456-6C. Now I observed in the the Implementation.pdf from Xilinx that Xilinx PCI IP does not support the chip 2S200-FG456-6C which is on our board... Does anyone know if it is possible or not really to use Xilinx PCI IP? Does other PCI IP exists for this card? Or I put in in the trash... The Insight Support didn't fix this issue in two weeks of calls...and I spent a lot of effort without any progress. Thank you for your attention. CatalinArticle: 50028
For CPLDs the fit might be decent using the rate multiplier. I'm not a fan of producing HDL that isn't simple to understand but once a function is put together and works well, there's no reason not to add it to the toolbox, particularly if it's a parameterized module giving you arbitrary width at a whim. I do stand by my suggestion that for FPGAs with integral carry chains, the benefits of readability, functionality, and resources work better with an accumulator approach. The comment that the binary rate multipler "is more difficult to code with today's HDLs" stems from not having any visual clues as to what the function is doing. Your code segment (thanks for including that) looks like it would work well with a generate construct which might improve the comprehension of the functionality, reducing my bias. Having once implemented a binary rate multiplier on a CPLD, I found that I much preferred the simple approach behind the DDS phase accumulator, especially since a clean sinewave could be produced with an external D/A if one wanted to go that far. A digital result with 1 master cycle of jitter peak-to-peak is beautiful for so many applications. The binary rate multiplier's jitter characteristics get uglier but indeed have their place. "Jim Granville" <jim.granville@designtools.co.nz> wrote in message news:3DE513FC.31A9@designtools.co.nz... > John_H wrote: > > > > Binary rate multipliers don't fit nearly as well into current FPGAs as do > > accumulator based approaches. > <snip> .... and is more difficult to code with today's HDLs. > > Both are valid design approaches, but the comments above I find > hard to follow : > > This is the engine of a 10 bit Rate Multiplier (in CUPL ) : > > fSUM.d = (fSet0 & RmC9 & !RmC8 & !RmC7 & !RmC6 & !RmC5 & !RmC4 & !RmC3 & > !RmC2 & !RmC1 & !RmC0 ) > # (fSet1 & RmC8 & !RmC7 & !RmC6 & !RmC5 & !RmC4 & !RmC3 & !RmC2 & > !RmC1 & !RmC0) > # (fSet2 & RmC7 & !RmC6 & !RmC5 & !RmC4 & !RmC3 & !RmC2 & !RmC1 & > !RmC0) > # (fSet3 & RmC6 & !RmC5 & !RmC4 & !RmC3 & !RmC2 & !RmC1 & !RmC0 ) > # (fSet4 & RmC5 & !RmC4 & !RmC3 & !RmC2 & !RmC1 & !RmC0 ) > # (fSet5 & RmC4 & !RmC3 & !RmC2 & !RmC1 & !RmC0 ) > # (fSet6 & RmC3 & !RmC2 & !RmC1 & !RmC0 ) > # (fSet7 & RmC2 & !RmC1 & !RmC0 ) > # (fSet8 & RmC1 & !RmC0 ) /* 256 pickets -> 25% freq, etc */ > # (fSet9 & RmC0 ) /* 512 pickets -> 50% Freq */ > ; > > Surely this does not challenge 'today's HDLs' ? > > We use Rate Multipliers in CPLDs, because they need LESS resource than > Accumulators. > The OP did not say if he targeted FPGA or CPLD. > > -jgArticle: 50029
I want to utilize the PowerPC core of VertexII Pro in a system, but I get confused by those documents on Xilinx Website. They seems tend to introduce the architecture of PowerPC itself, instead of how to use it. I would appreciate if anyone can tell me what HW/SW kits on earth I need to build/simulate/debug a PowerPC system on Vertex II pro. Thanks a million, HuaArticle: 50030
"A. Karen Alfke" <karen@2ndesign.com> wrote in message news:<3DE655F4.8F2FFB91@2ndesign.com>... > > Sorry for the late response. > I strongly believe that your problem was due to the difference in > capture time between the two signals, not at all to metastability. > Metastabilty resolves faster when the gain-bandwidth product of the > master-latch feedback loop is higher. > That means it resolves faster at low temperature! (Contradicting your theory) > I did not vary temperature, but varied Vcc instead. Changing Vcc is so > much simpler than changing temperature ! > High Vcc is equivalent to low temperature or fast processing. > Low Vcc is equivalent to high temperature or slow processing. > > Metastability is very often blamed for completely unrelated sins. > Synchronizing an asynchronous input in more than one flip-flop is the > most common deadly sin. > > Peter Alfke, Xilinx Applications When you say, that varying Vcc is the same as varying temperature you opinion is based on some theory. The theory may be right or wrong. For example, your theory doesn't take into account the influence of thermal noise and/or tunneling on metastabilty resolving time. Put your circuit into a thermostat and measure. Draw tau over temperature curve. Then you would know the answer based on facts. Of course it's easier to say than to do, because slack time doesn't remain constant too, but I believe you're able to find a solution for this problem.Article: 50031
Catalin wrote:
>
> Hello,
>
> I bought a Spartan-II 2S200 PCI (Develompent) Board from Insight
> Memec. Initaially I have discussed with them to develop on 2S200-PQ208
> chip but they delivered me a board based on 2S200-FG456-6C. Now I
> observed in the the Implementation.pdf from Xilinx that Xilinx PCI IP
> does not support the chip 2S200-FG456-6C which is on our board...
>
It sounds to me, you would have preferred if you were able to
purchase the older Insight Electronics Spartan-II 150 PCI Development
Kit which used Spartan-II XC2S150-5CPQ208.
Unfortunately, that board was discontinued six or more months ago.
If you put up a wanted posting for Spartan-II 150 PCI Development Kit
within this newsgroup, someone might sell you one.
Regarding Xilinx LogiCORE PCI, the Insight Electronics
Spartan-II 200 PCI Development Kit comes with a UCF file for
XC2S200-xCFG456.
Go to their reference design section to download the reference design
that contains the UCF file.
http://208.129.228.206/solutions/reference/xilinx/reference.shtml
> Does anyone know if it is possible or not really to use Xilinx PCI IP?
> Does other PCI IP exists for this card? Or I put in in the trash...
> The Insight Support didn't fix this issue in two weeks of calls...and
> I spent a lot of effort without any progress.
>
> Thank you for your attention.
>
> Catalin
Yes, it is possible to use the Insight Electronics Spartan-II
PCI Development Kit without Xilinx's LogiCORE PCI.
I did develop my own PCI IP core, and used Insight Electronics
Spartan-II 150 PCI Development Kit to test it to see if it will actually
work when plugged into a real computer.
I also heard that Opencores.org PCI IP core project used the same PCI
card to test their PCI IP core.
Other than what I just wrote, I don't know anyone else actively selling
a PCI IP core for Xilinx.
Kevin Brace (If you want to respond to what I wrote, I prefer if you
will do so within the newsgroup.)
Article: 50032Michael S wrote: >" > When you say, that varying Vcc is the same as varying temperature you > opinion is based on some theory. The theory may be right or wrong. For > example, your theory doesn't take into account the influence of > thermal noise and/or tunneling on metastabilty resolving time. > Put your circuit into a thermostat and measure. Draw tau over > temperature curve. Then you would know the answer based on facts. > Of course it's easier to say than to do, because slack time doesn't > remain constant too, but I believe you're able to find a solution for > this problem. Nice to get helpful advice from the real experts... Thanks! Peter AlfkeArticle: 50033
Kevin Brace <kev3inbrac5eusen7et@ho9tmail.c1om> wrote: ... : Yes, it is possible to use the Insight Electronics Spartan-II : PCI Development Kit without Xilinx's LogiCORE PCI. : I did develop my own PCI IP core, and used Insight Electronics : Spartan-II 150 PCI Development Kit to test it to see if it will actually : work when plugged into a real computer. : I also heard that Opencores.org PCI IP core project used the same PCI : card to test their PCI IP core. : Other than what I just wrote, I don't know anyone else actively selling : a PCI IP core for Xilinx. Kevin, you have talked so often about your PCI core. What do you do with the core? Is it only for a closed project of yours, do you sell it or do you even offer it for free? I am thinking about to take a plinge into the opencore PCI module... Thanks -- Uwe Bonnes bon@elektron.ikp.physik.tu-darmstadt.de Institut fuer Kernphysik Schlossgartenstrasse 9 64289 Darmstadt --------- Tel. 06151 162516 -------- Fax. 06151 164321 ----------Article: 50034
In the Coolrunner II datasheet it says that its compatible with several voltage levels: Mixed I/O voltages compatible with 1.5V, 1.8V, 2.5V, and 3.3V logic levels on all parts. Does that mean that i can interface with 3.3V devices without any external component, or does it just tolarate when a 3.3v signal comes ? Thank youArticle: 50035
skintigh@yahoo.com (Seth) wrote in message news:<ab6e8fe6.0211251516.2851d6bd@posting.google.com>... > I am looking for vendors of PCI FPGA boards for production, not just > prototyping. > > So far I know of Annapolis Microsystems which offers boards with > Virtex chips and RAM. > > Can anyone recommend any others? There is some great PCI boards provided by AVNET based on xilinx FPGA's. That is one : http://www.avnetmarshall.com/dynamic/html/forms/adx-20020322semw-req.html Note that avnet delivery is mostly not good !Article: 50036
This is a multi-part message in MIME format. --------------1ADC248A595A1EF1111BA56B Content-Type: text/plain; charset=us-ascii Content-Transfer-Encoding: 7bit Hua, You need the EDK software. http://www.xilinx.com/ise/embedded/edk.htm Dave Hua Ai wrote: > I want to utilize the PowerPC core of VertexII Pro in a system, but I > get confused by those documents on Xilinx Website. They seems tend to > introduce the architecture of PowerPC itself, instead of how to use it. > I would appreciate if anyone can tell me what HW/SW kits on earth I need > to build/simulate/debug a PowerPC system on Vertex II pro. > > Thanks a million, > > HuaArticle: 50037
Semih Hazar <semih.hazarNOSPAM@ao-group.de> wrote: : In the Coolrunner II datasheet it says that its compatible with several : voltage levels: : Mixed I/O voltages compatible with 1.5V, 1.8V, 2.5V, and 3.3V logic levels : on all parts. : Does that mean that i can interface with 3.3V devices without any external : component, or does it just tolarate when a 3.3v signal comes ? You must differentiate between "tolerance" and "compliance". The inputs have a maximum rating of 4 Volt, independant of VCCIO. So they are at least "3.3V tolerant". But to have output levels compliant to 3.3V signaling, you need to provide VCCIO=3.3V. Bye -- Uwe Bonnes bon@elektron.ikp.physik.tu-darmstadt.de Institut fuer Kernphysik Schlossgartenstrasse 9 64289 Darmstadt --------- Tel. 06151 162516 -------- Fax. 06151 164321 ----------Article: 50038
Is anyone aware of any kind of FSM implementation that is programmable? I am thinking of using scan chain to shift some value onto on-chip registers, but maybe there is also the option to compile FSM into a binary file and have FPGA load the binary file and execute it, sort of like a state table. Where should I go to find reference on those?Article: 50039
This is a multi-part message in MIME format. --------------DD935C049C285BFB9258F001 Content-Type: text/plain; charset=us-ascii Content-Transfer-Encoding: 7bit Hi, Why not take a look at PicoBlaze on the Xilinx website - alternativly you could use a RAM for the presentstate nextstate transition table, and then when you want to change it re-write the contents. Dave zhengyu wrote: > Is anyone aware of any kind of FSM implementation that is programmable? > > I am thinking of using scan chain to shift some value onto on-chip > registers, but maybe > there is also the option to compile FSM into a binary file and have FPGA > load the > binary file and execute it, sort of like a state table. > > Where should I go to find reference on those?Article: 50040
Hi! Yesterday I was reading the news on xilinx web site, about new version of this great tool. After a few columns I found this: citation: " Higher performance Multiplier takes advantage of Virtex-II series pipelined dedicated multipliers along with placed input and output registers. Design can now accept clock rate as high as 285MHz with a latency of three." Q1: how is it possible to achieve that clock, because the privies relies of sys. gen. was able to speedup the multipliers to the max clock of 125Mhz? Thanks for the answer. SASAArticle: 50041
Hi, I'm looking for an introductory course in SDRAM technology. The background is that I'm currently working on an FPGA design involving a SDRAM controller, but I can't find any document describing the internal operation of these devices. For example, I know I have to do a PRECHARGE to close a row, but I'd like to know why I actually have to close a row. Anyone can recommend any good book and/or link (I'm already aware of the Xilinx appnotes & the Micron datasheets) ? Many thanks, Guy.Article: 50042
Sasa, The Virtex-II Multiplier features a pipeline register which allows higher performance multiplication (285MHz as indicated). The previous version of System Generator did not take advantage of this pipeline stage. - Paul "Sasa Bremec" <sasa@i-tech.si> wrote in message news:as7his$41p$1@planja.arnes.si... > Hi! > > Yesterday I was reading the news on xilinx web site, about new version of > this great tool. > After a few columns I found this: > > citation: " Higher performance Multiplier takes advantage of Virtex-II > series pipelined dedicated multipliers along with placed input and output > registers. Design can now accept clock rate as high as 285MHz with a latency > of three." > > Q1: how is it possible to achieve that clock, because the privies relies of > sys. gen. was able to speedup the multipliers to the max clock of 125Mhz? > > Thanks for the answer. SASA > > > > >Article: 50043
The 18x18 multipliers are hardcore cores in the Virtex-II, on silicium. The sys. gen. will generate 18x18 soft cores for Spartan-II (E), VirtexE ... Laurent Gauch, Amontec http://www.amontec.com Sasa Bremec wrote: > Hi! > > Yesterday I was reading the news on xilinx web site, about new version of > this great tool. > After a few columns I found this: > > citation: " Higher performance Multiplier takes advantage of Virtex-II > series pipelined dedicated multipliers along with placed input and output > registers. Design can now accept clock rate as high as 285MHz with a latency > of three." > > Q1: how is it possible to achieve that clock, because the privies relies of > sys. gen. was able to speedup the multipliers to the max clock of 125Mhz? > > Thanks for the answer. SASA > > > > >Article: 50044
Check out www.avvida.com for Altera Stratix FPGA PCI board. Brian "Seth" <skintigh@yahoo.com> wrote in message news:ab6e8fe6.0211251516.2851d6bd@posting.google.com... > I am looking for vendors of PCI FPGA boards for production, not just > prototyping. > > So far I know of Annapolis Microsystems which offers boards with > Virtex chips and RAM. > > Can anyone recommend any others?Article: 50045
"Sasa Bremec" <sasa@i-tech.si> wrote in message news:<as7his$41p$1@planja.arnes.si>... > Hi! > > Yesterday I was reading the news on xilinx web site, about new version of > this great tool. > After a few columns I found this: > > citation: " Higher performance Multiplier takes advantage of Virtex-II > series pipelined dedicated multipliers along with placed input and output > registers. Design can now accept clock rate as high as 285MHz with a latency > of three." > > Q1: how is it possible to achieve that clock, because the privies relies of > sys. gen. was able to speedup the multipliers to the max clock of 125Mhz? > > Thanks for the answer. SASA Hi, Check out the number of pipe-lined stages? what device family u r referring to regarding 125Mhz clock. Regards, MuthuArticle: 50046
David Hawke <dhawke@xilinx.com> wrote in message news:<3DE745DB.2E75228D@xilinx.com>... > Hi, > > Why not take a look at PicoBlaze on the Xilinx website - alternativly you > could use a RAM for the presentstate nextstate transition table, and then > when you want to change it re-write the contents. > > Dave Hi, yeah thats right, we can change the FSM behaviour in the "Block RAM way of implenting FSM" by affecting the Memory contents. But we can not implement FSM using the BRAMs, if the number of inputs are more. and this goes to occupy more memory locations.Article: 50047
elaborating on the RAM implementation furthere what you can do is use a Xilinx BlockRAM to implement your state machine. All you need to do is to connect the RAM's data bus back to it's adderss bus with a single clock cyccle delay. This reverse feedback path should be routed to two memories actually, one will be your next state generation logic and the other will be your output decoder logic. The second memory outputs can be used as outputs of your state machine. Durin synthesis you will have to come up with the binary data to store in the Block RAM . for more details refer to the Xcell article by Peter Alfke in some issue which does not come to my mind right now. regards, Nachiket Kapre. Design Engineer. Paxonet Communications. "zhengyu" <zhengyu@attbi.com> wrote in message news:<YRGF9.155856$WL3.65530@rwcrnsc54>... > Is anyone aware of any kind of FSM implementation that is programmable? > > I am thinking of using scan chain to shift some value onto on-chip > registers, but maybe > there is also the option to compile FSM into a binary file and have FPGA > load the > binary file and execute it, sort of like a state table. > > Where should I go to find reference on those?Article: 50048
Hi Guy, you can find SDRAM controller and relative documentation by Xilinx application "Xapp134". J hope this is useful for you !! Paolo. Guy Eschemann <geschemann@yahoo.fr> wrote in message b9f16a5b.0211290339.c4f5196@posting.google.com... >Hi, > > I'm looking for an introductory course in SDRAM technology. The >background is that I'm currently working on an FPGA design involving a >SDRAM controller, but I can't find any document describing the >internal operation of these devices. > For example, I know I have to do a PRECHARGE to close a row, but I'd >like to know why I actually have to close a row. > Anyone can recommend any good book and/or link (I'm already aware of >the Xilinx appnotes & the Micron datasheets) ? > >Many thanks, >Guy.Article: 50049
Sasa Bremec wrote: > > > citation: " Higher performance Multiplier takes advantage of Virtex-II > series pipelined dedicated multipliers along with placed input and output > registers. Design can now accept clock rate as high as 285MHz with a latency > of three." > > Q1: how is it possible to achieve that clock, because the privies relies of > sys. gen. was able to speedup the multipliers to the max clock of 125Mhz? > The multiplier has not only tightly coupled input and output registers, but also a register carefully placed "kind-of down the middle" of the multiplier array. That's what is meant by pipelining, which of course causes latency. You can use it to achieve high throughput, but you can also eliminate it to achieve a strictly combinatorial multiplier. It's your choice... Peter Alfke, Xilinx Applications, presently with Karen Alfke 2nd Nature Design Port Townsend, WA karen@2ndesign.com
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