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Hi Thomas, Thanks for your reply, but my question is different.(Probably it was not clear enough) What i want to do is: I want to take the vhdl netlist that i get from XFT 4.1i, edit it according to my need and then convert it in to EDIF/EDN/XNF. The reason for doing this is, I want to simulate the edited netlist using the gate level simulator in XFT. And the simulator take in, only the netlist in EDIF/EDN/XNF format. Thanks Praveen.Article: 40326
"Ray Andraka" <ray@andraka.com> schrieb im Newsbeitrag news:3C8431EA.3E7F2860@andraka.com... > devices for the past decade. Another remaining advantage Xilinx has is the infamous SRL16. These not only make for compact small delay queues (which can > be made up for with the stratix memory architecture), but also serve as reloadable LUTs, which is very handy for things like reloadable distributed arithmetic. > Sure, with the addition of fast multipliers, the need for DA may be reduced, but it is still a very useful tool in the shed. And they can also be used for very compact, fast synchjronous FIFOs. -- MfG FalkArticle: 40327
I've thought of doing something similar myself when my design ran too slow for the DLL's (Digital locked loop) to lock in the Xilinx part I was using. For starters you can look at the Xilinx app note that describes their DLL's. I guess its is a really long delay line with selectable taps. Generating such a long delay consume a lot of real estate because your reference has such a long period. You know that there are dinky generic MSI 74HCXX type PLL's that work in the range you're trying to lock don't you? Maybe a PLL is closer to what you want, I think they're better for frequency synthesis like what I'm assuming you're doing- trying to generate a pixel clock phase locked to the hsync. Maybe one of Altera's smaller parts with a PLL can do what you want? Just throwing out ideas here... Regards Guy Eschemann <geschem@surfeu.de> wrote in message news:<3C84E900.455F5BF0@surfeu.de>... > Hi, > I need to design a digital PLL to fit in a small FPGA or CPLD. > This PLL should lock on a video H-sync which has a period of 64us. > Could anyone please give me some hints on how to get started with it ? > Many thanks, > Guy.Article: 40328
"Guy Eschemann" <geschem@surfeu.de> schrieb im Newsbeitrag news:3C84E900.455F5BF0@surfeu.de... > Hi, > I need to design a digital PLL to fit in a small FPGA or CPLD. > This PLL should lock on a video H-sync which has a period of 64us. > Could anyone please give me some hints on how to get started with it ? At first jus should ask yourself some question. What output frequency do I want (15 khz, just like H-synch, or multiples of that) ? What amount of jitter is allowed (0.1UI, 0.01 UI or less )? A main problem of pure digital PLLs (made of CPLDs/FPGAs) is intrinsic jitter. This is due to the limited timing resolution, which depends on the frequency of your master clock. With 200 Mhz, this gives you 5ns resolution in time. With a 10 MHz output frequency, this is 1/20 = 0.05 UI. I have a VHDL description of the more or less famous 74HC297, If you would like to have a look at it, drop me a mail. -- MfG FalkArticle: 40329
Seems to be both commercial (network/storage?) and defense. Defense seems to be finally getting "with it" as to what a real engineering salary is although whenever I talk to those guys they call anything that isn't defense a "dot com". Tom <tomcip@concentric.net> wrote in message news:<3C84E201.DB8C248D@concentric.net>... > Jay wrote: > > > Come on down to the CA (California that is), I have head hunters > > calling all the time... > > Why is that? I have noticed that while the Silicon Valley is still dead I am getting calls from pondscum > headhunters claiming jobs in Orange County. Is it related to the defense industry? > > Tom > > > > > > > > > "Albert" <wagain@hotmail.com> wrote in message news:<01kf8.239995$I8.48176768@news4.rdc1.on.home.com>... > > > Hi, > > > > > > I have many years of experience on DSP/embedded system and FPGA/CPLD design. > > > I'm in Vancouver and looking for jobs. If the company you work for has any > > > opening or you know any job opportunities that my skills fit, and your > > > information finally leads to my job, I will be glad to share half of my > > > first two months' net income to you. I guarantee it. I will be glad to > > > relocate to other cities in Canada. It is double wins, for me, I got a job > > > and sharing my half of salary to you is absolutely no problem, and for you, > > > that position you know will doom to be filled by someone finally, why don't > > > you do me a favor? > > > > > > I appreciate any reply. My email address is: wagain@hotmail.com. > > > > > > > > > Thank you for your time. > > > > > > AlbertArticle: 40330
For the EQ, you can use serial arithmetic. See the tutorial on distributed arithmetic on my website. Remco Poelstra wrote: > Ray Andraka wrote: > > That said, I am assuming you are talking about audio mixing. If that is the > > case, you can get into a smaller, cheaper device by working with bit serial > > arithmetic for the mixing. In that case, the multiplier is little more than > > an adder. See the multiplier page on my website (when it comes back > > up...seems the ball got dropped in transferring the domain name to the new > > ISP so it may be a day or so before you can get to the website). > > Apart from audio mixing, I want to implement a digital EQ, but I assume > that doesn't make any difference for the multiplier? > > Thanks for the reply, > > Remco PoelstraArticle: 40331
Guy, This period is much too slow for the DLL (or DCM). If you synthesize it from a higher frequency (ie DDFS, or fractional synthesizer) you may have unnacceptable jitter (leads to blurred pixels). Austin Guy Eschemann wrote: > Hi, > I need to design a digital PLL to fit in a small FPGA or CPLD. > This PLL should lock on a video H-sync which has a period of 64us. > Could anyone please give me some hints on how to get started with it ? > Many thanks, > Guy.Article: 40332
Russell Shaw wrote: > I'm using LS v2001_1d.24_OEM_Altera. It *does* utilize LPM black-boxes > from your vhdl such as counters etc. Things like dual-port rams with > separate read and write addresses aren't tho. However, black-boxing > of these functions works if you first generate the files using the > megawizard thing in maxplus2/quartus2. Since Kevin said he is also using LeonardoSpectrum-Altera, another alternative is to just write the code and let Leo pick out the blocks. Leo can infer any of the LPM functions from code that matches the function. This makes simulation much easier as well. -- Mike TreselerArticle: 40333
Wait as long as you can to buy your new machine. By the time the V2-8000 is in your hand, the machines will be more attainable. If the design can be partitioned or scaled, then you can use a smaller part(s) and not have to wait painful 8+ hours for a P&R. We run on a Sun server with loads of RAM sometimes. Regards mschreiber75@yahoo.com (M Schreiber) wrote in message news:<e8caa675.0203050633.59597cca@posting.google.com>... > all, > Has anybody found a good method for implementing designs using the > Xilinx 4.1 ISE (under windows) that require more than 2GB of memory > for the place and route? I have read that Xilinx now supports their > tools running Linux (using WINE). Does this new method allow users to > exceed the 2GB limitations or is this a function of application > executable? We are looking to complete an upcoming design that may > require a Virtex 2 (xc2v8000) and xilinx recommends that you need at > least 3 GB of memory for place and route. What are most people doing > to overcome this? Are there any relatively cheap unix based machines > ($<10,000) that can accomplish this? Any recommendations would be > greatly appreciated. > Thanks in Advance, > Mike Schreiber > hardware engineerArticle: 40334
Paul wrote: > I'm producing a trailing edge pulse from a clock and passing it > straight out as an output port for testing purposes but some of the > pulses are missing when implementing onto a FPGA. It works fine when > simulating with Modelsim. > The clock going into the FPGA is correct. > > Could it be a metastability issues? More likely a timing race issue. Either reconsider you test plan or start with a 2X clock and do a synchronous generator. -- Mike TreselerArticle: 40335
I have heard from some folks: That even with Linux on the PC platform, that 2 Gbytes is the limit. There are people looking into why this is. Stay tuned for the answer. This may be related to the hardware they are using, or the build of Linux.... Austin Austin Lesea wrote: > We have Linux support now.....nice low cost way to break out of the 2Gbyte > limit of Windows on PC platforms. Dell supports a 4Gbyte memory, that > could be used by Linux. > > http://www.xilinx.com/prs_rls/software/0225_Em_Linux.html > > Austin > > M Schreiber wrote: > > > all, > > Has anybody found a good method for implementing designs using the > > Xilinx 4.1 ISE (under windows) that require more than 2GB of memory > > for the place and route? I have read that Xilinx now supports their > > tools running Linux (using WINE). Does this new method allow users to > > exceed the 2GB limitations or is this a function of application > > executable? We are looking to complete an upcoming design that may > > require a Virtex 2 (xc2v8000) and xilinx recommends that you need at > > least 3 GB of memory for place and route. What are most people doing > > to overcome this? Are there any relatively cheap unix based machines > > ($<10,000) that can accomplish this? Any recommendations would be > > greatly appreciated. > > Thanks in Advance, > > Mike Schreiber > > hardware engineerArticle: 40336
There are techniques to develop a stable average frequency from a high frequency reference using the 64us pulse as a correction. I'd suspect, however, that the jitter information that would be inherent in the DPLL could form visual patterns that detract from your true needes. In my opinion, good video needs good analog elements in key places like this: timing. Guy Eschemann wrote: > Hi, > I need to design a digital PLL to fit in a small FPGA or CPLD. > This PLL should lock on a video H-sync which has a period of 64us. > Could anyone please give me some hints on how to get started with it ? > Many thanks, > Guy.Article: 40337
Look at what National Semiconductor does with their LVDS serializer/deserializer chips. Albert wrote: > I need to design a multiplexer/demuliplexer. > > The multiplexer support 4 input serial ports each (TXD,RXD,RTS,DTR) > all the signals are sended via a signle pairArticle: 40338
Challenging the need for HVLs
From: Ben Cohen [vhdlcohen@aol.com]
This article challenges the need of specialized verification language
in favor of transaction-based verification in HDL. It also addresses
verification techniques for the definition of test vectors, and the
confirmation that the design under test (DUT) meets the design
functional requirements.
http://members.aol.com/vhdlcohen2/vhdl/veriflang.pdf
---- ---- ---- ---- ---- ---- ----
From: Anonymous
That article was useful and I forwarded your email to others who just
finished a study on replacing VHDL with verification languages or
tools. The group came up with the same view, which is that VHDL is a
good solution as long as the verification engineers use good
techniques and methodologies. As long as there are computer or design
languages, the age old proberb of "garbage in, garbage out" prevails.
---- ---- ---- ---- ---- ---- ----
From: Ben Cohen [vhdlcohen@aol.com]
Thanks for your feedback. Just for the record, I do not mean that
verification languages are bad. In fact they do offer some nice
features, like probing internal signals for grey-box verification; or
like the close tie-in to code coverage, or access to C++ routines for
verification of design against algorithms. Experienced people claim a
great speed advantage (4x?) over HDL.
My issues are:
1. Training costs and availability of (or access to) trained people
when you need them (e.g., make changes, new vectors, etc).
2. Overkill for sanity checks of subblocks, and for designs of
moderate complexity.
3. No force/release of errors inside hierarchy (not available either
in verification languages (at least for Vera and Testbuilder, don't
know about Specman)).
4. Verification languages are more appropriate to Verilog users for
the following reasons:
- Verif Langs have the look/feel of Verilog (more foreign to VHDL
users)
- Verilog lacks high level constructs (no record, no pointer, no
unconstrained arrays, no attributes (e.g., 'event, 'range), no
enumeration type). Thus Verification languages offer more
"FREEDOM" in the construction of the testbench.
You don't need a tractor for a one-horse daily manure cleanup. I know,
from experience, since I have a quarter horse named Specials.
Article: 40339The real problem is the modular design is not really real yet. Once that becomes usable, I think many of the issues with ever increasing machine memory will be largely resolved. To make it work correctly, though, I think XIlinx has to get away from the flat model for UCF , floorplans and place/route. Jay wrote: > Wait as long as you can to buy your new machine. By the time the > V2-8000 is in your hand, the machines will be more attainable. If the > design can be partitioned or scaled, then you can use a smaller > part(s) and not have to wait painful 8+ hours for a P&R. We run on a > Sun server with loads of RAM sometimes. > > Regards > > mschreiber75@yahoo.com (M Schreiber) wrote in message news:<e8caa675.0203050633.59597cca@posting.google.com>... > > all, > > Has anybody found a good method for implementing designs using the > > Xilinx 4.1 ISE (under windows) that require more than 2GB of memory > > for the place and route? I have read that Xilinx now supports their > > tools running Linux (using WINE). Does this new method allow users to > > exceed the 2GB limitations or is this a function of application > > executable? We are looking to complete an upcoming design that may > > require a Virtex 2 (xc2v8000) and xilinx recommends that you need at > > least 3 GB of memory for place and route. What are most people doing > > to overcome this? Are there any relatively cheap unix based machines > > ($<10,000) that can accomplish this? Any recommendations would be > > greatly appreciated. > > Thanks in Advance, > > Mike Schreiber > > hardware engineerArticle: 40340
Yeah, that too, although we call them elastic buffers in our library to differentiate them from the other fifos. They are also very handy for reordering data. We use them, for example in our FFT core for the data reordering. Falk Brunner wrote: > And they (SRL16's) can also be used for very compact, fast synchjronous > FIFOs. > > -- > MfG > FalkArticle: 40342
Paul wrote:
>
> I use Quartus2 1.1 SP2 with LS 2001.1d and find that I use Leonardo to
> control quartus command line for P&R.
>
> I didn't successfully get Q2 to control LS however
>
Yes, previously, I tried to run LS-Altera 2001.1a_028 from QII
1.1 Web Edition (a build around September of 2001), but it will crash at
Quartus_Cmp.exe.
Therefore, I upgraded to QII 2.0 WE + LS-Altera
OEM2002a_Altera_NIGHTLY_14.
QII 2.0 no longer crashes, so there is some improvement, but not perfect
at all.
> However I also now use ActiveHDL and that controls the command line of both
> LS (for synthesis) and Q2 for P&R OK.
>
> I would say I wasn't at all keen on trying the new LS until I hear some good
> reports.
>
> Take a look at the problems left in. If they can't get library (LPM etc) to
> work correctly in a release something needs fixing. LPM integration is such
> a basic requirement of an Altera tool IMHO.
> From the LS readme file:
> 5. The LeonardoSpectrum-Altera Software Version 2002a.14 will not recognize
> LPM instantiations in HDL as black boxes. This may result in one or more
> of the following types of Error messages :-
> =======================================================================
> Error : output port/net "<net>" of instance "<instance>" of cell
> <blackbox> has no driver.
> WARNING: output port is not driven -- <port_name>
>
> =======================================================================
> <followed by a script fix>
>
> Reports on Q2 v2 and LS2002 gratefully areceived.
>
> Paul
>
Although I don't use LPM, it sounds like Mentor Graphics/Altera
is releasing a synthesis tool with major flaws.
Does Synplify or FPGA Compiler II handle LPM correctly?
If LS doesn't handle LPM, do people end up using Quartus II's Altera
in-house synthesis tool, which is not as good as LS?
> PS did you install Q2 or LS into a path containing spaces? Leo doesn't
> appear to be finding a system library (flex10e.syn)
>
Regarding the directory I installed QII 2.0 and LS-Altera, for
QII 2.0, I installed at d:\Quartus20, and for LS-Altera,
d:\Exemplar\LeoSpec\OEM2002a_Altera_NIGHTLY_14 (NIGHTLY ???? Who got
that name???).
So the directory names don't include any spaces.
This Solutions Database answer seems to be a similar problem to
what I am having.
http://www.altera.com/support/solutions/rd12151999_9269.html
But the above solution is for a version about 3 years old.
The interesting twist to this problem is that when I tried to
synthesize a small test design with FLEX6000 and APEX20KE, the
NativeLink feature worked fine, but when I tried it with ACEX1K and
FLEX10KE, the NativeLink didn't work (couldn't find acex1k.syn or
flex10ke.syn).
Following your suggestion, I checked the directory where *.syn files are
located (d:\Exemplar\LeoSpec\OEM2002a_Altera_NIGHTLY_14\lib), and I
finally figured out the problem.
It turned out that QII 2.0's NativeLink script (Where is it located? Can
I modify it?) tries to reference "acex1k.syn" and "flex10ke.syn," but
LS-Altera's \lib directory has only "acex1.syn" and "flex10e.syn."
Yes, some idiot at Altera added an extra 'k' to QII 2.0-LS NativeLink
script, so the thing didn't work!!!
I wasted several hours yesterday because of this idiot!!!
What is the QA (Quality Assurance) person of QII 2.0 doing!!!
Aren't you (QA person) adequately testing the product before releasing
it?
It looks like the QA person forgot to test NativeLink with LS-Altera
when FLEX10KE/ACEX1K is used.
I guess my comment yesterday was correct that Altera indeed didn't test
the product adequately before releasing it.
I wish Altera doesn't release products with problems.
Because LS-Altera might still use "acex1.syn" and "flex10e.syn,"
I simply made copies of those files, and added that 'k'.
Now LS-Altera works perfectly fine from QII 2.0 WE.
Kevin Brace (Don't respond to me directly, respond within the
newsgroup.)
Article: 40343Thanks for your answer Falk, concerning the output frequency, it should be equal to the input frequency (ca. 15 KHz). I'm not sure about the allowed jitter, but the criterion here is that the phase jitter should not be visible on the display. I will have to do some experiments to determine this, but first I need a working design. I had a look at the newsgroup archive, and the most widely used approach seems to be the frequency synthesis by a phase accumulator. The problem is that I'm lacking some theoritical background here, especially for the logic around the phase accumulator (feedback loop...). Anyway, I would be highly interested in having a look at the 74HC297 VHDL description. Many thanks, Guy. Falk Brunner schrieb: > "Guy Eschemann" <geschem@surfeu.de> schrieb im Newsbeitrag > news:3C84E900.455F5BF0@surfeu.de... > > Hi, > > I need to design a digital PLL to fit in a small FPGA or CPLD. > > This PLL should lock on a video H-sync which has a period of 64us. > > Could anyone please give me some hints on how to get started with it ? > > At first jus should ask yourself some question. > > What output frequency do I want (15 khz, just like H-synch, or multiples of > that) ? > What amount of jitter is allowed (0.1UI, 0.01 UI or less )? > > A main problem of pure digital PLLs (made of CPLDs/FPGAs) is intrinsic > jitter. This is due to the limited timing resolution, which depends on the > frequency of your master clock. With 200 Mhz, this gives you 5ns resolution > in time. With a 10 MHz output frequency, this is 1/20 = 0.05 UI. > I have a VHDL description of the more or less famous 74HC297, If you would > like to have a look at it, drop me a mail. > > -- > MfG > FalkArticle: 40344
Maybe you can describe the circuit you're using, but if you're doing something asynchronous that depends on the relative delays of gates then all bets are off. When you say this signal is a clock, is it THE clock for the design, or can you sample it with another higher freuency clock? paul.lee@sli-institute.ac.uk (Paul) wrote in message news:<9aeb7852.0203050323.12f72b04@posting.google.com>... > Hi everyone, > > I'm producing a trailing edge pulse from a clock and passing it > straight out as an output port for testing purposes but some of the > pulses are missing when implementing onto a FPGA. It works fine when > simulating with Modelsim. > The clock going into the FPGA is correct. > > Could it be a metastability issues? > > > Any help will be great. > > Thanks > > Paul LeeArticle: 40345
Guy Eschemann wrote: > > Thanks for your answer Falk, > > concerning the output frequency, it should be equal to the input frequency (ca. > 15 KHz). I'm not sure about the allowed jitter, but the criterion here is that > the phase jitter should not be visible on the display. I will have to do some > experiments to determine this, but first I need a working design. I had a look > at the newsgroup archive, and the most widely used approach seems to be the > frequency synthesis by a phase accumulator. The problem is that I'm lacking some > theoritical background here, especially for the logic around the phase > accumulator (feedback loop...). Anyway, I would be highly interested in having a > look at the 74HC297 VHDL description. Many thanks, Guy. A 60MHz PLL clock would be 1/10 of a typical PAL Teletext Pixel ( 6 MHz IIRC) You may need to look at a dual scheme, a digital loop for fast sync, and then an analog loop (74HC4046 family) in parallel, that is used once it locks. You should also check the source options/quality, a lot of video has jitter problems, and is not precisely on frequency. -jgArticle: 40346
See www.xilinx.com/virtex2pro . Congratulations to Xilinx on another blockbuster achievement. It's a bit of a cliche, but the arrival of V2Pro and the Altera Excallibur family marks a huge turning point for the programmable logic industry. Assuming they are priced competitively, I think these new devices, and the forthcoming cores libraries and system builder tools that will accompany them, will prove irresistable to nearly all embedded systems designers -- so that (say) three years from now there will be "tons" of programmable logic in all but the most cost constrained new designs. It's the full employment act for FPGA designers! :-) The debut of these parts is also exciting because it represents the continued "democratization" of cutting edge technologies. You don't need a "million unit order" to get access to fast embedded processors, fast logic, fast embedded RAMs, fast serial links, clock management, a rich cores library, etc. As for V2Pro, gigabit links and PowerPCs aside, I applaud the extra generous helpings of BRAM provided in these new devices. I have posted some early news links and commentary, including a small table comparing V2 and V2Pro devices, at www.fpgacpu.org/#020304. Jan Gray Gray Research LLCArticle: 40347
All, I had lunch with our video interface guru, and he sees no degradation from using the DCM insofar as pixel jitter is concerned up to his fastest video rate, which is ~ 50 MHz on CRT's. He mentioned that on LCD's, the jitter might be more noticeable. 0.01 UI at 50 MHz is 200 ps P-P, which is pretty darn tight for a jitter specification in an FPGA that is also doing lots of SSOs and CLBs toggling. Austin Jim Granville wrote: > Guy Eschemann wrote: > > > > Thanks for your answer Falk, > > > > concerning the output frequency, it should be equal to the input frequency (ca. > > 15 KHz). I'm not sure about the allowed jitter, but the criterion here is that > > the phase jitter should not be visible on the display. I will have to do some > > experiments to determine this, but first I need a working design. I had a look > > at the newsgroup archive, and the most widely used approach seems to be the > > frequency synthesis by a phase accumulator. The problem is that I'm lacking some > > theoritical background here, especially for the logic around the phase > > accumulator (feedback loop...). Anyway, I would be highly interested in having a > > look at the 74HC297 VHDL description. Many thanks, Guy. > > A 60MHz PLL clock would be 1/10 of a typical PAL Teletext Pixel ( 6 MHz > IIRC) > > You may need to look at a dual scheme, a digital loop for fast sync, > and > then an analog loop (74HC4046 family) in parallel, that is used > once it locks. > > You should also check the source options/quality, a lot of video has > jitter problems, and is not precisely on frequency. > > -jgArticle: 40348
I have been using QII 2.0 Web Edition for a few days, and one of
the new features of QII 2.0 is fast fit option which reduces compile
(P&R) time.
http://www.altera.com/corporate/news_room/releases/products/nr-stx_quartus.html
Didn't kind of feature to reduce the P&R effort level already existed in
Xilinx tools for years?
In Xilinx tools (like ISE WebPACK 4.1 I primarily use), the user can
choose between five P&R effort levels with an optional Extra Effort
level available.
So, what is the big deal about it, Altera?
I guess I am now critical of Altera because of my bad experiences with
QII 2.0 WE + LeonardoSpectrum-Altera 2002 Level 1 NativeLink issue when
FLEX10KE or ACEX1K is the target device.
Kevin Brace (Don't respond to me directly, respond within the
newsgroup.)
Article: 40349Austin Lesea wrote: > All, > > I had lunch with our video interface guru, and he sees no degradation from using the > DCM insofar as pixel jitter is concerned up to his fastest video rate, which is ~ 50 > MHz on CRT's. Using a DCM to produce a fixed frequency can generate acceptable jitter. Any DCM jitter should be distributed about the "ideal" timing edge as some form of additive white noise. The trouble with using DPLL techniques is that they (typically) would use an NCO approach to slave to the reference edge. The NCO produces jitter that can be very correlated line-to-line. Visual artifacts can blossom rather than just fuzz.
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