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Hi, I am trying to convert an old project written in MachXL DSL to a more modern Mach device. Since the current Lattice software does not support DSL, I am going to have to convert to another design language. As far as I can see, my choices are Verilog, VHDL and ABEL. I was recommended to learn either Verilog or VHDL, preferably VHDL since that is more used here in Europe, but no mention was made of ABEL. As far as I can see, however, ABEL is a much simpler language, which should be more than sufficient for my needs. As far as I have understood it from what I have read so far, both Verilog and VHDL are simulation languages, and only a small part of the language is actually synthesizable in hardware, whereas ABEL is designed as as hardware description language. I have little experiance with PLD/FPGA design, apart from a couple of projects several years ago. I will probably be doing a bit more in the future, so it is useful to learn a portable language rather than tying myself specifically to the one device family, but PLD/FPGA design will only ever be a minor part of my job (mostly low-level microcontroller programming, and some electronic design). I'd value any comments about what language would be the best choice before I get too far down the wrong road. -- David Brown WestControl a.s NorwayArticle: 40576
If you want explain it to me in german it would be great. I'm dutch, so translation wouldn't be a big problem. Peter Alfke <peter.alfke@xilinx.com> wrote in message news:<3C892C85.39C0C531@xilinx.com>... > My mistake. > I offered him some private coaching, if necessary in German...:-) > > Peter > ========================= > Peter Alfke wrote: > > > "F. Modderkolk" wrote: > > > > > Ok, I think I understand finally what you tried to tell me. I want to > > > thank you for that, because I'm only a simple student trying to > > > graduate. As a final solution, you suggest me to use an simple FPGA in > > > combinaton of an DDS. > > > Thanks again.Article: 40577
Due to the nature of RTR designs, simulation of the full design in a conventional simulator is not possible. However, a number of methods are available to alter the design to mimic the desired behaviour. Probably the simplest is to put multiplexers round the parts of the design which are to be reconfigured. If you want to see the effects of the reconfiguration, a more sophisticated model is required. You may find the following papers of interest: 1) W. Luk, N. Shirazi and P.Y.K. Cheung, "Compilation tools for run-time reconfigurable designs", Proc. IEEE Symposium on Field-Programmable Custom Computing Machines, Napa, California, USA, April 1997. 2) D. Robinson and P. Lysaght, "Methods of Exploiting Simulation Technology for Simulating the Timing of Dynamically Reconfigurable Logic", in IEE Proceedings Computer and Digital Techniques - Special Issue on Reconfigurable Systems, G. Brebner and B. Hutchings (Eds.) Vol. 147, No. 3 May 2000. 3) M. Vasilko and D. Cabanis, "A Technique for Modelling Dynamic Reconfiguration with Improved Simulation Accuracy", in IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences, November 1999. best regards, Ian "Kris Nichols" <knichols@uoguelph.ca> wrote in message news:3C841B6F.50304@uoguelph.ca... > I'm working on a project that involves run-time reconfiguration of VHDL > designs on a Xilinx FPGA. With run-time reconfiguration, the FPGA is > dynamically reconfigured at run-time to solve the current task at hand. > Is there any support for the simulation of run-time reconfiguration in > Xilinx EDA tools? I heard that the new Xilinx Foundation 4.2i tools > support partial run-time reconfiguration. How would one test/simulation > such a design? How, if at all, is run-time reconfiguration realized > in a VHDL testbench? Thanks for your time. > > Kris Nichols >Article: 40578
Rick, Spartan-IIE has a proper CMOS output that pulls all the way to the rail when lightly loaded. So, ignore the Voh min spec in your case. The output coltage will be just a few mV below Vcc. Peter Alfke, Xilinx Applications ======================================= rickman wrote: > I need to drive a CMOS device with a Spartan II E chip. The data sheet > only guarantees 2.4 volts on the output at 24 mA. Nothing is said about > lighter loads, for example a CMOS input. Working with an odd Vdd on the > CMOS device of 3.8 volts, I get a Vih of 2.66 volts. Is it safe to > assume that the Spartan device will pull fully to 3.3 volts (or very > near) with such a light load? The input current on the CMOS device is > <10 uA. Or should I use pullups? In spite of the data sheet note > saying that the internal pullups should not be used to pull external > signals, will they be sufficient to provide sufficient pullup with such > a light load? I am not even sure if you can enable the pullups on pin > used as outputs. Anyone have experience with this? > > -- > > Rick "rickman" Collins > > rick.collins@XYarius.com > Ignore the reply address. To email me use the above address with the XY > removed. > > Arius - A Signal Processing Solutions Company > Specializing in DSP and FPGA design URL http://www.arius.com > 4 King Ave 301-682-7772 Voice > Frederick, MD 21701-3110 301-682-7666 FAXArticle: 40579
Simulate it with IBIS. Why does everyone avoid such a simple solution? The Hyperlynx demo is free, and includes some useful IBIS models (like Xilinx parts). Austin rickman wrote: > I need to drive a CMOS device with a Spartan II E chip. The data sheet > only guarantees 2.4 volts on the output at 24 mA. Nothing is said about > lighter loads, for example a CMOS input. Working with an odd Vdd on the > CMOS device of 3.8 volts, I get a Vih of 2.66 volts. Is it safe to > assume that the Spartan device will pull fully to 3.3 volts (or very > near) with such a light load? The input current on the CMOS device is > <10 uA. Or should I use pullups? In spite of the data sheet note > saying that the internal pullups should not be used to pull external > signals, will they be sufficient to provide sufficient pullup with such > a light load? I am not even sure if you can enable the pullups on pin > used as outputs. Anyone have experience with this? > > -- > > Rick "rickman" Collins > > rick.collins@XYarius.com > Ignore the reply address. To email me use the above address with the XY > removed. > > Arius - A Signal Processing Solutions Company > Specializing in DSP and FPGA design URL http://www.arius.com > 4 King Ave 301-682-7772 Voice > Frederick, MD 21701-3110 301-682-7666 FAXArticle: 40580
Hi, what you should do is not to take a look on LVDS capability only. You also need to consider that some FPGAs require external resistors and some other do not. My pesronal believe is that Alteras LVDS offering currently is the best. regards lsuserArticle: 40581
Well, If it has internal resistors, that makes it best? Hardly. What about support? What about cores? What about performance? Virtex II has every pin LVDS capable. I am curious what your application is, and how you have measured this "best." How many systems do you have working over process/voltage/temperature? How many systems have you shipped? What is your eye opening? What is your jitter tolerance? Can you even measure these parameters (Virtex II can, while running, fully characterize the eye opening and input jitter tolerance using the variable phase shift feature). Austin lsuser wrote: > Hi, > > what you should do is not to take a look on LVDS capability only. You also need to consider that some FPGAs require external resistors and some other do not. My pesronal believe is that Alteras LVDS offering currently is the best. > > regards > > lsuserArticle: 40582
Hello! I'm looking for information about Motorola SPI interface implemented in Xilinx Spartan FPGA. I saw some cores on the web but I would like to do the hard job by my self, that is why i am looking for some advice from the guy's that have done this before me. TNX SASHArticle: 40583
The best and fastest divide-by four counter is a synchronous two-bit Johnson counter, i.e. a two-bit shift register with the second-stage output Q driving the first-stage D input through an inverter. That runs >250 MHz in any modern FPGA. Peter Alfke, Xilinx Applications =================================== Antonio wrote: > for the following circuit I need a clock divided by 4, to obtain it I > used a > cascade of 2 FFT , the output of the first FFT is an enable for the > second > > these are the constrain I used : > > FFTNET "clk" TNM_NET = "clk"; > TIMESPEC "TS_clk" = PERIOD "clk" 6 ns HIGH 50 %; > > NET "out_fft_1" TNM_NET = "out_fft_1_net"; > TIMESPEC "TS_out_fft_1_net" = FROM "out_fft_1_net" TO "out_fft_1_net" > "TS_clk" * 2; > > The result is just 100MHz while using a counter modulo 4 I can obtain > 124MHz always on V1000, > how I can obtain better results ?? Are the constrain well setted ?? > > library ieee; > use ieee.std_logic_1164.all; > use ieee.std_logic_signed.all; > > entity mult_C2_adder is > port(in_mca : in std_logic_vector(11 downto 0); > reset : in std_logic ; > clk : in std_logic ; > out_mca : out std_logic_vector(11 downto 0)); > end mult_C2_adder; > > architecture mult_C2_adder_arch of mult_C2_adder is > signal out_fft_1 : std_logic; > signal out_fft_2 : std_logic; > begin > > process(clk, reset) > begin > if reset = '1' then > out_fft_1 <= '1'; > elsif rising_edge(clk) then > out_fft_1 <= not out_fft_1; > end if; > end process; > > process(clk, out_fft_1, reset) > begin > if reset = '1' then > out_fft_2 <= '1'; > elsif rising_edge(clk) then > if out_fft_1 = '1' then > out_fft_2 <= not out_fft_2; > end if; > end if; > end process; > > process(clk, reset, out_fft_2, in_mca) > begin > if reset = '1' then > out_mca <= x"000" ; > elsif rising_edge(clk) then > out_mca <= in_mca ; > if out_fft_2 = '1' then > out_mca <= ( not in_mca) + 1 ; > end if; > end if; > end process; > > end mult_C2_adder_arch ;Article: 40584
Must...supress...overwhelming...urge...to...pun.... Sandwich boards - only if your job is toast. Do you need a slice of the action? If you're looking to meat employers... Forgive me - it's Monday and I am weak... (to embarassed to sign)Article: 40585
What timing is associated with the generation of the stream you're recovering? If the clk10x comes from the transmitter and corresponds to all 7 timeslots with specific timing guarantees (i.e. does the rising edge of clk10x always correspond to timeslot 6 with specified setup and hold?) you should be okay. My thoughts are you can use the clk35x to sample the clk10x (this makes the clk10x non-global for the sampling but should be okay) and figure out your alignment from the samples. You need setup but no hold on the sampling (a little negative hold in many cases) so phase aligned clocks should give you stable sampling. The samples produce different patterns for the two locked conditions allowing you to select the appropriate phasing. If you use the ddr structures in the IOBs, you'll still have to do your external alignment to extract your odd information from the even pairing so having a state machine control the selection mechanism should be straight forward. Enjoy! Mark wrote: > Hello, > > I'm trying to align an input "receiver" to ddr data in an XC2V6000-5. > The ddr data rate is 7x the 1x "system" clock. > > (The following are waveforms that are best viewed with a > non-proportional/fixed-width font.) > ______ ______ __ > clk10x _/ \______/ \______/ > _ _ _ _ _ _ _ _ > clk35x_p _/ \_/ \_/ \_/ \_/ \_/ \_/ \_/ \ > _____________________________ > locked __/ > > _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ > ddr_data X6X0X1X2X3X4X5X6X0X1X2X3X4X5X6X0 > - - - - - - - - - - - - - - - - > ______ ______ __ > clk10x _/ \______/ \______/ > _ _ _ _ _ _ _ _ > clk35x_p \_/ \_/ \_/ \_/ \_/ \_/ \_/ \_/ > _____________________________ > locked (2) __/ > > - clk10x and clk35x_p are phase-locked and clk10x rising edges are > "aligned" with clk35x_p's every 7 3.5x clock cycles. > - locked is synchronous to clk10x. It could be made synchronous to > clk35x_n. > - clk35x_n is also available. It is 180 deg phase locked/shifted from > clk35x_p. > - ddr_data is input to the ddr register. Its output is every other ddr > data at the 3.5x rate. > > - Using clk35x_p after locked goes high, the output of the ddr register > is 1,3,5,0,2,4,6,.... > - Using clk35x_p after locked (2) goes high, the output is > 0,2,4,6,1,3,5,0,.... > - This difference is due to an odd number, 7, of 3.5x clock cycles > occurring in two 1.0x clock cycles. > > The approach I've been trying is to align a state machine to the data by > determining which data, 1 or 0, is "first", using bits that toggle at > the different clock rates. > > I think I've been staring at this too long and need to get out of my > "box" to find a solution. I would greatly appreciate any thoughts. > > Thank you, > MarkArticle: 40586
Erwin Rol <Erwin.Rol_nospam_@Q-Soft-Engineering.com> writes: > hamish@cloud.net.au wrote: > > B. Joshua Rosen <bjrosen@polybus.com> wrote: > > > >>environment. I read a mention somewhere, either here or in the wine > >>group, that they intend to have a fully native version next year. The > >>GUIs are written using a tool that puts out both Windows and Unix code, I > >>think they are waiting for that tool to support Linux. > >> > > > > UNIX GUIs (ie X11) will already work on Linux - no changes required. > > > > Well it is unlikely they use bare X11, it is more likely they use > Motif/CDE under HP-UX and Solaris. And Motif 2.x and CDE are poorly > supported under Linux (unless you buy a commercial version, which will > cost you additional money). So Wine might be the easier (and cheaper) > solution here. There are quite a few Motif based applications available under Linux. Motif is available under the Open Group Public License: http://www.opengroup.org/openmotif/license/ The sources can be downloaded from the same site. However, the Xilinx GUI based apps (nder Solaris) does not seem to be linked with Motif (unless they are statically linked), e.g. the floorplanner appears to be linked with some other libraries (libRogueWave, libXdh, libGui_Framework, etc.). Petter -- ________________________________________________________________________ Petter Gustad 8'h2B | (~8'h2B) - Hamlet in Verilog http://gustad.comArticle: 40587
David Brown wrote: > > Hi, > > I am trying to convert an old project written in MachXL DSL to a more modern > Mach device. Since the current Lattice software does not support DSL, I am > going to have to convert to another design language. As far as I can see, > my choices are Verilog, VHDL and ABEL. I was recommended to learn either > Verilog or VHDL, preferably VHDL since that is more used here in Europe, but > no mention was made of ABEL. As far as I can see, however, ABEL is a much > simpler language, which should be more than sufficient for my needs. As far > as I have understood it from what I have read so far, both Verilog and VHDL > are simulation languages, and only a small part of the language is actually > synthesizable in hardware, whereas ABEL is designed as as hardware > description language. <snip> Abel, and the HDL variants ( CUPL, Altera HDL, PHDL etc ) are still widely used. It depends on the project size, and target devices. eg VHDL has problems reaching down to SPLD, as EDIF fitters for SPLD are ?? I also know designers who use Altera's AHDL in preference to VHDL, for quite large projects. Perhaps you could post some snippets of DSL, and the size of the target device(s) you expect to be using - then those here will be better able to adivse direction options -jgArticle: 40588
Thank you Austin. This is exactly what I´m talking about. Performance, Cores, Support, lowest number of external components, proven solutiuons. Do you believe that your LVDS solution is any better than the one being offered by Altera? Why? Wo really needs every single I/O pin LVDS capable? BTW, are we talking bout technical stuff or religion? Maybe, you could get a new house near Masar-el-Sharif. I heard that houses are quite cheap there in these days. Also, they´re looking for some new leaders who really believe in that what they´ve learned to be the truth. Maybe you could apply for a leading position?Article: 40589
lsuser wrote: > <snip>BTW, are we talking bout technical stuff or religion? Maybe, you could get a new house near Masar-el-Sharif. I heard that houses are quite cheap there in these days. Also, they´re looking for some new leaders who really believe in that what they´ve learned to be the truth. Maybe you could apply for a leading position? Cut out the crap if you are too much of a coward to give us your name. We don't need this kind of sarcasm here ! Peter AlfkeArticle: 40590
David Brown wrote:
> I will probably be doing a bit
> more in the future, so it is useful to learn a portable language rather than
> tying myself specifically to the one device family, but PLD/FPGA design will
> only ever be a minor part of my job (mostly low-level microcontroller
> programming, and some electronic design).
If you are just converting a working design
from Minc/Mach DSL to VHDL, you wouldn't
have to learn a lot of the language, and
the design is probably simple.
Look at some working VHDL example designs, then
have at it.
/ becomes not
* becomes and
+ becomes or
= becomes <=
NODE q CLOCKED_BY clk RESET_BY reset; becomes
process(reset, clk) begin . . .
Compile on a vhdl simulator to find the syntax errors.
Good luck.
-- Mike Treseler
Article: 40591"X. Q." <qijun@okigrp.com.sg> schrieb im Newsbeitrag news:3c8c6a00@news.starhub.net.sg... > Hi: > > I want to know whether it's ok to fit an MP3 decoder with 32MB RAM(external) > in a 60K FPGA device? Hmmm, good question. At www.opencores.org or www.fpgacpu.org I remember an article about a MP3 decoder in a 200K gates FPGA. -- MfG FalkArticle: 40592
"David Brown" <david_no_spam@no.spam.westcontrol.com> schrieb im Newsbeitrag news:a6i15k$4qa$1@news.netpower.no... > Hi, > > no mention was made of ABEL. As far as I can see, however, ABEL is a much > simpler language, which should be more than sufficient for my needs. As far Yes it is. > as I have understood it from what I have read so far, both Verilog and VHDL > are simulation languages, and only a small part of the language is actually > synthesizable in hardware, whereas ABEL is designed as as hardware Right. BUT, if you concentrate first on the core elements of VHDL/Verilog and firsat forget about all thoses fancy academic simulation stuff, you will get into a professional HDL (VHDL or Verilog) very quickly and wont regret the decicion. > description language. I have little experiance with PLD/FPGA design, apart > from a couple of projects several years ago. I will probably be doing a bit > more in the future, so it is useful to learn a portable language rather than > tying myself specifically to the one device family, but PLD/FPGA design will Exactly. > only ever be a minor part of my job (mostly low-level microcontroller > programming, and some electronic design). I'd value any comments about what > language would be the best choice before I get too far down the wrong road. Hmm I only "speak" VHDL. Its good, reminds me always of Turbopascal. Bad mouths say, VHDL is too much blabla and Verilog constructs are more compact. Hmm, maybe, but when writing VHDL Iam NOT in a hacker contest writing the most hard to understand hardware description. The opposite is reality, I try to make is a readable as possible. (Not only for other people, also for me) -- MfG FalkArticle: 40593
"Sasa Bremec" <sasa@i-tech.si> schrieb im Newsbeitrag news:3C8CDEDE.8040504@i-tech.si... > Hello! > > I'm looking for information about Motorola SPI interface implemented in > Xilinx Spartan FPGA. > > > I saw some cores on the web but I would like to do the hard job by my > self, that is why i am looking for some advice from the guy's that have > done this before me. I did this some time ago. Simply take any IC (ADC/ Serial FLASH etc) with SPI and look a the timing diiagramms. It comes down to some counters, state machines and shift registers. A nice project to learn much on HDL coding and simulation. -- MfG FalkArticle: 40594
Hello,
I am trying to instantiate a startup module in a spartan2e design.
When I run the constraints editor I get the following message which
comes from the translation phase of the design.
ERROR:NgdBuild:604 - logical block 'u0_startup' with type
'startup_spartan2' is
unexpanded. Symbol 'startup_spartan2' is not supported in target
'spartan2e'.
I have tried just replacing the spartan2 with spartan2e and the result
is basicly unchanged.
Where (specifically, I have already tried to find documentation myself)
can I get documentation on the startup module (especially for the
spartan2e parts)?
What happens if I don't instantiate a startup module? (Is one inferred
for me?)
Thanks,
Theron Hicks
Article: 40595peter, thank you very much. There is a reason why I´ve posted that. any_user: could somebody tell me why jtag programming is not working with my ispLSI 2023? Peter Alfke : I don´t know but you could use Xilinx XC95K or Coolrunner. any_user: Exist other firms which have such fpgas Peter Alfke: I don´t know but you could use Xilinx Virtex 2. etc etc etc. know what i mean?Article: 40596
Hello, I am in the process of designing a system where the clock will be distributed in a differential fashion. This clock will be buffered and sent to as many as 16 boards over short 50 ohm coax cables. Each board gets a pair of coax clock inputs. I have used a LVPECL distribution system before with no problems. I am considering replacing the LVPECL buffers with a single Spartan2E on the clock generator board for the system. I am already using a Spartan2E on each daughter card so it would have a good match between the signal levels from the clock generator and the daughter card clock inputs. The coax cables (RG316) are only about 10 cm long at most. The lines on the board are also 50 Ohm characteristic impedance. By the way, the clock frequency is 102.4 MHz and is coming from a LVPECL oscillator. The clock will be buffered in each FPGA via the clock DLL. The questions are: 1. Will this work well without aditional off chip buffering? 2. Do I need any more on chip buffering? 3. How should I terminate these signals? (What impedance and what termination voltage?) 4. Would an LVDS system be better in terms of noise, etc? Thanks, Theron HicksArticle: 40597
Isuser on drugs? I wish I could figure out how to kill file him.
Peter, Austin and others,
Keep up the good work. I wish other semiconductor vendors had half the help available that I
get here for free. BTW, that is why Xilinx is designed in to my product. Fortunately I have
that option available to me.
Isuser,
Did you ever consider that that is what they get paid for? Would you expect TI to
recomend an On-Semi part to replace a TI part? Do your own vendor research or live with the
free help.
Theron Hicks
lsuser wrote:
> peter, thank you very much.
>
> There is a reason why I´ve posted that.
>
> any_user: could somebody tell me why jtag programming is not working with my ispLSI 2023?
>
> Peter Alfke : I don´t know but you could use Xilinx XC95K or Coolrunner.
>
> any_user: Exist other firms which have such fpgas
>
> Peter Alfke: I don´t know but you could use Xilinx Virtex 2.
>
> etc etc etc.
>
> know what i mean?
Article: 40598
Sasa,
I placed a similar request a few weeks ago. I got a little help, but I
would recomend that you write your own code. The reason is that (in my
case) the various ADCs and DACs all are slightly different from each
other. Thus, while they may work with a specific processor, the optimal
design will vary. BTW, if you are talking about ADC and DAC parts, I found
the timing diagrams from Linear Tech to be simplest to implement and most
comprehensible.
Thanks,
Theron Hicks
Sasa Bremec wrote:
> Hello!
>
> I'm looking for information about Motorola SPI interface implemented in
> Xilinx Spartan FPGA.
>
> I saw some cores on the web but I would like to do the hard job by my
> self, that is why i am looking for some advice from the guy's that have
> done this before me.
>
> TNX SASH
Article: 40599The answer to that is very simple. Because it took me about 2 minutes to ask such a simple question which Peter answered in about 1 minute, very likely. On the other hand, I could have spent 15 minutes reading about the Hyperlynx tools (after finding the right page), spend what, maybe half an hour to a couple of hours downloading the tools, (I am working over a 28Kbps link) and then a couple more hours learning how to use the tool, setting it up, getting the result and then not trusting it since I have no way to make sure both I and the tool did it correctly. I have tried using "free" tools before that were provided by vendors. It is not uncommon that they don't work right, are hard to use or even crap out my machine (that happened to me with Swift Designer from TI for their power converter chips). So let me see... 3 minutes vs. 3 hours... Maybe Hyperlynx really is easy to use. But it is not justified at this point even if it takes 5 minutes to get the answer. I will be giving Hyperlynx a try later when I am ready to lay out the board. I have a 100 MHz SDRAM memory interface. But until then, I just need a little info to get the schematic finished. Thanks for the diagram. Seeing that encourages me to give it a try. Austin Lesea wrote: > > Simulate it with IBIS. > > Why does everyone avoid such a simple solution? The Hyperlynx demo is free, > and includes some useful IBIS models (like Xilinx parts). > > Austin > > rickman wrote: > > > I need to drive a CMOS device with a Spartan II E chip. The data sheet > > only guarantees 2.4 volts on the output at 24 mA. Nothing is said about > > lighter loads, for example a CMOS input. Working with an odd Vdd on the > > CMOS device of 3.8 volts, I get a Vih of 2.66 volts. Is it safe to > > assume that the Spartan device will pull fully to 3.3 volts (or very > > near) with such a light load? The input current on the CMOS device is > > <10 uA. Or should I use pullups? In spite of the data sheet note > > saying that the internal pullups should not be used to pull external > > signals, will they be sufficient to provide sufficient pullup with such > > a light load? I am not even sure if you can enable the pullups on pin > > used as outputs. Anyone have experience with this? > > > > -- > > > > Rick "rickman" Collins > > > > rick.collins@XYarius.com > > Ignore the reply address. To email me use the above address with the XY > > removed. > > > > Arius - A Signal Processing Solutions Company > > Specializing in DSP and FPGA design URL http://www.arius.com > > 4 King Ave 301-682-7772 Voice > > Frederick, MD 21701-3110 301-682-7666 FAX -- Rick "rickman" Collins rick.collins@XYarius.com Ignore the reply address. To email me use the above address with the XY removed. Arius - A Signal Processing Solutions Company Specializing in DSP and FPGA design URL http://www.arius.com 4 King Ave 301-682-7772 Voice Frederick, MD 21701-3110 301-682-7666 FAX
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