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On Tue, 12 Mar 2002 10:50:32 +0000 (UTC), Christopher.Saunter@durham.ac.uk (Christopher Saunter) wrote: >One 'gotcha' to watch out for with I2C is that the spec allows a >slave device recieving / transmiting data onto SDA to slow the clock, SCLK >down, by electrically overriding it, which the master has to notice and >obey. If the device you are talking to can do this, it's probably best >just to run with a slower clock and avoid the associated grief... I don't think that's allowed on SMBus. The slaves aren't allowed to drive SCL IIRC. One of the reasons that "two wire" interfaces that are nominally IIC are given a different name is that they aren't fully compatible with the spec, even though they interwork in every practical way. Regards, Allan.Article: 40651
In addition to all the other responses I'd like to add that the reason most of the manufacturers do'nt call it IIC has to with licensing fees to be paid to Philips, as it is 'their' protocol. They did sue a manufacturer a while ago if my memory serves me correctly. So this why they are called differently each time but the dataline-names will always have a reference to Clock and Data. Cheers, Jan Martin Wagenaar In article <3C8D8F19.108838BE@yahoo.com>, spamgoeshere4@yahoo.com says... > I need to implement a two wire interface used on a Cypress CY22393 clock > chip. The data sheet simply refers to it as "industry-standard > signaling". The two signal names are SDAT and SCLK. They give no info > on the logic or the timing of the interface. > > The ATmega devices include an interface they call, TWI, for two wire > interface. The signal names are SDA and SCL. Is this the same > interface? Why can I not find info (in a Yahoo search anyway) on any of > these names other than at Atmel or Cypress? Is this interface a real > orphan? > > I can likely use the Atmel data as a spec, but I would like to find a > real spec and be sure I am designing the right interface. I have a > request into Cypress, but so far I have not heard back. > >Article: 40652
Its more of the aiming the tools at the lowest common denominator bit. A properly targeted FPGA design rarely sees any benefit to the pipelining/retiming tools that are the latest rage. Allan Herriman wrote: > On Sat, 09 Mar 2002 09:01:19 +0000, Rick Filipkiewicz > <rick@algor.co.uk> wrote: > > >> I always have pipelining turned off though. > > > >How come ? Are there problems with it ? > > Hi Rick, > > No problems, but I think it is aimed at behavioural (i.e. bloated) > designs that have lots of combinatorial logic and few pipeline stages. > As Ray said, my desings mostly have very little logic between flip > flop stages, so the pipelining feature has little benefit. > > Regards, > Allan.Article: 40653
Leave the outputs floating. IIRC, you are a VHDL user. use the 'open' reserved word for in place of a signal name for output ports you don't want to connect. If the signals would be helpful in debug during simulation, it doesn't hurt to connect them to a loadless signal so that they are visible at the hierarchical level where the component is instantiated. A fifo empty signal owuld be a good example of this. The synthesizer will optimize out any outputs from the core that are not connected. Unused core inputs should be tied off to the constant that is appropriate to enable/disable the particular pins normal function. Antonio wrote: > Yes it's ok, the inputs connected to ground is always a good practice, > I was more interested to the output, in fact putting it to ground > seems to me that could force some electrical conflict, for example in > my project I don't use the empty flag of the FIFO Xilinx CORE, (...I > use the almost empty) , I think that the CORE would want to change the > Empty signal according to the state of the FIFO, what happens if I > shortcut this output to ground, is this a shortcircuit that bring up > dissipation and damage the device ??Article: 40654
Synthesis often collapses or renames internal signals as part of the optimization process. If you need to see an internal signal in a post synthesis simulation, you'll have to take steps to preserve that signal, which may affect your synthesis results. rg wrote: > when i simulate on RTL Mode,i can see all signal including input/output/wire/reg.but when i simulate on Gate-Level/Post Mode,some internal variable (wire/reg) cann't be founded.why?Article: 40655
Hi, The virtex2pro having 2 inbuild powerpc 405. Is it mean that, for any logic design the powerpc will be used to give the logic functionality? or If we need POwerpc we can use it? What is the special about having inbuild powerpc? Thanks and Regards, MuthuArticle: 40656
Thanks to everyone who posted. I am familiar with I2C, just not enough, I guess, to recognize it without its name. If the I2C name can't be used without paying license fees, is there a "generic" name for the same interface? Some posts seem to indicate that SMbus is similar and/or compatible. I guess that is the generic equivalent? I kinda like the Atmel name, TWI. It is easy to say and is an interesting abbreviation (as opposed to an acronym, Randy :). rickman wrote: > > I need to implement a two wire interface used on a Cypress CY22393 clock > chip. The data sheet simply refers to it as "industry-standard > signaling". The two signal names are SDAT and SCLK. They give no info > on the logic or the timing of the interface. > > The ATmega devices include an interface they call, TWI, for two wire > interface. The signal names are SDA and SCL. Is this the same > interface? Why can I not find info (in a Yahoo search anyway) on any of > these names other than at Atmel or Cypress? Is this interface a real > orphan? > > I can likely use the Atmel data as a spec, but I would like to find a > real spec and be sure I am designing the right interface. I have a > request into Cypress, but so far I have not heard back. -- Rick "rickman" Collins rick.collins@XYarius.com Ignore the reply address. To email me use the above address with the XY removed. Arius - A Signal Processing Solutions Company Specializing in DSP and FPGA design URL http://www.arius.com 4 King Ave 301-682-7772 Voice Frederick, MD 21701-3110 301-682-7666 FAXArticle: 40657
Dears Sirs, I would like to know if that is correct: - when the FPGA is clear (after a power-up or after a low pulse on /PROGRAM) all pins are pull-up; - all the unused not forced pins (after configuration) have a pull-up; - all the inputs (after configuration) don't have a pull-up. Thanks.Article: 40658
Was the question too simple ??Article: 40659
Hi, I'm fairly new to this kind of desinging circuitry. I've used VHDL at school to program some simple things, but what I want to do is the following. I want to connect my own circuitry (like a microcontroller or some other logic) to the PCI-bus of my computer. There are PCI interface ic's, but this also can be done using a fpga and an ip core from http://www.opencores.org . It's obvious I want to use the PCI-bridge core. This way my device keeps it's flexibility. Can someone please help me with finding a right fpga (type and/or manufacturer) and how to program this device? Like the cable I have to use, the software for compiling the core and the software to get the code into the fpga. Maybe there's someone out there who's actually used thos core in one of hos projects who can help me. I am really new at this, but I'm always in to learn :). Hope someone can help me woth this. Any help is appreciated. TimArticle: 40660
Muthu wrote: > What is the special about having inbuild powerpc? The advantage of built-in PowerPC microprocessor is that it connects very well to the logic fabric ( the CLBs, BlockRAMs, etc.) In Virtex-IIPro, each PPC has about 700 connections to the fabric, with several 64-wide busses. Obviously, you could use an external PPC, but that would not only mean an additional package, it would also mean many hundreds of FPGA pins being wasted on interfacing to the external PPC. More space, more power, less reliability, and most likely lower system performance. The tight and flexible connection between PPC and the logic is the biggest advantage. You can use the PPC for anything you want, from glorified state machine ( living off its two 16 Kbyte caches, to a full-fledged computer with its operating system residing in external RAM. This covers a very wider range. You can make many different trade-offs between hardware and software implementation, perhaps without ever changing the pc-board. Peter AlfkeArticle: 40661
rickman wrote: > Some posts seem to indicate that > SMbus is similar and/or compatible. I guess that is the generic > equivalent? SMBus is defined as a layer on top of I2C, and refers to that spec as well.Article: 40662
Erwin Rol wrote: > > Hmmm Rogue Wave makes several cross-OS libaries, so it seems like a poor > excuse to not just port a native version to Linux. Also cause Wine for > example doesn't run on PowerPC-Linux. Some people have in the past played around with PowerPC ports of Wine. There is not a fundamental problem with doing this, but there is little interest so far. This is of course because the one of the main focuses of wine is to run programs that are compiled for X86, and they would not run on a PowerPC even with wine. -- My real email is akamail.com@dclark (or something like that).Article: 40663
You need to check the data sheet and/or application note for the particular device manufacturer. As a for-instance, most Xilinx FPGAs can be configured (through pin connections) to provide either weak pullups or tristate conditions until properly configured. The device and manufacturer determine the exact behavior. Similarly, unused pins are different depending on device family. Diping wrote: > Dears Sirs, I would like to know if that is correct: > > - when the FPGA is clear (after a power-up or after a low pulse on > /PROGRAM) all pins are pull-up; > - all the unused not forced pins (after configuration) have a pull-up; > - all the inputs (after configuration) don't have a pull-up. > > Thanks.Article: 40664
To avoid sampling the clock, you could do something a little different: Have a toggle flip-flop clocked by clk10x. Use the positive and negative edges of the clk35x to sample the toggle output. When the sampled toggle value are different in the two time domains, you're at an edge of the clk10x. Which edge of the clk35x you use to sample the difference determines which edge you're on. In the past Ray Andraka's pointed out the troubles with using a DLL recovered clock to sample signals in the reference clock's domain - clock skew and jitter can sometimes make same-edge sampling unreliable. Depending on the allowable skew in your data sampling, you might be able to add a small phase shift in the DCM on the "safe" side. You might also figure out how to use the 90 degree version of the clk10x to give you the timing margin you need but detect a specific middle timeslot. Mark wrote: > I did consider the approach you mentioned. I've been rather spoiled, having > done nearly all synchronous designs. I don't have any real, meaning internal to > FPGA chips, experience with "sampling" one clock with another.Article: 40665
Hi I would recommand you to look into www.andraka.com there is a great tutorial on fir filter using distributed arithmetic I am sur It will help you jacky -- Use our news server 'news.foorum.com' from anywhere. More details at: http://nnrpinfo.go.foorum.com/Article: 40666
Erwin Rol <Erwin.Rol_nospam_@Q-Soft-Engineering.com> writes: > Hmmm Rogue Wave makes several cross-OS libaries, so it seems like a poor > excuse to not just port a native version to Linux. Also cause Wine for > example doesn't run on PowerPC-Linux. I don't know Rouge Wave, but I think I've seen the name flash by on some of my kids games. Maybe there will be a PS2 port :-) Most EDA vendors (Synopsys, Cadence etc.) support only a single Linux distribution (typically Red Hat on X86) so I don't have very high hopes for a PPC Linux. > Maybe if they just OpenSource it like Netscape did someone will port it > for them :-) But i am sure Xilinx doesn't like the idea that someone > might port support for Altera devices in the software, eventhough for > custumors it would be a good thing :-) Absolutely! Petter -- ________________________________________________________________________ Petter Gustad 8'h2B | (~8'h2B) - Hamlet in Verilog http://gustad.comArticle: 40667
David Brown wrote:
> Am I right in thinking that ABEL is only supported by a few vendors?
Yes.
> While this is
> going to be a Lattice/Mach project, it would be silly to spend a lot of
> effort learning a language that I can't otherwise use for other designs.
True.
> Does anyone have any pointers to VHDL tutorials on-line that concentrate on
> design, rather than on all the other parts of VHDL ? The ones I have found
> so far seem to mix in simulation-only aspects of the language along with
> synthesizable parts.
Better to get a book to get started.
Or grab some code examples to modify and run sim/synth tools on.
Google seach on something like:
architecture begin end group:*vhdl* insubject:Re:
Article: 40668Why don't you start off with an ISA bus card. Just to get your feet wet. Then if that works for you, then go into the more difficult interfaces like PCI. Timmestein <timmestein@hotmail.com> wrote in message news:<3c8e1b11$0$24817$e4fe514c@dreader3.news.xs4all.nl>... > Hi, > > I'm fairly new to this kind of desinging circuitry. I've used VHDL at > school to program some simple things, but what I want to do is the > following. > > I want to connect my own circuitry (like a microcontroller or some other > logic) to the PCI-bus of my computer. There are PCI interface ic's, but > this also can be done using a fpga and an ip core from > http://www.opencores.org . It's obvious I want to use the PCI-bridge core. > This way my device keeps it's flexibility. > > Can someone please help me with finding a right fpga (type and/or > manufacturer) and how to program this device? Like the cable I have to use, > the software for compiling the core and the software to get the code into > the fpga. > Maybe there's someone out there who's actually used thos core in one of hos > projects who can help me. > > I am really new at this, but I'm always in to learn :). > Hope someone can help me woth this. Any help is appreciated. > > TimArticle: 40669
Outputs not used should just be left unconnected, again, perhaps you'll save a few gates when the tools see the signal is unused and eliminate the logic that drives it. "floating" is a term I use to describe an input that is not being driven- bad; "unconnected" is the term I use to describe an output without a load- okay. dottavio@ised.it (Antonio) wrote in message news:<fb35ea96.0203112338.1b97a22f@posting.google.com>... > Yes it's ok, the inputs connected to ground is always a good practice, > I was more interested to the output, in fact putting it to ground > seems to me that could force some electrical conflict, for example in > my project I don't use the empty flag of the FIFO Xilinx CORE, (...I > use the almost empty) , I think that the CORE would want to change the > Empty signal according to the state of the FIFO, what happens if I > shortcut this output to ground, is this a shortcircuit that bring up > dissipation and damage the device ??Article: 40670
Yeah, I read this article. It's pretty weak. There will come a day when we will write HDL at such a level of abstraction we won't even need to know what a CLB looks like. That day is a long long way off. The tragedy is that some managers believe this hype and allocate valuable resources to it, ushering in a wave of weak, bloated, 50-levels-of-logic desgins.Article: 40671
"Kevin Neilson" <kevin_neilson@removethis-yahoo.com> wrote in message news:MNsj8.27108$af7.22802@rwcrnsc53... > Yeah, I read this article. It's pretty weak. There will come a day when we > will write HDL at such a level of abstraction we won't even need to know > what a CLB looks like. That day is a long long way off. The tragedy is > that some managers believe this hype and allocate valuable resources to it, > ushering in a wave of weak, bloated, 50-levels-of-logic desgins. Kevin, And that's when they call us! Simon Ramirez, Consultant Synchronous Design, Inc. Oviedo, FL USAArticle: 40672
i am looking for VHDL to implement cryptographic cyphers in an FPGA, and an FPGA with a PCI interface. does anybody have any ideas? --drakeArticle: 40673
giga_super_man <super@man.com> wrote in message news:<ee754ba.0@WebX.sUN8CHnE>... > why dont you just use the megawizard provided by Max+2 or quartus 2 to create the same functionality a being provided by RAMB4_S16_S16. If you need special functionality as write_first etc. this is not possible with current implementation of altdprame etc. You should be able to use the Quartus megawizard to configure the ram. Play around with the different ram types inside the megawizard. They are pretty straightforward. Or else if you are feeling lazy, I think we have a helpline which is answered by the apps people.Article: 40674
In article <MNsj8.27108$af7.22802@rwcrnsc53>, Kevin Neilson <kevin_neilson@removethis-yahoo.com> wrote: >Yeah, I read this article. It's pretty weak. There will come a day when we >will write HDL at such a level of abstraction we won't even need to know >what a CLB looks like. That day is a long long way off. The tragedy is >that some managers believe this hype and allocate valuable resources to it, >ushering in a wave of weak, bloated, 50-levels-of-logic desgins. And if they don't need to worry about the bloat and slowdown, there is no problem. My classic example: An academic implementation of a Rijndael core relies heavily on HDL synthesis, and uses an 8 stage pipeline for the single round. It ran at 100 MHz (according to static timing analysis) on a Virtex-6, using 2000 slices and 8 BlockRAMS, with expanded subkeys stored in Luts-as-ram. 1.2 Gbps throughput on nonfeedback modes, 150 Mbps throughput on feedback modes. My implementation relied heavily on hand placing and understanding the target architecture. It uses a 5 stage pipeline for the single round. It runs at 115 MHz (according to static timining analysis) on a Spartan II-5, using 800 slices and 10 BlockRAMs[1], with subkeys computed on the fly. 1.3 Gbps throughput on nonfeedback modes, 260 Mbps throughput on feedback modes. Ray Andraka probably could have added another 5-10% improvement [2]. So, by using a synthesis methodology instead of programming to the device, there is an ~10% penalty in throughput on nonfeedback modes, a ~70% penalty in throughput on feedback modes, and a ~60% penalty on area. If these costs don't matter, then synthesis worked fine. If costs DOES matter, then synthesis failed hideously, and someone who was doing this as part of a product would have to call one of the many FPGA expert consultants to have it done right. [1] The extra 2 BlockRAMs were for the sboxes in the subkey-generation. [2] Based that some of my design decisions were done on gut feel and in combination with other bits. It may be possible to shave off a cycle without hurting the clock TOO much, but I doubt it, but it may be possible to squeeze a little bit better with some better balancing, but it's hard to get much faster when you are hitting the BlockRAMs. -- Nicholas C. Weaver nweaver@cs.berkeley.edu
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Compare FPGA features and resources
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