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who have this book?Article: 40626
Useful for generating a quadrature signal as well, by using both Q outputs!
Copy and change to a fixed-width font (e.g. Courier) to view properly...
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Paul T
> The best and fastest divide-by four counter is a synchronous two-bit
Johnson
> counter, i.e. a two-bit shift register with the second-stage output Q
driving
> the first-stage D input through an inverter.
> That runs >250 MHz in any modern FPGA.
>
> Peter Alfke, Xilinx Applications
Article: 40627"Austin Franklin" <austin@dar55kroom.com> wrote in message news:u8qj6hieu1el9b@corp.supernews.com... > ...Hardware WEENIES don't draw schematics any more. ..." Yes, it says > exactly that. > > To start with, I find it unconscionable that a supposed professional, the > author, and a supposed professional magazine would allow the use of name > calling in an article. Please, Austin, don't get too worked up over being called a "hardware weenie." I know you've been called worse names than that ... and survived! Jim is simply trying to predict the future. As we all know, this is very hard to do. He may be right; he may be wrong. I do find some fallacies in his thinking, though. He says that C doesn't have parallelism. How about multiple C programs being compiled/synthesized into one netlist? Hmm, this sounds like concurrency, doesn't it? Also, this guy didn't say anything about analog hardware. Just recently I had a talk with an engineer who had problems with the latest FPGA technology devices. He said that the board was designed incorrectly and delivered some distorted signals to the FPGA. Sounds like some designs might need some signal integrity tools in the very near future! While the signal integrity tools are software, it takes someone that understands the analog/RF aspect of hardware design to work the tools and oversee the outcome. It isn't plug and play yet for the software guy, and his prospects are getting dimmer as signals get faster, as some hardware guys have found out. One may predict that some day there will be one icon on the computer, and someone will click it and out pops out exactly what the customer wanted. It may happen, but just like computer technology put an end to some blue collar jobs, it created jobs elsewhere. The trick is to follow the jobs. Simon Ramirez, Consultant Synchronous Design, Inc. Oviedo, FL USAArticle: 40628
lsuser <ls@swissonline.ch> wrote in message news:<ee7560e.0@WebX.sUN8CHnE>... > u should connect them to GND. Take a look in the (Altera) databook. Tells you exactly why you should do so. Information can be used for Lattice, Actel, Quicklogic, Triscend, Cypress,Atmel and Xilinx devices as well. Not generally true. Unused outputs you should leave unconnected. Unused inuputs you should tie to a valid logic level - GND or VDD. What level depends on the function of the input. / Jonas ThorArticle: 40629
What about this Xilinx app note with sample code on SPI... http://www.xilinx.com/xapp/xapp348.pdf "Sasa Bremec" <sasa@i-tech.si> wrote in message news:3C8CDEDE.8040504@i-tech.si... > Hello! > > I'm looking for information about Motorola SPI interface implemented in > Xilinx Spartan FPGA. > > > I saw some cores on the web but I would like to do the hard job by my > self, that is why i am looking for some advice from the guy's that have > done this before me. > > TNX SASH >Article: 40630
And I would not consider asking complex questions here of nearly any category. A newsgroup is not a place to get answers to complex questions. Unfortunately, I don't know what venue is a good way to get complex questions answered. I usually have to struggle to get answers and often find none. :) But I do appreciate Austin's efforts to promote a tool that he feels is very worth while. He has raised my awareness of SI issues and likely has tipped the scales so that I will be using the tool on the high speed bus and clocks. Peter Alfke wrote: > > It is true that the answer took me only a minute... > But that's because it was a simple question. > I will or can not answer complicated signal-integrity questions this way. > > Peter Alfke > > rickman wrote: > > > The answer to that is very simple. Because it took me about 2 minutes > > to ask such a simple question which Peter answered in about 1 minute, > > very likely. ...snip... -- Rick "rickman" Collins rick.collins@XYarius.com Ignore the reply address. To email me use the above address with the XY removed. Arius - A Signal Processing Solutions Company Specializing in DSP and FPGA design URL http://www.arius.com 4 King Ave 301-682-7772 Voice Frederick, MD 21701-3110 301-682-7666 FAXArticle: 40631
I need to implement a two wire interface used on a Cypress CY22393 clock chip. The data sheet simply refers to it as "industry-standard signaling". The two signal names are SDAT and SCLK. They give no info on the logic or the timing of the interface. The ATmega devices include an interface they call, TWI, for two wire interface. The signal names are SDA and SCL. Is this the same interface? Why can I not find info (in a Yahoo search anyway) on any of these names other than at Atmel or Cypress? Is this interface a real orphan? I can likely use the Atmel data as a spec, but I would like to find a real spec and be sure I am designing the right interface. I have a request into Cypress, but so far I have not heard back. -- Rick "rickman" Collins rick.collins@XYarius.com Ignore the reply address. To email me use the above address with the XY removed. Arius - A Signal Processing Solutions Company Specializing in DSP and FPGA design URL http://www.arius.com 4 King Ave 301-682-7772 Voice Frederick, MD 21701-3110 301-682-7666 FAXArticle: 40632
>who have this book? Take a look at my bok Real Chip Design and Verification Using Verilog and VHDL, 2002 isbn 0-9705394-2-8 . It provides los of guidel for design and verification, among other useful practical designs guides. See TOC and forewords at my site. ---------------------------------------------------------------------------- Ben Cohen Publisher, Trainer, Consultant (310) 721-4830 http://www.vhdlcohen.com/ vhdlcohen@aol.com Author of following textbooks: * Real Chip Design and Verification Using Verilog and VHDL, 2002 isbn 0-9705394-2-8 * Component Design by Example ", 2001 isbn 0-9705394-0-1 * VHDL Coding Styles and Methodologies, 2nd Edition, 1999 isbn 0-7923-8474-1 * VHDL Answers to Frequently Asked Questions, 2nd Edition, isbn 0-7923-8115 ------------------------------------------------------------------------------Article: 40633
"rickman" <spamgoeshere4@yahoo.com> wrote in message news:3C8D8F19.108838BE@yahoo.com... > I need to implement a two wire interface used on a Cypress CY22393 clock > chip. The data sheet simply refers to it as "industry-standard > signaling". The two signal names are SDAT and SCLK. They give no info > on the logic or the timing of the interface. >From their datasheet: The serial port uses industry-standard signaling in both stan-dard and fast modes. This section describes the unique fea-tures of the serial interface in this family of devices. The device address is a 7-bit value that is configured during Field Programming. By programming different device address-es, two or more parts can be connected to the serial interface and be independently controlled. The device address is com-bined with a read/write bit as the LSB and is sent after each start bit. This family of devices supports 1-byte memory addressing. The memory address is always sent after each Device Ad-dress/ Write bit combination. It describes the memory location within the device to be accessed. The memory address is in-cremented after each acknowledge, allowing sequential mem-ory access. To read a memory location, a write operation must be per-formed with the memory address to be read, and zero data bytes. This is followed by a repeated start bit and the Device Address/Read byte, after which the desired memory location is available for reading. -------------- That sounds like I2C. > The ATmega devices include an interface they call, TWI, for two wire > interface. The signal names are SDA and SCL. Is this the same > interface? Why can I not find info (in a Yahoo search anyway) on any of > these names other than at Atmel or Cypress? Is this interface a real > orphan? That definitely sounds like I2C. It's all over the place. --Keith BraffordArticle: 40634
On Tue, 12 Mar 2002 00:16:09 -0500, rickman <spamgoeshere4@yahoo.com> wrote: >I need to implement a two wire interface used on a Cypress CY22393 clock >chip. The data sheet simply refers to it as "industry-standard >signaling". The two signal names are SDAT and SCLK. They give no info >on the logic or the timing of the interface. > >The ATmega devices include an interface they call, TWI, for two wire >interface. The signal names are SDA and SCL. Is this the same >interface? Why can I not find info (in a Yahoo search anyway) on any of >these names other than at Atmel or Cypress? Is this interface a real >orphan? > >I can likely use the Atmel data as a spec, but I would like to find a >real spec and be sure I am designing the right interface. I have a >request into Cypress, but so far I have not heard back. Sounds a lot like what is often called the I2C protocol (that's I-squared-C.) You can look up a poor rendition of it on the Microchip 24C32A serial EEPROM device, for example. Their application notes are a little better, but not complete. Philips has a 46-pager: THE I2C-BUS SPECIFICATION VERSION 2.1 JANUARY 2000 You might look for it, too. Much better. JonArticle: 40635
rickman wrote: > > I need to implement a two wire interface used on a Cypress CY22393 clock > chip. The data sheet simply refers to it as "industry-standard > signaling". The two signal names are SDAT and SCLK. They give no info > on the logic or the timing of the interface. > > The ATmega devices include an interface they call, TWI, for two wire > interface. The signal names are SDA and SCL. Is this the same > interface? Why can I not find info (in a Yahoo search anyway) on any of > these names other than at Atmel or Cypress? Is this interface a real > orphan? SDA and SCL are the names used for i2c bus. To get info on that, grab any (AT) 24Cxx data sheet. Cypress may mean the same thing, but be using different names. Compare the limits from a 24Cxx for hints on if cypress is i2c There are other 2 wire bus designs. SMbus is a PC system BUS, similar to i2c. We have developed a 2 wire BUS called SPL, that has a smaller design footprint than i2c, and can use 80C51 Mode0 UART, for up to 10 MBaud link rates. Unlike i2c, it is fully clock syncronous eg A SPL Keypad Scanner fits in a 16V8. - jgArticle: 40636
Yes it's ok, the inputs connected to ground is always a good practice, I was more interested to the output, in fact putting it to ground seems to me that could force some electrical conflict, for example in my project I don't use the empty flag of the FIFO Xilinx CORE, (...I use the almost empty) , I think that the CORE would want to change the Empty signal according to the state of the FIFO, what happens if I shortcut this output to ground, is this a shortcircuit that bring up dissipation and damage the device ??Article: 40637
Hi John, The timing is spec'd for the clock, data, and the clock/data relationship. Also, I didn't explicitly mention this, but as you obviously understood, the transmitted clock, clk10x, is also used to determine the data "framing" for 7 timeslots. This clock is used to process the data, hence, I also called it the system clock. I did consider the approach you mentioned. I've been rather spoiled, having done nearly all synchronous designs. I don't have any real, meaning internal to FPGA chips, experience with "sampling" one clock with another. Also, I'm a Xilinx newbie and am now at the point of getting up to speed with constraints, the timing analyzer, etc. (I've been trying to get on a project using Xilinx FPGAs for several years. 12 months ago, I got on one. 6 months ago, I started working on the design entry and learning the Xilinx tools.) I don't think my approach could ever work. It was to use signals from the different clock domains to align the state machine to the timeslots. I cannot logically see that any synchronous combination of such signals could detect the difference between any two adjacent timeslots. I think I understand your approach. I do use the ddr structures in the IOBs and have been able to "recover" data from the timeslots in the correct order. The transmitted clock, clk10x, is input to a DCM. Its clock outputs go to BUFGs. Thank you! Mark John_H wrote: > What timing is associated with the generation of the stream you're > recovering? If the clk10x comes from the transmitter and corresponds to all > 7 timeslots with specific timing guarantees (i.e. does the rising edge of > clk10x always correspond to timeslot 6 with specified setup and hold?) you > should be okay. > > My thoughts are you can use the clk35x to sample the clk10x (this makes the > clk10x non-global for the sampling but should be okay) and figure out your > alignment from the samples. You need setup but no hold on the sampling (a > little negative hold in many cases) so phase aligned clocks should give you > stable sampling. The samples produce different patterns for the two locked > conditions allowing you to select the appropriate phasing. > > If you use the ddr structures in the IOBs, you'll still have to do your > external alignment to extract your odd information from the even pairing so > having a state machine control the selection mechanism should be straight > forward. > > Enjoy! > > Mark wrote: > > > Hello, > > > > I'm trying to align an input "receiver" to ddr data in an XC2V6000-5. > > The ddr data rate is 7x the 1x "system" clock. > > > > (The following are waveforms that are best viewed with a > > non-proportional/fixed-width font.) > > ______ ______ __ > > clk10x _/ \______/ \______/ > > _ _ _ _ _ _ _ _ > > clk35x_p _/ \_/ \_/ \_/ \_/ \_/ \_/ \_/ \ > > _____________________________ > > locked __/ > > > > _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ > > ddr_data X6X0X1X2X3X4X5X6X0X1X2X3X4X5X6X0 > > - - - - - - - - - - - - - - - - > > ______ ______ __ > > clk10x _/ \______/ \______/ > > _ _ _ _ _ _ _ _ > > clk35x_p \_/ \_/ \_/ \_/ \_/ \_/ \_/ \_/ > > _____________________________ > > locked (2) __/ > > > > - clk10x and clk35x_p are phase-locked and clk10x rising edges are > > "aligned" with clk35x_p's every 7 3.5x clock cycles. > > - locked is synchronous to clk10x. It could be made synchronous to > > clk35x_n. > > - clk35x_n is also available. It is 180 deg phase locked/shifted from > > clk35x_p. > > - ddr_data is input to the ddr register. Its output is every other ddr > > data at the 3.5x rate. > > > > - Using clk35x_p after locked goes high, the output of the ddr register > > is 1,3,5,0,2,4,6,.... > > - Using clk35x_p after locked (2) goes high, the output is > > 0,2,4,6,1,3,5,0,.... > > - This difference is due to an odd number, 7, of 3.5x clock cycles > > occurring in two 1.0x clock cycles. > > > > The approach I've been trying is to align a state machine to the data by > > determining which data, 1 or 0, is "first", using bits that toggle at > > the different clock rates. > > > > I think I've been staring at this too long and need to get out of my > > "box" to find a solution. I would greatly appreciate any thoughts. > > > > Thank you, > > MarkArticle: 40638
Just when I think I am getting somewhere about the languages, I find out more and end up changing my mind yet again... Am I right in thinking that ABEL is only supported by a few vendors? I have had a brief look at information on tools from Altera, Atmel and Xilinx, and none of them appear to support ABEL as far as I can see. While this is going to be a Lattice/Mach project, it would be silly to spend a lot of effort learning a language that I can't otherwise use for other designs. Does anyone have any pointers to VHDL tutorials on-line that concentrate on design, rather than on all the other parts of VHDL ? The ones I have found so far seem to mix in simulation-only aspects of the language along with synthesizable parts. Thanks for all your comments so far. David Brown "David Brown" <david_no_spam@no.spam.westcontrol.com> wrote in message news:a6i15k$4qa$1@news.netpower.no... > Hi, > > I am trying to convert an old project written in MachXL DSL to a more modern > Mach device. Since the current Lattice software does not support DSL, I am > going to have to convert to another design language. As far as I can see, > my choices are Verilog, VHDL and ABEL. I was recommended to learn either > Verilog or VHDL, preferably VHDL since that is more used here in Europe, but > no mention was made of ABEL. As far as I can see, however, ABEL is a much > simpler language, which should be more than sufficient for my needs. As far > as I have understood it from what I have read so far, both Verilog and VHDL > are simulation languages, and only a small part of the language is actually > synthesizable in hardware, whereas ABEL is designed as as hardware > description language. I have little experiance with PLD/FPGA design, apart > from a couple of projects several years ago. I will probably be doing a bit > more in the future, so it is useful to learn a portable language rather than > tying myself specifically to the one device family, but PLD/FPGA design will > only ever be a minor part of my job (mostly low-level microcontroller > programming, and some electronic design). I'd value any comments about what > language would be the best choice before I get too far down the wrong road. > > > -- > David Brown > WestControl a.s > Norway > >Article: 40639
Petter Gustad wrote: > Erwin Rol <Erwin.Rol_nospam_@Q-Soft-Engineering.com> writes: > > >>hamish@cloud.net.au wrote: >> >>>B. Joshua Rosen <bjrosen@polybus.com> wrote: >>> >>> >>>>environment. I read a mention somewhere, either here or in the wine >>>>group, that they intend to have a fully native version next year. The >>>>GUIs are written using a tool that puts out both Windows and Unix code, I >>>>think they are waiting for that tool to support Linux. >>>> >>>> >>>UNIX GUIs (ie X11) will already work on Linux - no changes required. >>> >>> >>Well it is unlikely they use bare X11, it is more likely they use >>Motif/CDE under HP-UX and Solaris. And Motif 2.x and CDE are poorly >>supported under Linux (unless you buy a commercial version, which will >>cost you additional money). So Wine might be the easier (and cheaper) >>solution here. >> > > There are quite a few Motif based applications available under Linux. > Motif is available under the Open Group Public License: > > http://www.opengroup.org/openmotif/license/ > > The sources can be downloaded from the same site. > > However, the Xilinx GUI based apps (nder Solaris) does not seem to be > linked with Motif (unless they are statically linked), e.g. the > floorplanner appears to be linked with some other libraries > (libRogueWave, libXdh, libGui_Framework, etc.). Hmmm Rogue Wave makes several cross-OS libaries, so it seems like a poor excuse to not just port a native version to Linux. Also cause Wine for example doesn't run on PowerPC-Linux. Maybe if they just OpenSource it like Netscape did someone will port it for them :-) But i am sure Xilinx doesn't like the idea that someone might port support for Altera devices in the software, eventhough for custumors it would be a good thing :-) - Erwin > > Petter >Article: 40640
On Sat, 09 Mar 2002 09:01:19 +0000, Rick Filipkiewicz <rick@algor.co.uk> wrote: >> I always have pipelining turned off though. > >How come ? Are there problems with it ? Hi Rick, No problems, but I think it is aimed at behavioural (i.e. bloated) designs that have lots of combinatorial logic and few pipeline stages. As Ray said, my desings mostly have very little logic between flip flop stages, so the pipelining feature has little benefit. Regards, Allan.Article: 40641
This is a multi-part message in MIME format. --------------ADC389981E14EB96E11BDDB6 Content-Type: text/plain; charset=iso-8859-1 Content-Transfer-Encoding: 8bit Hi, When you say download are you talking about JTAG or something similar. If my memory serves me correctly, there are 2 family members: 7200 and 7300. The 7200 is OTP and can only be programmed either by Xilinx hardware (HW120 or older with the correct programming adaptor) or another 3rd party programmer. The 7300 is a Windowed EPROM, so can be erased! Dave xchecker wrote: > Hi, > > for a new project I would like to use some older Xilinx FPGA´s (XC7272). Please dont tell me that I should use Virtex 2 parts because we do have excess inventory of the XC7272 FPGA´s. > > Im using XACT Step software and xchecker programming hardware. Simulation shows that application (decoder logic and fast statemachine)is working as expected. But, I cant download programming file into FPGA. My distributor tells me´that the FPGAs are defective. I believe they want to sell new FPGAs. > > Can anybody help me please? > > regards > > B. Braon / FPGA Consults ItalyArticle: 40642
PlsArticle: 40643
"rickman" <spamgoeshere4@yahoo.com> wrote in message news:3C8D8F19.108838BE@yahoo.com... Sounds like an IIC bus. (I squared C). Try Philips or TI for datasheets. Happy Hunting Phil -- Posted via Mailgate.ORG Server - http://www.Mailgate.ORGArticle: 40644
As far as I remember, XC7200/7300 had 2 versions, one was OTP and one with a Window for UV-erasing(making it re-programmable). Obviously the UV-version was for initial design phase for testing, and then for production one was supposed to use OTP. Cost difference was also 5x. Programming was not through JTAG, but only using Xilinx HW-130 programmer + correct adapter or a third-party programmer supporting this family (Data I/O,Hi-Lo, BP etc.) So essentially you need to convert your bitstream (.bit) file to a .mcs file (hex, intel-hex) depending upon the programmer you use. I think XACT step had this utlity to convert (PROM file formatter?) to hex format for programming. HTH -Neeraj Mark <mark@data_com.it> wrote in message news:<ee7566d.0@WebX.sUN8CHnE>... > Ciao, > > You could try to program the FPGAs with another PC. Maybe this would help. In the past I used ALtera EPM7128S devices which I programmed with a Bitblaster download cable.But: this was not possible with my notebook computer.I had to chnage the PC and it worked fine. > > Good Luck, MarkArticle: 40645
Hi Flora Check out www.tyder.com They have a downloadable filter design program demo Alan Alan McKitterick University of Strathclyde Glasgow "Flora Cathy" <floreq10@hotmail.com> wrote in message news:<ab390bfac576680790f39445990beea7.61115@mygate.mailgate.org>... > heya > for case study, i am looking for a symmetric filter of 32 taps or MORE > i want a real applicable FIR. looking for the FIR coefficients > > anticpated thanks > > ~CATHYArticle: 40646
when i simulate on RTL Mode,i can see all signal including input/output/wire/reg.but when i simulate on Gate-Level/Post Mode,some internal variable (wire/reg) cann't be founded.why?Article: 40648
The best place to look for a description of I2C is probably the Philips website, but I never found it that easy to find... Google search for 'I2C filetype:pdf site:philips.com' The spec is entry no 3 in the resutls. One 'gotcha' to watch out for with I2C is that the spec allows a slave device recieving / transmiting data onto SDA to slow the clock, SCLK down, by electrically overriding it, which the master has to notice and obey. If the device you are talking to can do this, it's probably best just to run with a slower clock and avoid the associated grief... I think there's a VHDL I2C core over at opencores.org, but I can't get there at the moment. Cheers, Chris SaunterArticle: 40649
how do i get this book?
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Compare FPGA features and resources
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