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John, Never thought of that. Thanks. I have stated that the jitter from the DCM is random, and various people have challenged that claim, but here is yet another way to 'prove' it, visually. Normally, we show randomness by performing the FFT on the jitter histogram, and by observing the output with a spectrum analyzer. If a set of spectral peaks show up in the output spectrum, they are probably there due to jitter induced by other things switching, and coupling into the interconnect and IOBs. Austin John_H wrote: > Austin Lesea wrote: > > > All, > > > > I had lunch with our video interface guru, and he sees no degradation from using the > > DCM insofar as pixel jitter is concerned up to his fastest video rate, which is ~ 50 > > MHz on CRT's. > > Using a DCM to produce a fixed frequency can generate acceptable jitter. Any DCM jitter > should be distributed about the "ideal" timing edge as some form of additive white noise. > > The trouble with using DPLL techniques is that they (typically) would use an NCO approach > to slave to the reference edge. The NCO produces jitter that can be very correlated > line-to-line. Visual artifacts can blossom rather than just fuzz.Article: 40351
"Ray Andraka" <ray@andraka.com> schrieb im Newsbeitrag news:3C851DAE.46C92F2C@andraka.com... > Yeah, that too, although we call them elastic buffers in our library to > differentiate them from the other fifos. They are also very handy for Whats the difference between a FIFO and an elastic buffer? -- MfG FalkArticle: 40352
> Although not the question you asked, Altera basically did the same thing > when they moved from APEX 20K (supported 5V PCI according to their > datasheet, manufactured in TSMC's 0.22u process) to APEX 20KE (dropped > 5V PCI support, manufactured in TSMC's 0.18u process). Not directly related to PCI, but doesn't the 20KE datasheet show that you can get 5V tolerance by adding a series input resistor? - but if the input clamp diodes aren't enabled until configuration is complete, then Vin > V Abs Max? !!! Paul TArticle: 40353
In our library, one uses RAM, the other uses SRL16's. The SRL16 version is a bunch faster and smaller too. Falk Brunner wrote: > "Ray Andraka" <ray@andraka.com> schrieb im Newsbeitrag > news:3C851DAE.46C92F2C@andraka.com... > > Yeah, that too, although we call them elastic buffers in our library to > > differentiate them from the other fifos. They are also very handy for > > Whats the difference between a FIFO and an elastic buffer? > > -- > MfG > FalkArticle: 40354
"Austin Lesea" <austin.lesea@xilinx.com> wrote in message news:3C85105F.97DF6B49@xilinx.com... > I have heard from some folks: > > That even with Linux on the PC platform, that 2 Gbytes is the limit. There > are people looking into why this is. Stay tuned for the answer. This may be > related to the hardware they are using, or the build of Linux.... Are you sure it doesn't relate to the 32 bit address space (4 GB) of the x86 class processor? Windows, I know reserves the high 2 Gb of memory for the operating system, leaving the lower 2 GB for application data. It may be possible to squeeze the OS space to 3GB as a special version is reputed to do, but the basic limitation in the CPU addressing. > > Austin > > Austin Lesea wrote: > > > We have Linux support now.....nice low cost way to break out of the 2Gbyte > > limit of Windows on PC platforms. Dell supports a 4Gbyte memory, that > > could be used by Linux. > > > > http://www.xilinx.com/prs_rls/software/0225_Em_Linux.html > > > > Austin > > > > M Schreiber wrote: > > > > > all, > > > Has anybody found a good method for implementing designs using the > > > Xilinx 4.1 ISE (under windows) that require more than 2GB of memory > > > for the place and route? I have read that Xilinx now supports their > > > tools running Linux (using WINE). Does this new method allow users to > > > exceed the 2GB limitations or is this a function of application > > > executable? We are looking to complete an upcoming design that may > > > require a Virtex 2 (xc2v8000) and xilinx recommends that you need at > > > least 3 GB of memory for place and route. What are most people doing > > > to overcome this? Are there any relatively cheap unix based machines > > > ($<10,000) that can accomplish this? Any recommendations would be > > > greatly appreciated. > > > Thanks in Advance, > > > Mike Schreiber > > > hardware engineer > >Article: 40355
Hi, I tried using the "timing constraint export" option with the FPGA exp synthesis, because I had some clock skew problem. Now the P&R is taking forever : more than 10 hours for a Virtex 2000E where I'm only using 50% of the slices. The Computer I use is Dual PIII 1GHZ with 4Gb of SDRAM. Is this normal ? Do you get runtime like this ? Thanks, Guillaume. Sorry if it's a stupid question.Article: 40356
[Note: apologies if you receive multiple copies of this msg.]
*** SECOND CALL FOR PAPERS ***
----------------------------------------------------------
11TH IEEE/ACM INTERNATIONAL WORKSHOP ON LOGIC & SYNTHESIS
http://www.iwls.org
JUNE 4-7, 2002
LOCATION:
Chateau Le Moyne,
New Orleans, Louisiana
(in French Quarter)
----------------------------------------------------------
==> NOTE: IWLS-02 is pleased to be co-located with <==
DAC-02 (www.dac.com) in New Orleans
----------------------------------------------------------
The International Workshop on Logic and Synthesis (IWLS) provides an
international forum to promote research and exchange ideas about all
aspects of IC synthesis, optimization, and verification. The workshop
encourages early dissemination of ideas and results. Accepted papers
are distributed to only IWLS participants.
The workshop format includes short talks, posters, a panel discussion,
and a social evening gathering. To further simulate interaction among
participants, there will be exercises in collaborative problem
solving. Attendees will be divided into groups, each tackling a
challenging problem submitted through the web and selected by the
focus group chair. The EDA community is encouraged to submit logic and
synthesis problems through http://www.iwls.org/ . Example problems
and details will be available in early January.
Topics of interest range across a variety of system-description
levels, including hardware/software, behavioral, architectural,
RTL, logic-level and transistor-level. Topics include, but are
not limited to:
* Architectures & Compilation
* Synthesis & Optimization
* Power & Timing Analysis
* Design Validation & Verification
* Design experiences
These topics span both synchronous and asynchronous domains,
in all technologies including CMOS, ECL, GaAs, and Adiabatic.
Authors may submit extended abstracts for their proposed
presentation. These must be no less than 1000 words and no greater
than 2500 words (i.e. 5 pages double column, 10 pt font). We
especially encourage submissions in the early stages of research,
which may highlight important new problems without necessarily
providing complete solutions. Only electronic submissions will
be accepted. See http://www.iwls.org for submission details. For
questions, contact program_chair@iwls.org.
Submission deadline for PAPERS and PROBLEMS: March 15, 2002
Notice of acceptance: April 15, 2002
Final version due: May 8, 2002
The workshop is co-sponsored by the IEEE Computer Society and
the ACM SIGDA. Travel grants may be obtained by applying to ACM
SIGDA's travel grant program at:
http://www.sigda.acm.org/Programs/TravelGrant/
Organizing Committee:
General Chair: Soha Hassoun (Tufts University)
Program & Publicity Chair: Steven Nowick (Columbia University)
Focus Group & Problem Chair: Yuji Kukimoto (Silicon Perspective)
Panel Chair: Diana Marculescu (CMU)
Benchmark Chair: Andreas Kuehlmann (Cadence)
Technical Program Committee:
I. Bahar (Brown University)
M. Berkelaar (Magma Design Automation)
R. Brayton (U.C. Berkeley)
J. Cortadella (UPC, Spain)
E. Dubrova (KTH, Sweden)
M. Fujita (University of Tokyo)
E. Jacobs (TU Eindhoven)
T. Kam (Intel)
V. Kravets (IBM T.J. Watson)
A. Kuehlmann (Cadence)
Y. Kukimoto (Silicon Perspective)
W. Kunz (University of Frankfurt)
D. Marculescu (CMU)
Y. Matsunaga (Kyushu University)
C. Meinel (University of Trier)
S.-I. Minato (NTT Network Innovation Labs)
R. Murgai (Fujitsu Labs of America)
K. Sakallah (University of Michigan)
T. Sasao (Kyushu Inst. of Technology)
H. Savoj (Magma Design Automation)
E. Sentovich (Cadence Berkeley Labs)
N. Shenoy (Synopsys)
L. Stok (IBM T.J. Watson)
T. Villa (PARADES, Italy)
Article: 40357
"Young-Su Kwon" <yskwon@vslab.kaist.ac.kr> wrote:
>Dear FPGA experts,
>
>I want to write synopsys library file (.lib) for FPGA.
>Usually XILINX and other FPGA companies support
>Synopsys db file, but the target I want is to generate Synopsys
>db file from .lib file.
>I have written the following library file.
>
>> library (si03) {
>> technology ( fpga ) ;
>>
>> ...
>> cell(LUT2) {
>> area : 1.000;
>> pin(I0) {
>> direction : input;
>> capacitance : 1.0000;
>> }
>> pin(I1) {
>> direction : input;
>> capacitance : 1.0000;
>> }
>> lut(L) {
>> input_pins : "I0 I1";
>> }
>> pin(Z) {
>> direction : output;
>> function : "L"
>> capacitance : 1.0000;
>> }
>> }
>>
>
>and it was successful to convert it to .db file.
>When I have tried to synthesis my simple design,
>the error messages from fpga compiler(from Synopsys) came out.
>
>> ------------ Message from dc_shell-------------
>> Error: Target library must contain a usable N-input lut cell. (OPT-910)
>> Error: Compile terminated abnormally. (OPT-100)
>> Current design is 'TEST1'.
>> 0
>
>It means that there are problems in LUT description.
>How can I describe LUT in .lib file?
The problem is that your function definition is faulty. You need to
define what the LUT2 does. You can't expect to get synopsys to fill in
what the LUT will do. Instead of defining a LUT2 you need to generate
(say) NAND2 and have something like function:"!(I0 & I1)". You should
define all 1 to 4 input functions as cells. Of course such a library
will have to be optimized again by Xilinx toolset to map the cells to
actual LUTs.
Muzaffer
FPGA/ASIC DSP Design/Verification Consulting
http://www.dspia.com
Article: 40358Kevin Brace <ihatespam99kevinbraceusenet@ihatespam99hotmail.com> wrote in message news:a63bum$p8s$1@newsreader.mailgate.org... ... > I guess I am now critical of Altera because of my bad experiences with > QII 2.0 WE + LeonardoSpectrum-Altera 2002 Level 1 NativeLink issue when > FLEX10KE or ACEX1K is the target device. Kevin, You have been exceedingly critical of Altera long before QII v2.0 WE was ever released. There gets to be a point when unsolicited "Boy this sucks, the other guys do it so much better" comments start to loose credibility - especially when they're not even part of a "how do I fix this?" or as and answer to someone's question. I'm sorry you've had a bad experience with the Altera tools. You might want to give Altera's tech support hotline a try at 800-800-EPLD since Altera doesn't pay their employees to monitor this newsgroup. If, however, you're just interested in being a troll, it would be nice if you could mark your posts as such. > So, what is the big deal about it, Altera? I'm not familiar enough with Xilinx's tools to know whether the level-of-effort settings serve the same purpose as the Quartus II fast-fit option. However, part of "the big deal" may be that this mode where the fitter is specially tuned for "pretty good" results and the shortest run times is not available in the previous versions of Quartus II. Not everyone who's now using Quartus II was previously using Xilinx tools. -Pete-Article: 40359
I've seen increased PAR runtime when the constraints file contains a large number of constraints. I would suggest trying to consolidate the constraints if possible. Also, the Answers Database gave the following solution when the Query was : "4.1 and par and memory and usage": http://support.xilinx.com/xlnx/xil_ans_display.jsp?iLanguageID=1&iCountryID=1&getPagePath=13270Article: 40360
Hi everyone i am using apex20k400e's ESB to act as register file, asyn read and syn write, but now I met with synthesis/simulation mismatch, if asyn read will cause any problem ?Article: 40361
Thank you all of your responses. I am new in Canada, so I cant go to USA unless getting an offer first. But maybe I should go to Toronto or Ottawa 'cause somebody says that it is a little easier to find a job there than in Vancouver. Is there anyone from Toronto or Ottawa? Could you please tell a little about this kind of job market there? I have no much stuff yet, so I can move very easily. Jay <kayrock66@yahoo.com> wrote in message news:d049f91b.0203041516.589a1f21@posting.google.com... > Come on down to the CA (California that is), I have head hunters > calling all the time... > > "Albert" <wagain@hotmail.com> wrote in message news:<01kf8.239995$I8.48176768@news4.rdc1.on.home.com>... > > Hi, > > > > I have many years of experience on DSP/embedded system and FPGA/CPLD design. > > I'm in Vancouver and looking for jobs. If the company you work for has any > > opening or you know any job opportunities that my skills fit, and your > > information finally leads to my job, I will be glad to share half of my > > first two months' net income to you. I guarantee it. I will be glad to > > relocate to other cities in Canada. It is double wins, for me, I got a job > > and sharing my half of salary to you is absolutely no problem, and for you, > > that position you know will doom to be filled by someone finally, why don't > > you do me a favor? > > > > I appreciate any reply. My email address is: wagain@hotmail.com. > > > > > > Thank you for your time. > > > > AlbertArticle: 40362
Peter Ormsby wrote:
>
>
> Kevin,
>
> You have been exceedingly critical of Altera long before QII v2.0 WE was
> ever released.
Although, I don't believe I was "exceedingly" critical of Altera
stuff, I was critical of free tools I downloaded from Altera like
LeonardoSpectrum-Altera Level 1 2001.1a.028 which crashed really easily
like when I stopped synthesis by pressing "Stop" button.
Although I have been using Xilinx ISE WebPACK for months, its synthesis
tool (XST) never crashes like that.
Shouldn't I be critical if something crashes so badly like that?
Yes, I use a Windows 98 PC which is known for its legendary instability,
but still XST doesn't crash like that.
You might say that Altera didn't write LS (Mentor Graphics/Exempler
Logic did), but if it is so buggy that it crashes when stop button is
pressed why is Altera distributing such software, even if it is free?
One of my major complaint of QII 1.1/2.0 (only tried Web Edition
though) is that for some reason, QII drains Windows 9x's system
resources much more heavily than ISE WebPACK.
Because Windows 98 is so bad, I always have to put Resource Meter on the
side of my screen, and whenever QII is running, I see it draining large
amounts of system resources, which comes back if I exit QII, but each
time this happens, I have to interrupt what I was doing, and I don't
like that.
Altera seemed to have made no improvements there compared to QII 1.1.
I read somewhere that Altera doesn't recommend using QII under Windows
98, and instead recommend using Windows NT 4.0 or 2000, but I sort of
suspect that is because the system resource issue.
I do notice that Altera uses much more graphics than Xilinx in QII, and
that might be another reason why it drains system resources heavily.
From what I see, the improvements made from QII 1.1 to 2.0 seems
small, although I do appreciate that Altera added ACEX1K support in QII
2.0 WE, but other than that not too much has changed.
Perhaps, Altera should have called QII 2.0 as QII 1.2.
I guess raising the version number is important to show that major
improvements are being made, so that people will upgrade, but I think if
things don't improve too much, that turns into disappointment.
The problem I had with QII 2.0 + LS-Altera (NativeLink) +
FLEX10KE was something that QII 2.0's NativeLink script tried to
reference "flex10ke.syn" instead of "flex10e.syn."
Being a beginner of QII tools, I had no idea what was going on until I
was told to look at the LS-Altera's directory for the file, and after I
noticed that small file name difference, it was easy to workaround it
(make a copy, and rename it to match QII 2.0's NativeLink script), but
it also shows that Altera must have forgotten to test QII 2.0 (Verilog
flow) + LS-Altera (NativeLink) + FLEX10KE or ACEX1K combination before
releasing.
Not only that, in QII 1.1, NativeLink with LS-Altera (2001.1a_28) didn't
even start (crashed at Quartus_cmp.exe), and I suspect lack of testing
for the crash.
Having seen these software problems, it is not surprising to me
that no wonder Altera has only 10% of a highend FPGA market, and rest of
90% belongs to Xilinx.
I read some time ago on EE Times that much of the reason customers
choose Virtex instead of APEX20K several years ago is because the
quality of Quartus wasn't as good as Xilinx's software offering at the
time.
To me, software stability seems to be Altera's weakest point even now.
I believe my past criticisms of Altera, and the complaints I
made here are fairly valid ones, from a Xilinx ISE WebPACK user's point
of view, because it seem like Altera has lost so many users to Xilinx
that the only way it can bring them back will be to listen to customer
complaints, and fix the problems.
If they don't, they will likely keep loosing market share to Xilinx, and
I personally don't like to see Xilinx becoming too dominant (It is
always good to have a strong No. 2.).
> There gets to be a point when unsolicited "Boy this sucks,
> the other guys do it so much better" comments start to loose credibility -
> especially when they're not even part of a "how do I fix this?" or as and
> answer to someone's question.
>
Okay, I did forget that A vs. X debate in this newsgroup always
gets nasty, so I guess I should have been a little more careful, or
maybe I shouldn't have asked this question all together, but couldn't
resist posting this question because it seemed like a such a small
feature being advertised as a big deal.
I guess that is called a marketing hype, and I guess I don't really like
marketers that much.
> I'm sorry you've had a bad experience with the Altera tools. You might want
> to give Altera's tech support hotline a try at 800-800-EPLD since Altera
> doesn't pay their employees to monitor this newsgroup. If, however, you're
> just interested in being a troll, it would be nice if you could mark your
> posts as such.
>
I never meant to be a troll, but just wanted to make fun of
marketers who hype a feature that existed at its competitor's products
probably for years.
Okay, it will be fair to criticize Xilinx for conducting "System Gate"
marketing for years which was totally meaningless because RAM bits were
also counted as part of that System Gate number.
> I'm not familiar enough with Xilinx's tools to know whether the
> level-of-effort settings serve the same purpose as the Quartus II fast-fit
> option. However, part of "the big deal" may be that this mode where the
> fitter is specially tuned for "pretty good" results and the shortest run
> times is not available in the previous versions of Quartus II. Not everyone
> who's now using Quartus II was previously using Xilinx tools.
>
> -Pete-
I nowadays keep the P&R effort level to "Lowest" when I want to
see how many levels of LUT XST generated for a critical timing path.
Being able to choose wide range of P&R effort level allows me not to
waste time P&Ring because all I want to know is the levels of LUT for
some signals paths after P&R.
One thing nice about QII is that it lets the user see the equations, and
as far as I know, Xilinx doesn't let me do that, but overall Xilinx
tools seem more stable, runs faster, and doesn't drain Windows 9x's
system resource like the way QII does.
Kevin Brace (Don't respond to me directly, respond within the
newsgroup.)
Article: 40363how do i write the initialize file(.coe) or edit INIT value after generated a single-port Ram? for example:in this ram,it is 16x256. how do i make it 256 differet value after initializtion?Article: 40364
mschreiber75@yahoo.com (M Schreiber) wrote in message news:<e8caa675.0203050633.59597cca@posting.google.com>... > all, > Has anybody found a good method for implementing designs using the > Xilinx 4.1 ISE (under windows) that require more than 2GB of memory > for the place and route? I have read that Xilinx now supports their > tools running Linux (using WINE). Does this new method allow users to > exceed the 2GB limitations or is this a function of application > executable? We are looking to complete an upcoming design that may > require a Virtex 2 (xc2v8000) and xilinx recommends that you need at > least 3 GB of memory for place and route. What are most people doing > to overcome this? Are there any relatively cheap unix based machines > ($<10,000) that can accomplish this? Any recommendations would be > greatly appreciated. > Thanks in Advance, > Mike Schreiber > hardware engineer We've run into memory problems when running PAR for a V2-6000 on Win2K machines (more than 2 GB RAM installed). Aside from general address-space problems, we've found that Xilinx has (had?) a problem with its tools: when running the PAR tool, it didn't release allocated memory when moving from Place to Route phase. We've worked around this problem by splitting the PAR into two separate processes. To do that, you must change from GUI design-flow to script design-flow (which you probably have to do anyway in a large design: the GUI doesn't allow full control of all required tool options). General Memory Problem: the problem is that a 32-bit processor (like all x86 PCs) has 4 GB of address space. x86 processors have been able for some years to support more than 4 GB of physical memory, but accessing it is awkward (similar to the infamous segmented addresses of 16-bit x86). All MS OSes split the virtual address seen by each application into two: user and OS space. In most versions, each application has 2 GB of address space and the other 2 GB is allocated to the OS. There are Advanced Server versions of both NT 4 and Win2K which allocate 3 GB to the user application; but they are VERY expensive (thousands of $); it's an expensive solution to install in every workstation. I've read somewhere that Linux can allocate 3 GB of virtual address-space for user applications, but I am not familiar with Linux. The best solution is to move to 64-bit processors: Sun, IBM and HP (and some others) offer 64-bit workstations now, and there are a lot of EDA tools available (including all Xilinx tools). This is also a pretty expensive solution: workstations are much more expensive than PCs (probably slower nowaday), and EDA S/W for Unix is usually much more expensive than the same S/W for Windows (not familiar with Linux pricing). Right now, we are eagerly waiting for the AMD Hammer - this appears to be the perfect solution for us Windows users who are trying to build big FPGAs.Article: 40365
In article <44b0ca4e.0203052147.7d093159@posting.google.com>, Assaf Sarfati <assaf_sarfati@yahoo.com> wrote: >Right now, we are eagerly waiting for the AMD Hammer - this appears to be >the perfect solution for us Windows users who are trying to build big FPGAs. The hammer looks like a GREAT solution, assuming Microsoft will support it. The cost of the 64 bit extention is remarkably low (4% area penalty, according to AMD), and AMD is already beating Intel on the performance side. The SMP solution for 2-8 nodes is also nice and clean. What I worry is that M$ will only support the hammer under NT "Server" variants, meaning that it wouldn't be accesable for workstation use and CAD tools. Also, it will still require a recompilation/restructuring to take advantage of the 64 bit address space. -- Nicholas C. Weaver nweaver@cs.berkeley.eduArticle: 40366
Jan Gray wrote: > > See www.xilinx.com/virtex2pro . > > Congratulations to Xilinx on another blockbuster achievement. It's a bit of > a cliche, but the arrival of V2Pro and the Altera Excallibur family marks a > huge turning point for the programmable logic industry. Assuming they are > priced competitively, I think these new devices, and the forthcoming cores > libraries and system builder tools that will accompany them, will prove > irresistable to nearly all embedded systems designers -- so that (say) three > years from now there will be "tons" of programmable logic in all but the > most cost constrained new designs. It's the full employment act for FPGA > designers! :-) > > The debut of these parts is also exciting because it represents the > continued "democratization" of cutting edge technologies. You don't need a > "million unit order" to get access to fast embedded processors, fast logic, > fast embedded RAMs, fast serial links, clock management, a rich cores > library, etc. > > As for V2Pro, gigabit links and PowerPCs aside, I applaud the extra generous > helpings of BRAM provided in these new devices. > > I have posted some early news links and commentary, including a small table > comparing V2 and V2Pro devices, at www.fpgacpu.org/#020304. > > Jan Gray > Gray Research LLC Can anyone tell me (without making me visit yet another web site today) what is special about V2Pro? Is this the V2 chip with on board PPC or other screaming CPU? -- Rick "rickman" Collins rick.collins@XYarius.com Ignore the reply address. To email me use the above address with the XY removed. Arius - A Signal Processing Solutions Company Specializing in DSP and FPGA design URL http://www.arius.com 4 King Ave 301-682-7772 Voice Frederick, MD 21701-3110 301-682-7666 FAXArticle: 40367
In article <3C85B110.F0FC60DE@yahoo.com>, rickman <spamgoeshere4@yahoo.com> wrote: >what is special about V2Pro? Is this the V2 chip with on board PPC or >other screaming CPU? 0-4 PowerPC cores (32b, integer only, 5 stage pipeline, up to 300 MHz), with close ties into the BlockRAMs (can use the BlockRAMS for I/D memories). Single cycle 16 bit MACs, full 32x32 hardware multiplier. 4-16 (depending) 3 Gbit serial I/O channels. The processor cores aren't that impressive (considering this is a .13 micron, 9 layer copper process, hell, .25 uM synthesized standard cell sparc run at 130), but the integration looks potentially cool. -- Nicholas C. Weaver nweaver@cs.berkeley.eduArticle: 40368
On Wed, 6 Mar 2002 06:02:53 +0000 (UTC), nweaver@CSUA.Berkeley.EDU (Nicholas Weaver) wrote: >In article <44b0ca4e.0203052147.7d093159@posting.google.com>, >Assaf Sarfati <assaf_sarfati@yahoo.com> wrote: >>Right now, we are eagerly waiting for the AMD Hammer - this appears to be >>the perfect solution for us Windows users who are trying to build big FPGAs. > >The hammer looks like a GREAT solution, assuming Microsoft will >support it. The cost of the 64 bit extention is remarkably low (4% >area penalty, according to AMD), and AMD is already beating Intel on >the performance side. The SMP solution for 2-8 nodes is also nice and >clean. > >What I worry is that M$ will only support the hammer under NT "Server" >variants, meaning that it wouldn't be accesable for workstation use >and CAD tools. > >Also, it will still require a recompilation/restructuring to take >advantage of the 64 bit address space. hopefully Xilinx will start supporting native Linux so there won't be a need for any MS OS to run FPGA EDA tools. Muzaffer Kal http://www.dspia.com ASIC/FPGA design/verification consulting specializing in DSP algorithm implementationsArticle: 40369
Nicholas Weaver wrote: > The hammer looks like a GREAT solution, assuming Microsoft will > support it. And it will be an even better solution, if M$ software isn't running at all ;-) Linux for x86-64 is up and running afaik ;-) And since Xilinx and most other EDA vendors support Linux now, why step down to the bluescreen? And yes, Linux user processes are normally limited to 3 GB memory on 32bit plattforms like x86. LarsArticle: 40371
Hello, do you know an FPGA which supports an LVDS interface? For my diploma thesis I need one FPGA which has an LVDS interface, so far I can find onyl one from Xilinx and Altera, there are more firms which have such FPGAs? Thank you for your answer. bye martinArticle: 40372
Anyone knows if ISE Webpack supports Virtex QPRO devices ? I know it supports Virtex II and Virtex E up to 300K gates but what = about QPRO Virtex ? Thanks in advance.Article: 40374
In article <3C85105F.97DF6B49@xilinx.com>, Austin Lesea
<austin.lesea@xilinx.com> writes
>I have heard from some folks:
>
>That even with Linux on the PC platform, that 2 Gbytes is the limit. There
>are people looking into why this is. Stay tuned for the answer. This may be
>related to the hardware they are using, or the build of Linux....
>
>Austin
I'm not sure exactly, but there was an article in uk.comp.os.linux
recently which mentioned that by default there are limits on how RAM is
allocated. If you are prepared to re-compile your kernel (*) you can
fiddle with
CONFIG_NOHIGHMEM=y
and change it to n (no).
Alan
(*) I'm of course referring to the Linux kernel here, not Windows :-)
<snip>
--
Alan Fitch
DOULOS Ltd.
Church Hatch, 22 Market Place, Ringwood, Hampshire BH24 1AW, United Kingdom
Tel: +44 1425 471223 Email: alan.fitch@doulos.com
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