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Hello, I am using Xilinx ISE 4.1 SP3 with the Synplify VHDL flow. I am getting some "phantom" timing contraints appearing in the map and par timing reports which seem to have come from nowhere (they are not in my ucf file) and they have no NETs attached to them. Can anyone shed any light on where these might have come from? Here they are: (map first, then par) Cheers, Ken ============================================================================ ==== Timing constraint: OFFSET = OUT 1000 nS AFTER COMP "DSP_CLK" ; 0 items analyzed, 0 timing errors detected. ---------------------------------------------------------------------------- ---- ============================================================================ ==== Timing constraint: OFFSET = OUT 1000 nS AFTER COMP "SYS_CLK" ; 2 items analyzed, 0 timing errors detected. Minimum allowable offset is 7.537ns. ---------------------------------------------------------------------------- ---- ============================================================================ ==== Timing constraint: OFFSET = IN 1000 nS BEFORE COMP "SYS_CLK" ; 26 items analyzed, 0 timing errors detected. Minimum allowable offset is 0.721ns. ---------------------------------------------------------------------------- ---- ============================================================================ ==== Timing constraint: OFFSET = IN 1000 nS BEFORE COMP "DSP_CLK" ; 0 items analyzed, 0 timing errors detected. ---------------------------------------------------------------------------- ---- >From PAR report: ---------------------------------------------------------------------------- ---- OFFSET = OUT 1000 nS AFTER COMP "DSP_CLK | | | " | | | ---------------------------------------------------------------------------- ---- OFFSET = OUT 1000 nS AFTER COMP "SYS_CLK | 1000.000ns | 12.669ns | 3 " | | | ---------------------------------------------------------------------------- ---- OFFSET = IN 1000 nS BEFORE COMP "SYS_CLK | 1000.000ns | 3.305ns | 2 " | | | ---------------------------------------------------------------------------- ---- OFFSET = IN 1000 nS BEFORE COMP "DSP_CLK | | | " | | | ---------------------------------------------------------------------------- ----Article: 40276
> I have installed Xilinx Foundation 2.1i on a Windows98 machine with an HP > 932c usb direct connected printer. Does the USB printer use "LPT3:" or something like that? Can you print to a file, then copy the file to LPT3: ??? PaulArticle: 40277
Suppose I have 6 inputs and 2 outputs like so: x <= a xor b xor c xor d; y <= b xor c xor d xor e xor f; Targeting 4 input LUTs, "x" requires one LUT because it has 4 inputs. "y" requires two LUTs since it has 5 inputs. However, it's possible to rewrite "y" as such: y <= x xor a xor e xor f; This "y" is a 4 input function! My circuit could be as small as two LUTs (one for "x" and one for "y")! Experimentally, I find that Xilinx XST 4.0.3 and Synplify Pro 7.0.3 both use 3 LUTs for this circuit. Even when I write "y" to explicitly depend on "a" and "x", the synthesizer removes the redundant input "a" and ends up with the 3 LUT solution. Is it true that these synthesizers will always remove unnecessary inputs without regard for circuit size? Said another way, can I count on the synthesizer to not add extra inputs to my function in order to minimize circuit size? Is this behavior common to other synthesizers? Thanks, Paul ButlerArticle: 40278
The speed of your system might suggest a more cost-effective approach. I worried a little when you mentioned you "need lots of inputs." Some of the shopping around I've been doing recently has put me into programmable devices much larger than I need in order to get my I/O. If you need the high output count because of many 16 bit parallel words bouncing around your system at 100kHz speeds (or something on that order) consider using one or two higher speed busses that read/write to/from inexpensive registers. If you have serial links, don't even think about making them parallel before coming onto the FPGA - parallel/serial conversion is cheap inside these devices. Conversely, external parallel/serial conversion to interface a serial stream to the FPGA could make life easier: no high speed busses to coordinate, just the channels you're using. With the bit-serial multipliers Ray mentioned, this approach could pay off nicely. Remco Poelstra wrote: > Hi, > > I want to build a digital mixing console, using an FPGA for the signal > processing, so I can do it (almost) all in parrallel. I need a lot of > multipliers for that task. What's the best FPGA to do that? I heard that > there are FPGA's with build-in multipliers, so I can spend the gates at > other things, is this true? Which FPGA's have build-in multipliers? Btw, > I also need a lot of input pins... > > Thanks for any advice, > > Remco PoelstraArticle: 40279
Ray, no doubt that performance is highly dependent on quality of source code. But, it is also highly dependent on features of the target device architecture. Up to now Xilinx had a clear advantage (especially when performing any multiplication) over Altera. That changed. It may change again when Xilinx will introduce its new family of devices. Anyway, what is the problem? I donīt care if there is brand A or brand x as device marking. I will choose the architecture which will solve my design and performance needs in a most efficient way. That was Xilinx for the last three years and now it is Altera.Article: 40280
In my Synplify experience, I've found little reason to have the very general timing constraints I specify in the Synplify tool to end up in the Xilinx flow. To make sure this doesn't happen, the item to "generate vendor constraints file" needs to be turned off within the Synplify environment. The option generates an "ncf" file (I'm pretty sure that's the suffix) that could be deleted to avoid the phantom timing for stuff you've already compiled. The Xilinx flow specifies an order for constraint interpretation such that a ucf will override anything stated differently in the ncf. Anything that's not respecified is kept. Ken Mac wrote: > Hello, > > I am using Xilinx ISE 4.1 SP3 with the Synplify VHDL flow. > > I am getting some "phantom" timing contraints appearing in the map and par > timing reports which seem to have come from nowhere (they are not in my ucf > file) and they have no NETs attached to them. > > Can anyone shed any light on where these might have come from? > > Here they are: (map first, then par) > > Cheers, > > Ken > > ============================================================================ > ==== > Timing constraint: OFFSET = OUT 1000 nS AFTER COMP "DSP_CLK" ; > > 0 items analyzed, 0 timing errors detected. > > ---------------------------------------------------------------------------- > ---- > > ============================================================================ > ==== > > Timing constraint: OFFSET = OUT 1000 nS AFTER COMP "SYS_CLK" ; > > 2 items analyzed, 0 timing errors detected. > > Minimum allowable offset is 7.537ns. > > ---------------------------------------------------------------------------- > ---- > > ============================================================================ > ==== > > Timing constraint: OFFSET = IN 1000 nS BEFORE COMP "SYS_CLK" ; > > 26 items analyzed, 0 timing errors detected. > > Minimum allowable offset is 0.721ns. > > ---------------------------------------------------------------------------- > ---- > > ============================================================================ > ==== > > Timing constraint: OFFSET = IN 1000 nS BEFORE COMP "DSP_CLK" ; > > 0 items analyzed, 0 timing errors detected. > > ---------------------------------------------------------------------------- > ---- > > From PAR report: > > ---------------------------------------------------------------------------- > ---- > OFFSET = OUT 1000 nS AFTER COMP "DSP_CLK | | | > " | | | > ---------------------------------------------------------------------------- > ---- > OFFSET = OUT 1000 nS AFTER COMP "SYS_CLK | 1000.000ns | 12.669ns | 3 > " | | | > ---------------------------------------------------------------------------- > ---- > OFFSET = IN 1000 nS BEFORE COMP "SYS_CLK | 1000.000ns | 3.305ns | 2 > " | | | > ---------------------------------------------------------------------------- > ---- > OFFSET = IN 1000 nS BEFORE COMP "DSP_CLK | | | > " | | | > ---------------------------------------------------------------------------- > ----Article: 40281
Jim Granville wrote: > Try and qualify on the leading edge of WRITE, rather than LOW write. -- I agree. -- Try adding a variable last_wr so you can say: if wr = '0' and last_wr = '1' then . . . -- Mike TreselerArticle: 40282
Paul wrote: > > However I also now use ActiveHDL and that > controls the command line of both > LS (for synthesis) and Q2 for P&R OK. I agree that the editor/simulator is the place to fire off sim,synth,route scripts, because that is where I spend most of my time. Let the dog wag his own tail. My usage of sim:synth:route is about 1000:10:1 Many synth runs are just sanity checks. I don't want to route them all. Vendor supplied integration scripts often don't work at all or don't work like you want. -- Mike TreselerArticle: 40283
The problem starts when you communicate between logic or registers clocked by different clocks that are asynchronous with respect to each other. In those interfaces, you will unavoidably violate the set-up requirements of the receiving logic. If you keep the interface one bit wide, you "only" have to worry about metastability, if it's wider the problems are much worse. The best advice is: Don't do it! Design synchronous systems, or be prepared to spend a lot of intelligent work on solving asynchronous problems. Peter Alfke, Xilinx Applications =========================== satya wrote: > Hi all, > I got a doubt and hope this group clears my doubt.I have a core which > is to be implemented in a virtex fpga.In the core I have three cores > which offer at different frequencies.so,when I try to implement in the > fpga,I will have asynchronous domains.Is it allowed?as for my > knowledge,all blocks should operate at the same frequency(??).please > clear my doubt. > > Regards > - satyaArticle: 40284
"David Hawke" <dhawke@xilinx.com> schrieb im Newsbeitrag news:3C833429.27285B2C@xilinx.com... > Antonio, > > Attach a TNM to the Clk_enable net, and then apply it to the gouping. The TNM will be > forward propagated to all the synchronous elements attached to the net: > > NET clk_enable TNM = clk_en; > TIMESPEC TS_multi_cycle = FROM clk_en TO clk_en 30; I dont think so. Since this is a CLOCK ENABLE signal, it must propagate within 1 clock cycle, NOT 2,3 or more. The clock enable is NO multicycle path. Only the data from one stage to another can have a propagation time of more than one clock cycle (when using a multi-cycle path). -- MfG FalkArticle: 40285
ray_morales@ureach.com (Ray Morales) wrote in message news:<1930f35d.0203040656.663cacd6@posting.google.com>... > Jim Granville <jim.granville@designtools.co.nz> wrote in message news:<3C82C4A4.47B4@designtools.co.nz>... > > Ray Morales wrote: > > > > > > for some odd reason, about 2% of writes that set xcs or rst are > > > failing (i.e. wrong value is set). reads seem to be quite stable > > > [always give the right value]. > > > > Is the 8051 clocked from the 24.576MHz, or in another clock domain ? > > > > Try and qualify on the leading edge of WRITE, rather than LOW write. > > > > 8051 is clocked from another clock domain entirely. > > What do you mean 'qualify'? > Oh (just got it :-) you mean rather than saying "if ( wr = '0' )", say "if ( falling_edge(wr) )". I will try that -- I normally try not to stray too far from "process(clk, rst)" pattern not to confuse leonardo spectrum but perhaps that is a little too conservative. falling_edge is probably better, but i still don't see why what i did won't work... thanks.Article: 40286
"satya" <satya@iwavesystems.net> schrieb im Newsbeitrag news:82741d43.0203040526.4825fb2a@posting.google.com... > Hi all, > I got a doubt and hope this group clears my doubt.I have a core which > is to be implemented in a virtex fpga.In the core I have three cores > which offer at different frequencies.so,when I try to implement in the > fpga,I will have asynchronous domains.Is it allowed?as for my It is allowed, but having less clock domains is always good. Since virtex has 4 global clock nets, this is no problem. When transfering datas between these clock domains, do it clean, means by use of asynchronous FIFOs or simmilar proofen methods. -- MfG FalkArticle: 40287
Ray Morales wrote: > > ray_morales@ureach.com (Ray Morales) wrote in message news:<1930f35d.0203040656.663cacd6@posting.google.com>... > > Jim Granville <jim.granville@designtools.co.nz> wrote in message news:<3C82C4A4.47B4@designtools.co.nz>... > > > Ray Morales wrote: > > > > > > > > for some odd reason, about 2% of writes that set xcs or rst are > > > > failing (i.e. wrong value is set). reads seem to be quite stable > > > > [always give the right value]. > > > > > > Is the 8051 clocked from the 24.576MHz, or in another clock domain ? > > > > > > Try and qualify on the leading edge of WRITE, rather than LOW write. > > > > > > > 8051 is clocked from another clock domain entirely. > > > > What do you mean 'qualify'? > > > > Oh (just got it :-) you mean rather than saying "if ( wr = '0' )", say > "if ( falling_edge(wr) )". I will try that -- I normally try not to stray > too far from "process(clk, rst)" pattern not to confuse leonardo spectrum but > perhaps that is a little too conservative. falling_edge is probably better, > but i still don't see why what i did won't work... thanks. The problem is crossing clock domains. To qualify on the falling edge, you need ( in CUPL ) FIELD Wd = [Wd1,Wd0]; Wd.ck = Sys24MHz; Wd.d = [Wd0,WRN]; WriteFALL = Wd1 & !Wd0; WRN ============\_______________________/========== Data XXXXXX________________________________XXXXXXXX Sys24MHz / / / / / WriteFALL __________/========\______________________ With wide enough WRN, you probably do not need to latch the WRITE data path, but as the C51 speed increases, you could need to latch the DATA on WRN fall, to allow WriteFALL to go past WRN rise. ( two clock domains ). You can also use both Sys clock edges ( maybe not in MAX3000a ? ) to reduce the 'push right' effects. FIELD Wd = [Wd1,Wd0]; Wd0.ck = !Sys24MHz; Wd1.ck = Sys24MHz; Wd.d = [Wd0,WRN]; WriteFALL = Wd1 & !Wd0; WRN ============\_______________________/========== Data XXXXXX________________________________XXXXXXXX Sys24MHz / \ / \ / \ / \ / WriteFALL __________/====\______________________ -jgArticle: 40288
I am using fpga compilerII and i get warnings like "initial values for signals not suppoted for synthesis.....so will be ignored", "configuration specifications are not supported for synthesis...". But i am getting zero errors.....and finally get a bitfile. Can these warnings (or any other warnings) cause damage to the fpgas if the bit file is loaded onto the fpga? -ChinmayArticle: 40289
Come on down to the CA (California that is), I have head hunters calling all the time... "Albert" <wagain@hotmail.com> wrote in message news:<01kf8.239995$I8.48176768@news4.rdc1.on.home.com>... > Hi, > > I have many years of experience on DSP/embedded system and FPGA/CPLD design. > I'm in Vancouver and looking for jobs. If the company you work for has any > opening or you know any job opportunities that my skills fit, and your > information finally leads to my job, I will be glad to share half of my > first two months' net income to you. I guarantee it. I will be glad to > relocate to other cities in Canada. It is double wins, for me, I got a job > and sharing my half of salary to you is absolutely no problem, and for you, > that position you know will doom to be filled by someone finally, why don't > you do me a favor? > > I appreciate any reply. My email address is: wagain@hotmail.com. > > > Thank you for your time. > > AlbertArticle: 40290
Ray makes a very good point- for audio frequencies, a bit serial implimentation of your multipliers will more than suffice so you could use vendor A or vendor X, which ever you prefer. Regards Ray Andraka <ray@andraka.com> wrote in message news:<3C8130D0.1B58ABB0@andraka.com>... > The Xilinx VirtexII is the only device that has them that you can buy > today. Altera announced its Stratix line a little more than a week ago, > which also has dedicated multipliers. You'll have to talk to a distributor > to fins out when you can get one. > > That said, I am assuming you are talking about audio mixing. If that is the > case, you can get into a smaller, cheaper device by working with bit serial > arithmetic for the mixing. In that case, the multiplier is little more than > an adder. See the multiplier page on my website (when it comes back > up...seems the ball got dropped in transferring the domain name to the new > ISP so it may be a day or so before you can get to the website). > > Remco Poelstra wrote: > > > Hi, > > > > I want to build a digital mixing console, using an FPGA for the signal > > processing, so I can do it (almost) all in parrallel. I need a lot of > > multipliers for that task. What's the best FPGA to do that? I heard that > > there are FPGA's with build-in multipliers, so I can spend the gates at > > other things, is this true? Which FPGA's have build-in multipliers? Btw, > > I also need a lot of input pins... > > > > Thanks for any advice, > > > > Remco Poelstra > > -- > --Ray Andraka, P.E. > President, the Andraka Consulting Group, Inc. > 401/884-7930 Fax 401/884-7950 > email ray@andraka.com > http://www.andraka.com > > "They that give up essential liberty to obtain a little > temporary safety deserve neither liberty nor safety." > -Benjamin Franklin, 1759Article: 40291
Chinmay wrote: > I am using fpga compilerII and i get warnings like "initial values for > signals not suppoted for synthesis.....so will be ignored", > "configuration specifications are not supported for synthesis...". > But i am getting zero errors.....and finally get a bitfile. Can these > warnings (or any other warnings) cause damage to the fpgas if the bit > file is loaded onto the fpga? > > -Chinmay No, as long as the bitfile DRC passes you should be o.k. at least internally. Of course if your code relies on the initial values or config specifications it might not work and its always possible that the error could propagate to external bus contention - but most modern devices are pretty tolerant of this.Article: 40292
I believe that David did get it right. clk_en is a TNM. It is attached to net clk_enable. The path tracer traverses the net clk_enable and attaches the TNM clk_en to synchronous elements such as RAMs and FFs. The timespec then sets a path constraint between these elements. What would have helped here is another TNM and timespec: Inst "name_of_ff_that_sources_clk_enable" TNM = clken_src_ff; timespec TS_clk_enable_distribution = FROM clken_src_ff TO clk_en 10; Philip On Mon, 4 Mar 2002 19:51:42 +0100, "Falk Brunner" <Falk.Brunner@gmx.de> wrote: >"David Hawke" <dhawke@xilinx.com> schrieb im Newsbeitrag >news:3C833429.27285B2C@xilinx.com... >> Antonio, >> >> Attach a TNM to the Clk_enable net, and then apply it to the gouping. The >TNM will be >> forward propagated to all the synchronous elements attached to the net: >> >> NET clk_enable TNM = clk_en; >> TIMESPEC TS_multi_cycle = FROM clk_en TO clk_en 30; > >I dont think so. Since this is a CLOCK ENABLE signal, it must propagate >within 1 clock cycle, NOT 2,3 or more. The clock enable is NO multicycle >path. Only the data from one stage to another can have a propagation time of >more than one clock cycle (when using a multi-cycle path). Philip Freidin FliptronicsArticle: 40293
I'm working on a project that involves run-time reconfiguration of VHDL designs on a Xilinx FPGA. With run-time reconfiguration, the FPGA is dynamically reconfigured at run-time to solve the current task at hand. Is there any support for the simulation of run-time reconfiguration in Xilinx EDA tools? I heard that the new Xilinx Foundation 4.2i tools support partial run-time reconfiguration. How would one test/simulation such a design? How, if at all, is run-time reconfiguration realized in a VHDL testbench? Thanks for your time. Kris NicholsArticle: 40295
Hi everyone I am using synplicty 6.2.4 to synthesis and then use modelsim non-OEM version 5.5e to simulate,the target device is altera's apex20k400e according to the doc of quartus, I modify the modelsim.ini to add the following line Veriuser = E:\quartus\eda\mentor\modelsim\convert_hex2ver.dll in my design there is sn block rom, it's content is store in a .hex file, so the convert_hex2ver is need to convert the .hex into .ver but when I start the simulation, I found thatthe rom have not been init to corrct content, and I also found that the .ver file have not been generate why? thank you in advanceArticle: 40296
I've been looking closely at the Stratix device. I do like what I see. However, what I am seeing for the most part brings it more or less to parity with the Xilinx offerings. It represents the first serious contender for DSP designs out of the A camp, as they have finally gotten something reasonable for arithmetic. The previous architectures were all seriously crippled by the arithmetic carry chain architecture. The stratix has a kind of bandaid fix that at least lets it handle add/subtract and accumulators with load/clear in one level of logic. The bandaid fix is the addition of an XOR in front of the pair of 3 LUTs and some changes to the carry chain to permit a controlled add/subtract. This is still not as flexible as the structure used in the Xilinx devices for the past decade. Another remaining advantage Xilinx has is the infamous SRL16. These not only make for compact small delay queues (which can be made up for with the stratix memory architecture), but also serve as reloadable LUTs, which is very handy for things like reloadable distributed arithmetic. Sure, with the addition of fast multipliers, the need for DA may be reduced, but it is still a very useful tool in the shed. Multipliers alone don't make a chip a good DSP platform, and in fact I can still get more function out of CLBs than I can from a multiplier (to wit, the design described in my paper "FPGAs make radar on a chip a reality" has a multiplier density that gets about 3CLBs per multiplier, and the filter is programmable without reconfiguration). The jury is still out as to which vendor has silicon better suited to maximum performance DSP, but if I were a betting man I'd put my money on Xilinx right now. That said, I think Altera is leading in terms of their DSP IP, now that they have a half decent platform to put it in we'll have to see where that goes. phil wrote: > Ray, no doubt that performance is highly dependent on quality of source code. But, it is also highly dependent on features of the target device architecture. Up to now Xilinx had a clear advantage (especially when performing any multiplication) over Altera. That changed. It may change again when Xilinx will introduce its new family of devices. Anyway, what is the problem? I donīt care if there is brand A or brand x as device marking. I will choose the architecture which will solve my design and performance needs in a most efficient way. That was Xilinx for the last three years and now it is Altera.Article: 40297
Hi Paul, Try this x <= ((a xor b) xor (c xor d)); y <= (( b xor c) xor (d xor e) xor f); Juggle with the parenthesis. Regards, SANKET. "Paul Butler" <Paul.Butler@ni.com> wrote in message news:<u877thegcjnsa6@corp.supernews.com>... > Suppose I have 6 inputs and 2 outputs like so: > > x <= a xor b xor c xor d; > y <= b xor c xor d xor e xor f; > > Targeting 4 input LUTs, "x" requires one LUT because it has 4 inputs. "y" > requires two LUTs since it has 5 inputs. However, it's possible to rewrite > "y" as such: > > y <= x xor a xor e xor f; > > This "y" is a 4 input function! My circuit could be as small as two LUTs > (one for "x" and one for "y")! > > Experimentally, I find that Xilinx XST 4.0.3 and Synplify Pro 7.0.3 both use > 3 LUTs for this circuit. Even when I write "y" to explicitly depend on "a" > and "x", the synthesizer removes the redundant input "a" and ends up with > the 3 LUT solution. > > Is it true that these synthesizers will always remove unnecessary inputs > without regard for circuit size? Said another way, can I count on the > synthesizer to not add extra inputs to my function in order to minimize > circuit size? Is this behavior common to other synthesizers? > > Thanks, > Paul ButlerArticle: 40298
Hi, Can anyone suggest me a method of converting a vhdl netlist in to either EDN or EDF or XNF netlist? (I am using Xilinx Fondation Tool 4.1i) thanks PraveenArticle: 40299
ssy wrote:
> I am using synplicty 6.2.4 to synthesis and then use modelsim non-OEM
> version 5.5e to simulate,the target device is altera's apex20k400e
...
> in my design there is sn block rom, it's content is store in a .hex
> file, so the convert_hex2ver is need to convert the .hex into .ver
>
> but when I start the simulation, I found thatthe rom have not been
> init to corrct content, and I also found that the .ver file have not
> been generate
Consider defining your rom as an array of constant vectors and let
synplicity do the heavy lifting.
-- Mike Treseler
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