Custom Search
Site Home Archive Home FAQ Home How to search the Archive How to Navigate the Archive
Compare FPGA features and resources
Threads starting:
Authors:A B C D E F G H I J K L M N O P Q R S T U V W X Y Z
That is a slight shift in the party line. During the SpartanII non-availability
fiasco two years ago the standard party line was to develop and use the XCV50 until
the spartans came out, that the bitstreams were the same. I have several customers
who cut over to the spartanII parts once they became available, with no absolutely
no changes other than a BOM change.
Marc Baker wrote:
> There are variable amounts of don't care bits in the bitstream that account for
> slight variations in counting the total bitstream length. The Spartan-II data
> sheet has been updated a couple times since the 3/3/2000 version, with the
> current one from March 2001 indicating the same bitstream length as the XCV100:
> 781,216, which is the current bitstream length created by the Xilinx development
> system.
>
> Bitstreams created for one family may work in another, but Xilinx does not test
> the parts that way and cannot guarantee that they will work. We strongly
> recommend creating the bitstream for the target device.
>
> The Spartan-II and Virtex families share the same JTAG family ID code, as do the
> Spartan-IIE and Virtex-E families. The software ignores any variations in
> revision, so it cannot differentiate between Virtex and Spartan devices of the
> same CLB matrix.
>
> Kevin Brace wrote:
>
> > That is not true.
> > According to Virtex datasheet dated 1/28/2000, the configuration bit
> > length for XCV100 is 781,216.
> > However, according to Spartan-II datasheet dated 3/3/2000, the
> > configuration bit length for XC2S100 is 781,248.
> >
> > Kevin Brace (Don't respond to me directly, respond within the
> > newsgroup.)
> >
> > Ray Andraka wrote:
> > >
> > > The bitstreams for virtex and spartanII for same size device are the same.
> > >
> > >
> > > --
> > > --Ray Andraka, P.E.
> > > President, the Andraka Consulting Group, Inc.
> > > 401/884-7930 Fax 401/884-7950
> > > email ray@andraka.com
> > > http://www.andraka.com
> > >
> > > "They that give up essential liberty to obtain a little
> > > temporary safety deserve neither liberty nor safety."
> > > -Benjamin Franklin, 1759
>
> --
> Marc Baker
> Xilinx Applications
> (408) 879-5375
--
--Ray Andraka, P.E.
President, the Andraka Consulting Group, Inc.
401/884-7930 Fax 401/884-7950
email ray@andraka.com
http://www.andraka.com
"They that give up essential liberty to obtain a little
temporary safety deserve neither liberty nor safety."
-Benjamin Franklin, 1759
Article: 39676"Paul Taylor" <p.taylor@ukonline.co.uk> schrieb im Newsbeitrag news:%v%a8.1557$Jp6.392877@monolith.news.easynet.net... > OK, but why not add a message "Not recommended for new designs" > when you run the fitter, instead of just not providing support? Hmm, this "messeage" is not on the Website/fitter software. But you FAE will tell you (if you got one). Or better read this newsgroup carefull ;-) > Akin to taking the datasheet off the web page? :-) > I understand, and like, the differences between -XL and -II, but I put > a lot of effort into making this experimentation PCB! Maybe next time you invest at least 20% of this work into a reseach about availability and future support? Just my 2 EURO-cent ;-) -- MfG FalkArticle: 39677
"rickman" <spamgoeshere4@yahoo.com> schrieb im Newsbeitrag news:3C6C8C3F.85941F7E@yahoo.com... > The only fly in the ointment is CCLK. As far as I can tell, it is > ignored when CS- is not asserted. I plan to connect CCLK to the WE- bus > signal. This will give me a single CCLK rising edge for each data word > (byte) while configuring. But once configuration is over, is it ok to > continue to toggle CCLK? I seem to remember that in some modes on other > Xilinx parts, CCLK should stop toggling once the part is fully AFAIK this is possible with Spartan-II and newer families. Only Spartan(XL) and older got messed up. -- MfG FalkArticle: 39678
Hello, I am having a fundamental clocking problem with sequential blocks within the webpack schematic capture environment. I distilled my design down to a single counter (CB4CE) that I want to clock from an external input pin that is not a dedicated CLK[0..n] pin. The rising edge of my external input should simply advance the counter. Under simulation (ModelSim) this works fine but when I download it to the part (XCR3064XL-10VQ44C) it only toggles bit0 of the counter and bit1-3 remain static. When I tie the dedicated CLK0 (~32KHz) to the counter clock input then it works as expected in terms of the counter output, i.e., bit0-3. This is the first time I've used the webpack tools and I'm not sure if I need to do something "special" in order to use external inputs to drive a rising edge clock input on a library component. Here is the basic wiring list for the "simple" counter circuit; -SERIAL_CLK (pin 43, B1) to rising edge of clock input of the CB4CE -CE on CB4CE is tied to VCC -CLR on CB4CE is tied to GND -Q0 on CB4CE is tied to an OBUF which drives pin 35 (A0) to which is attached an LED indicator -Q1 on CB4CE is tied to an OBUF which drives pin 34 (A1) to which is attached an LED indicator -Q2 on CB4CE is tied to an OBUF which drives pin 33 (A8) to which is attached an LED indicator -Q3 on CB4CE is tied to an OBUF which drives pin 31 (A10) to which is attached an LED indicator Recall that when I used the rising edge clock from the dedicated CLK0 input (pin 40) into the CB4CE counter it works correctly in the simulator and when it is running on the actual part. My conclusion thus far is that I cannot drive clock inputs on sequential library devices directly from a generic input without doing something special? I have tried running the external clock through a D-FLOP while clocking it from the dedicated CLK0 and using the Q output to drive the clock input on the CB4CE in the hope that the D-FLOP would somehow "qualify" my clock input, but alas that didn't make any difference. Thanks, RobertArticle: 39679
"Hristo Stevic" <hristostev@yahoo.com> schrieb im Newsbeitrag news:9bf3364d580063b1f1b4de5534d5e920.52609@mygate.mailgate.org... > hi > one my friends told me that if i use the output of an inv to feed its > input, A DANGER of *oscillation* could happen. is that right even for > LUT based on SRAM.what about a simple buffer. Yes it is. This will for a ring oscillator. Runs at 360 MHz in a Spartan-II-5 ;-)) > say also i have a 3 ports "and", one of its inputs will be the output of > that port, is there any risk of oscillation? Depends on the logic function. But in general, you should nod create combinatorical feedbacks. This is no clean synchronus design and will mess up the simulator, and, even more, has VERY good chances to mess up your design. (YES, there are some Asynchronous GURUs around who know how to deal with such problems, but a beginner isnt one of these) -- MfG FalkArticle: 39680
> I have no experience using FPGA. I have to choose some family, from > Altera or Xilinx. I suppose both should have a family that suits my > needs, but I need some advice considering what I have to do: > > - I have to do a PCB w/FPGA logic. Main requirement is to include > in-system reconfiguration, I mean, to change code loaded in FPGA > without desoldering the device. I have learned that a configuration > PROM is in charge of this, or even a JTAG interface. Is it correct? Do > I need a CPU to control FPGA as well? > Hi Dani, You can check out the Atmel AT17 family of In System Programmable Configurators. Atmel has an interesting chip, the FPSLIC which combines a processor and a 5k/10k/40k gate FPGA There will in a couple of months be a JTAG version, and hopefully it should be possible to download the FPGA AND CPU over JTAG using the standard AVR controller JTAG-ICE. > - I have worked with Texas' DSPs boards before. In that, I load > programs and debug the application with JTAG interface. I understand > Virtex devices have the same interface. Is software provided by these > people similar in this way to DSP's software? Is it possible to write > a program and inmediately load it in FPGA? > It is a little bit more involved. Typically you write in the VHDL or Verilog language. Then you *simulate*. After you think it works, you do synthesize , then you do place and route which can take some time. After place and route, you simulate again, since the synthesis process and P&R may have introduced speed problems or other problems. Only after the postlayut simulation , you download to your board. > - Which family should be best choice considering I have to design a > PCB w/reconfiguration capability? You can use any Family as long as the configurator is in reprogrammable memory. > - I'm thinking in buying a demo board to achieve experience w/FPGA > programming, which one is convenient, considering I have to implement > a PCB ? Is it a good choice to think in a demo board or it's better to > study and design the PCB right now? You need to get the datasheet for the configurator. I.E: http://www.atmel.com/atmel/products/prod22.htm will provie you info on AT17 > Thanks in advance. > > -Dani- -- Best Regards Ulf at atmel dot com These comments are intended to be my own opinion and they may, or may not be shared by my employer, Atmel Sweden.Article: 39681
"Paul Taylor" <p.taylor@ukonline.co.uk> writes: > OK, but why not add a message "Not recommended for new designs" > when you run the fitter, instead of just not providing support? Because support costs money.Article: 39682
All,
I am getting the following message on my place and route.
WARNING:DesignRules:372 - Netcheck: Gated clock. Clock net
fsync1/CPUINTERFACE_0/loop13_un187_cpu_addr is sourced by a combinatorial
pin. This is not good design practice. Use the CE pin to control the loading
of data into the flip-flop.
I believe its due to this code:
---
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.STD_LOGIC_UNSIGNED.all;
use IEEE.STD_LOGIC_ARITH.all;
use WORK.PIFSTYPES.all;
entity CPUWRTGEN is
port
(CPU_ADDR :in BIT11;
WRT :out BIT31);
end CPUWRTGEN;
architecture BEHAVIOR of CPUWRTGEN is
signal CPU_ADDR_INT : INT63;
begin
CPU_ADDR_INT <= conv_integer(CPU_ADDR(5 downto 0));
process(CPU_ADDR, CPU_ADDR_INT)
begin
for I in 39 downto 9 loop
if CPU_ADDR (10 downto 6) = "01000" and CPU_ADDR_INT = I then
WRT(I-9) <= '0';
else
WRT(I-9) <= '1';
end if;
end loop;
end process;
end BEHAVIOR;
--------
I also get a complaints in Synplify when synthesizing, like so:
Found clock fsync1.CPUINTERFACE_0.CPUWRTGEN_0.loop37_un19_cpu_addr_inferred_clock with period 1000ns
Now my question is how can I change my code so that I can eliminate these warnings, as its not a good design practice.
Salman
--
Salman Sheikh
NASA/GSFC Code 564
Greenbelt, MD 20771
301-286-3763 301-286-0220 (fax)
Article: 39683Hi! > -- You can/want do a workaround for the power-on surge of Spartan-II I am going to build an USB device with a Spartan-II or Spartan-IIe FPGA. Could you please describe this power-on surge or tell me, where I can find more details on that? Thanks HansiArticle: 39684
Jon Schneider wrote: > Bret Wade wrote: > > > > As David said, the synthesis tools has put IOB=TRUE constraints on the > > registers which directs Map to pack them into IOB components. > > But why has it done that ? > > Jon I assume we're taking about XST? I have no insight into why the IOB properties are being applied inappropriately. My guess would be that you've either inadvertently specified them or the synthesis tool has a bug. In either case, you can turn this off by setting the "Pack I/O Registers into IOBs" synthesis option to off (Proccess--> Properties-->Xilinx Specific Options). This will result in XST passing no IOB properties. You can then rely on the Map IOB register packing feature (-pr) instead to pack the appropriate registers into IOBs. These two IOB register packing feature work independently of each other, except that when both are used, the IOB property takes precedence. BretArticle: 39685
Consult, http://www.support.xilinx.com/xapp/xapp451.pdf and http://www.support.xilinx.com/xapp/xapp450.pdf And we refer to it as the "power On requirement, as needing less than 500 mA at 0C is not really a surge is it? I suppose everything is relative. Austin Johann Glaser wrote: > Hi! > > > -- You can/want do a workaround for the power-on surge of Spartan-II > > I am going to build an USB device with a Spartan-II or Spartan-IIe FPGA. > Could you please describe this power-on surge or tell me, where I can find > more details on that? > > Thanks > HansiArticle: 39686
Endlessly discussed in this group. Search old postings on Google. USB is tough. Johann Glaser wrote > Hi! > > > -- You can/want do a workaround for the power-on surge of Spartan-II > > I am going to build an USB device with a Spartan-II or Spartan-IIe FPGA. > Could you please describe this power-on surge or tell me, where I can find > more details on that? > > Thanks > HansiArticle: 39687
Tim wrote: > Endlessly discussed in this group. Search old postings on Google. > USB is tough. > > Johann Glaser wrote > There's also a Xilinx apps note describing some power supply fixes you can use to get around the surge if you don't have 0.5A (commercial) or 2A (industrial) available from your PSU.Article: 39688
Ray Andraka <ray@andraka.com> writes: >Connecting the output of an inverter back to the input results in an >oscillator no matter what the technology. Think about hwat happens. Say it >starts up with '0' at its output. That '0' value will go into the input, be >inverted making the output drive a '1'. The '1' then causes the output to >drive a zero and the cycle repeats. This is known as a ring oscillator. It >will oscillate at a frequency determined by the delay through the inverter >and the feed back path. It oscillates because there is no stable state. Well, it could just go to Vcc/2. When I used to make oscillators out of CMOS I used three inverters. If you connect a standard cell CMOS inverter output directly to the input it might not oscillate. In an FPGA the feedback path is much longer, and I would be pretty sure it would. It depends on other properties of the feedback path. In either case the current draw could be high. -- glenArticle: 39689
Thanks Philip.. I have got the same suggestion from Bryan to set the level as "orca" in the powerview's netlist writer.. Its working perfectly !! Philip Freidin <philip@fliptronics.com> wrote in message news:<1fmp6u0tpfijnpk71dd27h41r407c21ljr@4ax.com>... > Although I have never used the Orca stuff, it looks like you are using > a schematic flow, with viewlogic tools (Powerview). > > My guess is that you are using a schematic to edif netlist writer, > and you failed to set the "Level" attribute. The clue is that among > the primitives that it is complaining about, is "UDFDL" which I am > fairly sure is a Viewsim simulation primitive. This should not > be in an implementation netlist. > > In the "schematic edif netlist writer" window, look for a level > attribute, and set it to something like ATT/ORCA/Lucent/Agere/HP > > Philip Freidin > >Article: 39690
> Maybe next time you invest at least 20% of this work into a reseach about > availability and future support? When I bought the devices 18 months ago, Spartan-II was either on long lead time, or was difficult to obtain, so I was advised the -XL at the time. I only currently want to use it for educational reasons anyway, and have ordered a full BurchED XC2S200 value pack as well, so at the end of the day it doesn't really matter if I can't use VHDL with the XCS30XL, just seems a waste for me not to try! (Also I can use it NOW, before the XC2S200 arrives!!!)Article: 39691
True enough. It depends on the parasitics in relation to the loop delay. If the
loop delay is short enough, the parasitics can essentially act as a filter which
will keep it from oscillating. In FPGA's the loop delay is fairly long, the
drive strength is high (the amplification provided by the cell is high) so that
it will be a ring oscillator in an FPGA. In fact, ring oscillators like this
have been used to measure device performance. They can also be used to measure
die temperature indirectly, since the propagation delay, and therefore the
oscillation frequency are temperature dependent.
glen herrmannsfeldt wrote:
>
> Well, it could just go to Vcc/2. When I used to make oscillators
> out of CMOS I used three inverters. If you connect a standard cell
> CMOS inverter output directly to the input it might not oscillate.
> In an FPGA the feedback path is much longer, and I would be pretty
> sure it would.
>
> It depends on other properties of the feedback path.
> In either case the current draw could be high.
>
> -- glen
--
--Ray Andraka, P.E.
President, the Andraka Consulting Group, Inc.
401/884-7930 Fax 401/884-7950
email ray@andraka.com
http://www.andraka.com
"They that give up essential liberty to obtain a little
temporary safety deserve neither liberty nor safety."
-Benjamin Franklin, 1759
Article: 39692Ulf Samuelsson <ulf@atmel.REMOVE.com> wrote in message news:t%db8.10136$O5.23321@nntpserver.swip.net... > > I have no experience using FPGA. I have to choose some family, from > > Altera or Xilinx. I suppose both should have a family that suits my > > needs, but I need some advice considering what I have to do: > > > > - I have to do a PCB w/FPGA logic. Main requirement is to include > > in-system reconfiguration, I mean, to change code loaded in FPGA > > without desoldering the device. I have learned that a configuration > > PROM is in charge of this, or even a JTAG interface. Is it correct? Do > > I need a CPU to control FPGA as well? > > > Hi Dani, You can check out the Atmel AT17 family of In System Programmable > Configurators. > Atmel has an interesting chip, the FPSLIC which combines a processor and > a 5k/10k/40k gate FPGA > There will in a couple of months be a JTAG version, and hopefully it > should be possible to download the FPGA AND CPU over JTAG using the standard > AVR controller JTAG-ICE. > > > - I have worked with Texas' DSPs boards before. In that, I load > > programs and debug the application with JTAG interface. I understand > > Virtex devices have the same interface. Is software provided by these > > people similar in this way to DSP's software? Is it possible to write > > a program and inmediately load it in FPGA? > > > It is a little bit more involved. > Typically you write in the VHDL or Verilog language. > Then you *simulate*. > After you think it works, you do synthesize , then you do place and route > which can take some time. > After place and route, you simulate again, since the synthesis process and > P&R > may have introduced speed problems or other problems. > Only after the postlayut simulation , you download to your board. when I use verilog for the entry design, do I need to write the tester code respectively for pre-simulation and postlayout simulation? That means two different test codes? thanks. > > > - Which family should be best choice considering I have to design a > > PCB w/reconfiguration capability? > > You can use any Family as long as the configurator is in reprogrammable > memory. > > > - I'm thinking in buying a demo board to achieve experience w/FPGA > > programming, which one is convenient, considering I have to implement > > a PCB ? Is it a good choice to think in a demo board or it's better to > > study and design the PCB right now? > > You need to get the datasheet for the configurator. > I.E: http://www.atmel.com/atmel/products/prod22.htm will provie you info > on AT17 > > > > Thanks in advance. > > > > -Dani- > > -- > Best Regards > Ulf at atmel dot com > These comments are intended to be my own opinion and they > may, or may not be shared by my employer, Atmel Sweden. > > >Article: 39693
rickman <spamgoeshere4@yahoo.com> wrote in message news:3C6D5519.BD2F7E28@yahoo.com... > Dani Guzman wrote: > > > > Hi, > > I have no experience using FPGA. I have to choose some family, from > > Altera or Xilinx. I suppose both should have a family that suits my > > needs, but I need some advice considering what I have to do: > > > > - I have to do a PCB w/FPGA logic. Main requirement is to include > > in-system reconfiguration, I mean, to change code loaded in FPGA > > without desoldering the device. I have learned that a configuration > > PROM is in charge of this, or even a JTAG interface. Is it correct? Do > > I need a CPU to control FPGA as well? > > First, let me say that in terms of configuration, there is very little > real difference between the two vendors you mention. You can use a > (EE)PROM to configure the FPGA or you can use a micro. But JTAG is not a > viable option for normal operation of your board. JTAG is used during > debug to save the trouble of downloading designs to the (EE)PROM or to > what ever storage your micro is using. Did you mean that Xilinx's FPGA need a PROM for reconfiguration, while Atera's dont need, it is directly download in the FPGA? how about Actel's? thanks > > One question you need to answer is when/how do you plan to do the > updates? Will your board be connected to a PC which can download the > updates? Do you want to plug in a small memory module to update the > download? Will there be a remote comms connection of some kind? This is > the first question you need to answer. > > > > - I have worked with Texas' DSPs boards before. In that, I load > > programs and debug the application with JTAG interface. I understand > > Virtex devices have the same interface. Is software provided by these > > people similar in this way to DSP's software? Is it possible to write > > a program and inmediately load it in FPGA? > > Yes, JTAG works about the same with an FPGA as it does with the DSP. I > have not used JTAG to download FPGAs before, but the process is not > complex. The development software has an option of preparing a JTAG > format output file. I believe the vendors offer a PC compatible cable to > connect to your target board. > > > > - Which family should be best choice considering I have to design a > > PCB w/reconfiguration capability? > > I don't think you will find much difference between the different > vendors or families. I do know that you could use a standard EPROM with > the older Xilinx parts, but is not supported with the newer parts. But > that was a bit of a kludge requiring a large number of address lines in > addition to the data bus. > > > > - I'm thinking in buying a demo board to achieve experience w/FPGA > > programming, which one is convenient, considering I have to implement > > a PCB ? Is it a good choice to think in a demo board or it's better to > > study and design the PCB right now? > > I can't recommend a demo board vendor. But there are many out there. If > you really want to use the JTAG method, find one that works with JTAG. I > recommend that you skip the demo board and use the bit serial slave mode > or the byte wide parallel slave mode on your own board. I find these two > to be the easiest configuration modes when used with a micro processor. > > -- > > Rick "rickman" Collins > > rick.collins@XYarius.com > Ignore the reply address. To email me use the above address with the XY > removed. > > Arius - A Signal Processing Solutions Company > Specializing in DSP and FPGA design URL http://www.arius.com > 4 King Ave 301-682-7772 Voice > Frederick, MD 21701-3110 301-682-7666 FAXArticle: 39694
Kevin Brace <ihatespamkevinbraceusenet@ihatespamhotmail.com> wrote: > Perhaps if you leave the computer running for an hour or so, you should > start seeing something on a Wave window. > I simulated a design that occupied about 60% of XC2S150, at 33MHz for > 10us. > That took about 4 hours to finish, but I must say that's far better than > paying several thousands of dollars for a full version of ModelSim Depends how often you do it. For comparison's sake, just last week I ran a simulation of a 50%-full V2000E, running at 160 MHz, for 100us, and it completed in 1-2 hours (I don't remember exactly). That was with PE. Hamish -- Hamish Moffatt VK3SB <hamish@debian.org> <hamish@cloud.net.au>Article: 39695
Rick Filipkiewicz <rick@algor.co.uk> wrote: > Is it possible to use 4.1i speed files when building with 3.3i ? e.g. for an > XCV600E I could just copy over the %XILINX%/virtexe/data/v600e.spd from my 4.1i > installation to my 3.3i one ? No, you'll get error messages about the file format version numbers being different. (I tried it.) Hamish -- Hamish Moffatt VK3SB <hamish@debian.org> <hamish@cloud.net.au>Article: 39696
Both Altera and Xilinx need external storage for the configuration. This can
be a serial PROM (typical for stand-alone systems), a standard byte wide PROM
with something to load the FPGA, or a microprocessor with the FPGA image
stored in it's memory.
FPGA/IC wrote:
> rickman <spamgoeshere4@yahoo.com> wrote in message
> news:3C6D5519.BD2F7E28@yahoo.com...
> > Dani Guzman wrote:
> > >
> > > Hi,
> > > I have no experience using FPGA. I have to choose some family, from
> > > Altera or Xilinx. I suppose both should have a family that suits my
> > > needs, but I need some advice considering what I have to do:
> > >
> > > - I have to do a PCB w/FPGA logic. Main requirement is to include
> > > in-system reconfiguration, I mean, to change code loaded in FPGA
> > > without desoldering the device. I have learned that a configuration
> > > PROM is in charge of this, or even a JTAG interface. Is it correct? Do
> > > I need a CPU to control FPGA as well?
> >
> > First, let me say that in terms of configuration, there is very little
> > real difference between the two vendors you mention. You can use a
> > (EE)PROM to configure the FPGA or you can use a micro. But JTAG is not a
> > viable option for normal operation of your board. JTAG is used during
> > debug to save the trouble of downloading designs to the (EE)PROM or to
> > what ever storage your micro is using.
>
> Did you mean that Xilinx's FPGA need a PROM for reconfiguration, while
> Atera's dont need, it is directly download in the FPGA? how about Actel's?
>
> thanks
>
> >
> > One question you need to answer is when/how do you plan to do the
> > updates? Will your board be connected to a PC which can download the
> > updates? Do you want to plug in a small memory module to update the
> > download? Will there be a remote comms connection of some kind? This is
> > the first question you need to answer.
> >
> >
> > > - I have worked with Texas' DSPs boards before. In that, I load
> > > programs and debug the application with JTAG interface. I understand
> > > Virtex devices have the same interface. Is software provided by these
> > > people similar in this way to DSP's software? Is it possible to write
> > > a program and inmediately load it in FPGA?
> >
> > Yes, JTAG works about the same with an FPGA as it does with the DSP. I
> > have not used JTAG to download FPGAs before, but the process is not
> > complex. The development software has an option of preparing a JTAG
> > format output file. I believe the vendors offer a PC compatible cable to
> > connect to your target board.
> >
> >
> > > - Which family should be best choice considering I have to design a
> > > PCB w/reconfiguration capability?
> >
> > I don't think you will find much difference between the different
> > vendors or families. I do know that you could use a standard EPROM with
> > the older Xilinx parts, but is not supported with the newer parts. But
> > that was a bit of a kludge requiring a large number of address lines in
> > addition to the data bus.
> >
> >
> > > - I'm thinking in buying a demo board to achieve experience w/FPGA
> > > programming, which one is convenient, considering I have to implement
> > > a PCB ? Is it a good choice to think in a demo board or it's better to
> > > study and design the PCB right now?
> >
> > I can't recommend a demo board vendor. But there are many out there. If
> > you really want to use the JTAG method, find one that works with JTAG. I
> > recommend that you skip the demo board and use the bit serial slave mode
> > or the byte wide parallel slave mode on your own board. I find these two
> > to be the easiest configuration modes when used with a micro processor.
> >
> > --
> >
> > Rick "rickman" Collins
> >
> > rick.collins@XYarius.com
> > Ignore the reply address. To email me use the above address with the XY
> > removed.
> >
> > Arius - A Signal Processing Solutions Company
> > Specializing in DSP and FPGA design URL http://www.arius.com
> > 4 King Ave 301-682-7772 Voice
> > Frederick, MD 21701-3110 301-682-7666 FAX
--
--Ray Andraka, P.E.
President, the Andraka Consulting Group, Inc.
401/884-7930 Fax 401/884-7950
email ray@andraka.com
http://www.andraka.com
"They that give up essential liberty to obtain a little
temporary safety deserve neither liberty nor safety."
-Benjamin Franklin, 1759
Article: 39697My guess is that you are driving the enable pin with combinational logic. The inputs propagating through the logic cause this. Good luck "Niv" <niv@ntlworld.com> wrote in message news:Ij2b8.70986$H37.9343784@news2-win.server.ntlworld.com... > Hi, > I'm doing a post PAR sim on a Virtex XCV300. We have an output enable pin > which enables a tristate bus. > > When it's enabled, sometimes the bus goes from all 'Z's to the output value, > but transitions thru' a bunch of 'X's for maybe a couple of nanosecs. > > There is no bus contention apparently (using Modelsim & "check contention > add <signame>). > > Is this to be expected? It seems that as the relevent output is enabled, it > turns on in a strange way! > > tia, niv. > >Article: 39698
You need the addition of a clock signal that is synchronous with
the CPU writing to WRT(...). Make your sensitivity list consist of
the clock and your reset signal.
process(CPU_CLK, RESET_N)
begin
if (reset_n /= '1') then
WRT <= (others => <reset value>);
elsif (CPU_CLK'event and CPU_CLK = <1=rising edge>,<0=falling edge>)
then
for I in 39 downto 9 loop
if CPU_ADDR (10 downto 6) = "01000" and CPU_ADDR_INT = I then
WRT(I-9) <= '0';
else
WRT(I-9) <= '1';
end if;
end loop;
end if; -- elsif
end process;
Good luck.
"Salman Sheikh" <sheikh@pop500.gsfc.nasa.gov> wrote in message
news:ee74dea.0@WebX.sUN8CHnE...
> All,
>
> I am getting the following message on my place and route.
>
> WARNING:DesignRules:372 - Netcheck: Gated clock. Clock net
> fsync1/CPUINTERFACE_0/loop13_un187_cpu_addr is sourced by a
combinatorial
> pin. This is not good design practice. Use the CE pin to control the
loading
> of data into the flip-flop.
>
> I believe its due to this code:
> ---
> library IEEE;
> use IEEE.STD_LOGIC_1164.all;
> use IEEE.STD_LOGIC_UNSIGNED.all;
> use IEEE.STD_LOGIC_ARITH.all;
> use WORK.PIFSTYPES.all;
>
> entity CPUWRTGEN is
> port
> (CPU_ADDR :in BIT11;
> WRT :out BIT31);
> end CPUWRTGEN;
>
> architecture BEHAVIOR of CPUWRTGEN is
>
> signal CPU_ADDR_INT : INT63;
>
> begin
>
> CPU_ADDR_INT <= conv_integer(CPU_ADDR(5 downto 0));
>
> process(CPU_ADDR, CPU_ADDR_INT)
> begin
> for I in 39 downto 9 loop
> if CPU_ADDR (10 downto 6) = "01000" and CPU_ADDR_INT = I then
> WRT(I-9) <= '0';
> else
> WRT(I-9) <= '1';
> end if;
> end loop;
> end process;
>
> end BEHAVIOR;
> --------
> I also get a complaints in Synplify when synthesizing, like so:
>
> Found clock
fsync1.CPUINTERFACE_0.CPUWRTGEN_0.loop37_un19_cpu_addr_inferred_clock with
period 1000ns
>
> Now my question is how can I change my code so that I can eliminate these
warnings, as its not a good design practice.
>
> Salman
>
> --
> Salman Sheikh
> NASA/GSFC Code 564
> Greenbelt, MD 20771
> 301-286-3763 301-286-0220 (fax)
Article: 39699"Paul Taylor" <p.taylor@ukonline.co.uk> schrieb im Newsbeitrag news:pqhb8.3948$Jp6.691987@monolith.news.easynet.net... > > Maybe next time you invest at least 20% of this work into a reseach about > > availability and future support? > > When I bought the devices 18 months ago, Spartan-II was either on long > lead time, or was difficult to obtain, so I was advised the -XL at the time. Hmm, OK this is another story. -- MfG Falk
Site Home Archive Home FAQ Home How to search the Archive How to Navigate the Archive
Compare FPGA features and resources
Threads starting:
Authors:A B C D E F G H I J K L M N O P Q R S T U V W X Y Z