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There are actually non-volatile FPGA's made by Actel and Quicklogic, fuse, anti-fuse, and flash. Regards "Ulf Samuelsson" <ulf@atmel.REMOVE.com> wrote in message news:<A%0d8.11031$O5.25276@nntpserver.swip.net>... > These comments are intended to be my own opinion and they > may, or may not be shared by my employer, Atmel Sweden. > > "X. Q." <qijun@okigrp.com.sg> skrev i meddelandet > news:3c746c0c@news.starhub.net.sg... > > I built my design with Spartan-II. Now the research centre in another > > country > > needs my design. Let's pressume they don't have any expertise in FPGA and > > such, while they want my design. How can I transport my design to them? My > > design is 10K gates in ASIC. Can I get any CPLD which can hold this > design? > > I understand FPGA dies after I unplug the power. > > > > Best Regards > > XQ. > > > > > > Why not send them an FPGA + a Preprogrammed Configurator? > - An Atmel AT17 is always appreciated :-)Article: 39876
basic question, could we tell that IIR performs a convolution operation as FIR does thanks -- Posted via Mailgate.ORG Server - http://www.Mailgate.ORGArticle: 39877
"Dave Brown" <dbrown12@shaw.ca> wrote in message
news:a539he$9b4$1@pallas.novatel.ca...
> I have a project written in VHDL that I'm trying to synthesize using XST
and
> ISE 4. Part of the project uses a dual port ram block that was created
using
> CoreGen. When I try and place and route the design, I get errors that say
> the dual port ram block is unexpanded. I have included the .xco file for
the
> ram block inb the project files, what more do I need to do to get place
and
> route to work? The component that uses the RAM has the correct component
> declartions from the CoreGen generated template file. Any help would be
> great.
> Thanks,
> Dave
>
>
>
Dave,
A little more info...
Using ISE4.1 this is what I do.
First create a project using ISE4.1
Then create a project using coregen in the same subdirectory as the ISE4.1
subdirectory
now create your core. it will automatically show up in the ISE4.1 project
Now jsu instantiate is normally.
Here is the wrapper file I used to test my dual port ram.
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
-- synopsys translate_off
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
-- synopsys translate_on
entity dualportwrapper is
Port ( wr_clk : in std_logic;
rd_clk : in std_logic;
wr_addr : in std_logic_vector(4 downto 0);
rd_addr : in std_logic_vector(4 downto 0);
wr_data : in std_logic_vector(16 downto 0);
rd_data : out std_logic_vector(16 downto 0);
wr_ena : in std_logic);
end dualportwrapper;
architecture Behavioral of dualportwrapper is
component dualportram
port (
addra: IN std_logic_VECTOR(4 downto 0);
addrb: IN std_logic_VECTOR(4 downto 0);
clka: IN std_logic;
clkb: IN std_logic;
dina: IN std_logic_VECTOR(16 downto 0);
doutb: OUT std_logic_VECTOR(16 downto 0);
wea: IN std_logic);
end component;
-- XST black box declaration
attribute box_type : string;
attribute box_type of dualportram: component is "black_box";
begin
your_instance_name : dualportram
port map (
addra => wr_addr,
addrb => rd_addr,
clka => wr_clk,
clkb => rd_clk,
dina => wr_data,
doutb => rd_data,
wea => wr_ena);
end Behavioral;
--here is the test bench I used
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
ENTITY testbench IS
END testbench;
ARCHITECTURE behavior OF testbench IS
COMPONENT dualportwrapper
PORT(
wr_clk : IN std_logic;
rd_clk : IN std_logic;
wr_addr : IN std_logic_vector(4 downto 0);
rd_addr : IN std_logic_vector(4 downto 0);
wr_data : IN std_logic_vector(16 downto 0);
wr_ena : IN std_logic;
rd_data : OUT std_logic_vector(16 downto 0)
);
END COMPONENT;
SIGNAL wr_clk : std_logic;
SIGNAL rd_clk : std_logic;
SIGNAL wr_addr : std_logic_vector(4 downto 0);
SIGNAL rd_addr : std_logic_vector(4 downto 0);
SIGNAL wr_data : std_logic_vector(16 downto 0);
SIGNAL rd_data : std_logic_vector(16 downto 0);
SIGNAL wr_ena : std_logic;
BEGIN
uut: dualportwrapper PORT MAP(
wr_clk => wr_clk,
rd_clk => rd_clk,
wr_addr => wr_addr,
rd_addr => rd_addr,
wr_data => wr_data,
rd_data => rd_data,
wr_ena => wr_ena
);
process
begin
wr_clk<='0', '1' after 50 ns;
wait for 100 ns;
end process;
process
begin
wr_addr<="00000";
wr_ena<='0';
wait for 5 us;
for I in 1 to 32 loop
wr_addr<=std_logic_vector(TO_UNSIGNED(I-1, wr_addr'Length));
wr_ena<='1';
wait for 100 ns;
end loop;
wr_ena<='0';
wait for 1.8 us;
end process;
process
begin
wr_data<=std_logic_vector(TO_UNSIGNED(0, wr_data'Length));
wait for 5 us;
for I in 1 to 32 loop
wr_data<=std_logic_vector(TO_UNSIGNED(I, wr_data'Length));
wait for 100 ns;
end loop;
wait for 1.8 us;
end process;
process
begin
for I in 1 to 32 loop
rd_clk<='0', '1' after 100 ns;
wait for 200 ns;
end loop;
wait for 3.6 us;
end process;
process
begin
for I in 1 to 32 loop
rd_addr<=std_logic_vector(TO_UNSIGNED(I-1, wr_addr'Length));
wait for 200 ns;
end loop;
wait for 3.6 us;
end process;
END;
-- to simulate this at the behavioral level you will need to compile the
coregen part within Modelsim
Article: 39878Currently, IEEE 1076.3 (ieee.numeric_std package) is up for revision http://www.vhdl.org/vhdlsynth/ One of the things that came up is that it would be nice to add a synthesizable floating point (and possibly fixed point) package. Does anybody have one of these packages that we could use and modify? At this point we can add things like this to the standard. If anybody else has ideas, please sign up on the e-mail reflector on the vhdlsynth page. -- NAME: David W. Bishop INTERNET: dbishop@vhdl.org ( \ ) US MAIL: Hilton NY A Long time ago, \__\/ PHYSICAL: 43:17:17N 77:47:37W 281' In a Galaxy far, far away... | | For Supernova info: http://www.RochesterAstronomy.org/snimages/ | | For VHDL/Synthesis info: http://www.vhdl.org/siwg _/___\_ All standard disclaimers apply. [_______]Article: 39879
Don't use it in a production setting if you exceeded the absolute maximum
ratings listed in the DC specifications part of the data sheet. You may have
stressed it enough that it may fail after a short time in service, or may not
meet all the timing even though it may still work correctly.
Eric Smith wrote:
> "X. Q." <qijun@okigrp.com.sg> writes:
> > Last time I purchased a XC9572 CPLD and an SC2S100 Spartan-II chip.
> > I applied a 5V to it's VCCO. I want to know how to decide whether the chip
> > has been spoiled.
>
> Try using it correctly. If it works, it isn't *completely* broken.
--
--Ray Andraka, P.E.
President, the Andraka Consulting Group, Inc.
401/884-7930 Fax 401/884-7950
email ray@andraka.com
http://www.andraka.com
"They that give up essential liberty to obtain a little
temporary safety deserve neither liberty nor safety."
-Benjamin Franklin, 1759
Article: 39880
We've seen similar problems on occasion, it is certainly not unique to Dell machines, and not all Dell machines do it. In our experience it has been due to a glitch on the program line. To work around it, we have been leaving the program wire on
the cable unconnected and manually pulsing the program input to the board.
Neil wrote:
> I've had problems with Dell parallel ports with other devices. The fix for me has been to use an old parallel port zip drive to buffer the signal! I'm not sure this will help in this case, but if you can find an old zip drive, it's worth a try!
--
--Ray Andraka, P.E.
President, the Andraka Consulting Group, Inc.
401/884-7930 Fax 401/884-7950
email ray@andraka.com
http://www.andraka.com
"They that give up essential liberty to obtain a little
temporary safety deserve neither liberty nor safety."
-Benjamin Franklin, 1759
Article: 39881
Wrong library. The coregen components are in the xilinxcorelib library. You
only need the library declaration for simulation however. As long as the edif
netlist can be found by ngdbuild, you should be OK. Make sure it is either in
the same directory as your top level edif, or that you set the macro search
path to point to the directory it is in.
Theron Hicks wrote:
> "Dave Brown" <dbrown12@shaw.ca> wrote in message
> news:a539he$9b4$1@pallas.novatel.ca...
> > I have a project written in VHDL that I'm trying to synthesize using XST
> and
> > ISE 4. Part of the project uses a dual port ram block that was created
> using
> > CoreGen. When I try and place and route the design, I get errors that say
> > the dual port ram block is unexpanded. I have included the .xco file for
> the
> > ram block inb the project files, what more do I need to do to get place
> and
> > route to work? The component that uses the RAM has the correct component
> > declartions from the CoreGen generated template file. Any help would be
> > great.
> > Thanks,
> > Dave
> >
> >
> >
>
> Dave,
> Did you include the library?
>
> -- synopsys translate_off
> library UNISIM;
> use UNISIM.VCOMPONENTS.ALL;
> -- synopsys translate_on
>
> Theron
--
--Ray Andraka, P.E.
President, the Andraka Consulting Group, Inc.
401/884-7930 Fax 401/884-7950
email ray@andraka.com
http://www.andraka.com
"They that give up essential liberty to obtain a little
temporary safety deserve neither liberty nor safety."
-Benjamin Franklin, 1759
Article: 39882
AFAIK, the webpack version of IMPACT only supports JTAG downloads.
Falk Brunner wrote:
> "Ray Andraka" <ray@andraka.com> schrieb im Newsbeitrag
> news:3C750BE8.DE42CE4C@andraka.com...
> > They replaced it with something called "iMPACT". I haven't used it yet,
> so I
> > can't tell you how good/bad it is. It does still require you to do a full
> > xilinx install to be able to download devices :-(
>
> If you want to use only the commercial version, then YES.
> But there is also the WEBPACK version of IMPACT, which is AFAIK identical to
> the commercial version.
> So you jst need to install IMPACT (WEBPACK)
>
> --
> MfG
> Falk
--
--Ray Andraka, P.E.
President, the Andraka Consulting Group, Inc.
401/884-7930 Fax 401/884-7950
email ray@andraka.com
http://www.andraka.com
"They that give up essential liberty to obtain a little
temporary safety deserve neither liberty nor safety."
-Benjamin Franklin, 1759
Article: 39883Hello, I'm not sure how to classify this problem so here's my best explaination. I'm using a Xilinx part, and in order to use LVDS, LVPECL, or 5V outputs, I need to specify the IOBUFs manually. Xilinx does not have an IOBUF that takes inout data from the internal FPGA, so I'm required to breakout the internal tristate buffers into an input, output, and tristate signals. This is turning my code into a real mess. Has anyone run into this problem and found an elegant solution? Thanks Jason s_p_a_m_lapenta_jm@yahoo.com_spamArticle: 39884
Hi! I bought an evaluation board with a Xilinx Spartan XCS10 FPGA on it to learn how to program FPGAs some months ago. (http://www.digilent.cc/) Two weeks ago I had time to work a little with it. After working half a night to geht a ready "compiled" .bit file into the FPGA (I had to write my own Linux downloading program) the board worked with the provided demo program. But now I want to write my own FPGA "programs" to learn that. My problem is that I have no software to translate an EDIF file to a .bit file for the XCS10 FPGA. Xilinx WebPack offers this feature for SpartanII and SpartanIIe FPGAs, but not for my FPGA. Is it allowed (and possible) to copy simply the few files from a Xilinx Foundation or Alliance? Or is it allowed to use a slightly old version of these programs when the one who bought them already uses a newer version? If all this is not allowed: Could Xilinx please release the bitgen, par, map, ... executables which are necessary for my task to be downloaded? Without the huge graphical frontends, ... And with the same kind of support (only the website) as for the WebPack. Another (optional) topic: The command line tools I have talked about now seem to be developed under some kind of Unix environment. At least at the beginning. Would it be a big problem to provide them for Linux? Without sources, only the executables. That would make the life faaaar easier for many Linux users, because they don't have to install Wine. Bye HansiArticle: 39885
Johann Glaser wrote > Another (optional) topic: The command line tools I have talked about now > seem to be developed under some kind of Unix environment. At least at the > beginning. Would it be a big problem to provide them for Linux? Without > sources, only the executables. That would make the life faaaar easier for > many Linux users, because they don't have to install Wine. Linux support seems to be leaking out. See the X web page.Article: 39886
NGDBUILD should recognise the KCPSM "black box" in your higer level EDIF and pull in the kcpsm.edn file. "Theron Hicks" <hicksthe@egr.msu.edu> wrote in message news:a53a04$8iu$1@msunews.cl.msu.edu... > I am trying to use the KCPSM microcontroller in a VHDL design in ISE 4.1. > 4.1 does not appear to recognize the EDIF file in a VHDL project. (ISE3.3 > does seem to work OK.) > > I get the following messages... > > EDIF source are not supported for the selected device and flow. Import file > kcpsm.EDN? > > This design contains sources that are not supported by the current device > and flow. You may view these sources, but not process them. These are : > kcpsm.EDN > > Am I missing something obvious?Article: 39887
"Falk Brunner" wrote > "Kumar" <yatiks@yahoo.com> schrieb im Newsbeitrag > news:b479edf8.0202202254.58dbda7e@posting.google.com... > > > Then I connected the same Board to other PC with less speed( config > > --366 Mhz Celeron ) I have not faced any problem in programming the > > FPGA ( XC2s200-5PQ208 ) through JTAG with same cable (length = appr 5 > > feet). > > > > Can anybody tell what is causing the problem (is the speed of the PC > > or something else) and also how can I solve this problem ???????? > > Looks like a driver problem. Or inadequate signal levels from the PC?Article: 39888
"Theron Hicks" <hicksthe@egr.msu.edu> schrieb im Newsbeitrag news:a53a04$8iu$1@msunews.cl.msu.edu... > I am trying to use the KCPSM microcontroller in a VHDL design in ISE 4.1. I did this too a while ago, it worked fine. I used ISE 4.1 (Service Pack3), XST VHDL flow, and a XC2S100 > 4.1 does not appear to recognize the EDIF file in a VHDL project. (ISE3.3 > does seem to work OK.) > > I get the following messages... > > EDIF source are not supported for the selected device and flow. Import file > kcpsm.EDN? > > This design contains sources that are not supported by the current device > and flow. You may view these sources, but not process them. These are : > kcpsm.EDN Hmm, what design flow do you use? And which device? -- MfG FalkArticle: 39889
If I understand you right, you are voicing a fundamental problem: There can be bidirectional lines with 3-state buffers on the pc-board, and there can also be such bidirectional Longlines with 3-state drivers inside the Xilinx chip. But you cannot make a bidirectional connection across the chip boundary. The reason is that there are separate unidirectional output and input amplifiers at the chip boundary. Inputs are always active, but outputs can be 3-stated. You cannot cross the chip boundary without controlling the 3-state driver. This is fundamental, and I know of no circuit trick to overcome it, since we will never bring unbuffered internal signals to the pins. Peter Alfke, Xilinx Applications ============================ Jason LaPenta wrote: > Hello, > > I'm not sure how to classify this problem so here's my best > explaination. I'm using a Xilinx part, and in order to use LVDS, LVPECL, > or 5V outputs, I need to specify the IOBUFs manually. Xilinx does not > have an IOBUF that takes inout data from the internal FPGA, so I'm > required to breakout the internal tristate buffers into an input, > output, and tristate signals. This is turning my code into a real mess. > > Has anyone run into this problem and found an elegant solution? > > Thanks > Jason > s_p_a_m_lapenta_jm@yahoo.com_spamArticle: 39890
Hi Madhu... The set of digital circuits which can be described by only their inputs and outputs is quite limited. Consider trying to describe a simple 2-input 32-bit adder by using inputs and outputs. Or better yet apply it to an decryption unit (like in your pay TV decoder). What your friend is saying is correct. The hard part is generation of enough I/O vectors to fully or even adequately describe the functionallity of the digital system. The same apply's to your C program generator. Eric Pearson "Madhu" <pp_madhavi@yahoo.com> wrote in message news:c074a7b1c70d79729ac318bbc52aa174.67011@mygate.mailgate.org... > Hi all, > here is an argument with one of my friend who is a mechanical engineer > and writing S/W. > He argues that if the input and output waveforms are given he can > write a tool which generates a digital circuit for those inputs and > outputs. He knows about truth tables and gates. > He is not convinced when I told all digital circuits are not just > combinational. > Then I asked him whether he can generate a C program if the inputs and > outputs are given. But he says that it is obsurd that I am comparing a > language with digital design. > Still he believes in what he says. > So friends, please do respond. > Thank you > Madhu > > > -- > Posted via Mailgate.ORG Server - http://www.Mailgate.ORGArticle: 39891
Ray Andraka wrote: > AFAIK, the webpack version of IMPACT only supports JTAG downloads. > > Falk Brunner wrote: > > > "Ray Andraka" <ray@andraka.com> schrieb im Newsbeitrag > > news:3C750BE8.DE42CE4C@andraka.com... > > > They replaced it with something called "iMPACT". I haven't used it yet, > > so I > > > can't tell you how good/bad it is. It does still require you to do a full > > > xilinx install to be able to download devices :-( > > > > If you want to use only the commercial version, then YES. > > But there is also the WEBPACK version of IMPACT, which is AFAIK identical to > > the commercial version. > > So you jst need to install IMPACT (WEBPACK) > > > > -- > > MfG > > Falk > > -- > --Ray Andraka, P.E. > President, the Andraka Consulting Group, Inc. > 401/884-7930 Fax 401/884-7950 > email ray@andraka.com > http://www.andraka.com > > "They that give up essential liberty to obtain a little > temporary safety deserve neither liberty nor safety." > -Benjamin Franklin, 1759 Aha! iMPACT is the merged version of JTAGProgrammer and HardwareDebugger but I couldn't see this because I'm using iMPACT from WEBPACK [as a JTAG programmer for XC95K & XC18Vxx] which I loaded that well before I started experimenting with 4.1i.Article: 39892
Jason LaPenta wrote: > Hello, > > I'm not sure how to classify this problem so here's my best > explaination. I'm using a Xilinx part, and in order to use LVDS, LVPECL, > or 5V outputs, I need to specify the IOBUFs manually. Xilinx does not > have an IOBUF that takes inout data from the internal FPGA, so I'm > required to breakout the internal tristate buffers into an input, > output, and tristate signals. This is turning my code into a real mess. > > Has anyone run into this problem and found an elegant solution? > > Thanks > Jason > s_p_a_m_lapenta_jm@yahoo.com_spam Its a standard problem and, as Peter points out, you can't just take an internal tri-state across the chip boundary. A second question is: Why are you using internal tri-state buffers ? They are slower, they have been getting fewer from XC4K->Virtex->Virtex-2, and the placement restrictions are much greater than using unidirectional signals internally + muxes. If you do abandon internal tri-states then you can do this for a synthesisable bi-dir. wire foo_out, foo_enable; // Assignment is somewhere else ... inout foo; assign foo = foo_enable ? foo_out : 1'bz; wire foo_in = foo; And hold the actual buffer type in a separate constraints file; makes it a lot easier to change IO standards. At least you can do that if you're using Synplify.Article: 39893
Hi - "Madhu" <pp_madhavi@yahoo.com> wrote in message news:<c074a7b1c70d79729ac318bbc52aa174.67011@mygate.mailgate.org>... > Hi all, > here is an argument with one of my friend who is a mechanical engineer > and writing S/W. > He argues that if the input and output waveforms are given he can > write a tool which generates a digital circuit for those inputs and > outputs. He knows about truth tables and gates. > He is not convinced when I told all digital circuits are not just > combinational. > Then I asked him whether he can generate a C program if the inputs and > outputs are given. But he says that it is obsurd that I am comparing a > language with digital design. > Still he believes in what he says. > So friends, please do respond. > Thank you > Madhu Here's a challenge to your friend, a simple single-input, single-output digital block that he can use to test his theory. Just do the following: 1) create an arbitrary message. 2) convert the message to ASCII, then convert the ASCII to a single bitstream. 3) feed the bitstream through a triple-DES encoder; label the resulting bitstream INPUT. 4) Label your original message bitstream OUTPUT. 5) Convert the INPUT and OUTPUT bitstreams to waveform diagrams. Now give your friend the waveform diagrams, and ask him to write a program that creates the logic to produce OUTPUT from INPUT. I'd do it myself, but I'm kind of busy. Take care, Bob Perlman ---------- Cambrian Design Works send mail to cambriandesign.com user name bobArticle: 39894
I think the problem is with the BIOS setting for the parallel port. You have to set it to EPP (or was it ECP, i'm not sure). This could solve your problem "Kumar" <yatiks@yahoo.com> wrote in message news:b479edf8.0202202254.58dbda7e@posting.google.com... > Hi, > > I am using B5 Spartan2+ Board from Bruch Electronics Designs > containing XC2s200-5PQ208 FPGA .Xilinx ISE BASEX software .Impact > Programing tool (Downloading mode JTAG).Synthesis and implimentation > through FPGA Express .PC Configuration P4 1.7GHz with 850 chipset from > Intel. > > Problem : I have not faced any problem till generating Bit files.While > Downloading the bit file to FPGA ( XC2s200-5PQ208 ) through > JTAG ,I am facing a problem "Cable connection failed. Elapsed time = > 23 sec" . and getting a warning error > WARNING:iMPACT:547 - Can not find cable, please check cable setup ! > > Then I connected the same Board to other PC with less speed( config > --366 Mhz Celeron ) I have not faced any problem in programming the > FPGA ( XC2s200-5PQ208 ) through JTAG with same cable (length = appr 5 > feet). > > Can anybody tell what is causing the problem (is the speed of the PC > or something else) and also how can I solve this problem ???????? > > regards > Yathish Kumar > yatiks@yahoo.comArticle: 39895
> We've seen similar problems on occasion, it is certainly not unique to Dell machines, and not all Dell machines do it. In our experience it has been due to a glitch on the program line. To work around it, we have been leaving the program wire on > the cable unconnected and manually pulsing the program input to the board. > > Neil wrote: > > > I've had problems with Dell parallel ports with other devices. The fix for me has been to use an old parallel port zip drive to buffer the signal! I'm not sure this will help in this case, but if you can find an old zip drive, it's worth a try! I made JTAG parallel cable with 2 74HC125 about a year ago and used it with no problems on 2 Dells - Optiplex and Dimension, and programmed Spartan-II, Spartan-IIE, XC9500 and XCV400. I used 5V supply for cable for XC9500 and 3.3V supply for others, everything was fine. I had no problems with WebPack 3.3 SP8 programmer software until one day, that day both computers refused to program any chip that I knew was good. I thought cable was dead and replaced both 74HC125-s with no effect. One day later I received mail from Xilinx about next WebPack and day after that I downloaded WebPack 4 first release and chips and cable were working again, I could program all of them.Article: 39896
Hello, I'm trying to configure a XC2S30 FPGA from the ISA bus in a PC (embedded). The configuration file generation is no problem and I'm following the datasheet and application note for 'Parallel slave' programming: (as seen from the processor) WRITE# = '0' (always) PROGRAM# = '1' INIT# = input with pull up DONE = input with pull up CCLK = IOW# CS# = CS# from ISA bus (0x360) DATA = DATA To start I pulse the PROGRAM# low and wait for INIT# to come high. Then I start writing to addres 0x360. After the last byte the DONE line is high, but the INIT line is low. According to the datasheet this line should be high aswell. The content of the FPGA is correct, I can access the internal registers. Why is the INIT# pin low? Thanks in advanceArticle: 39897
I am wondering if someone has done a Verilog/VHDL mixed language
design in ISE WebPACK 4.1 with XST.
I have a top module written in Verilog, and a lower module written in
VHDL.
What I want to do here is to instantiate the lower module written in
VHDL from the top module written in Verilog, and implement the design
(Implementing a design means going through NGDBUILD -> MAP -> PAR.).
However, the problem with ISE WebPACK 4.1 is that when I create a
project, I have to select a Verilog flow, a VHDL flow, or an EDIF flow,
and there is no support for mixed Verilog/VHDL flow.
I know my question sounds like a real beginner's question, but should I
create two different projects, one for the Verilog top module and
another one for VHDL lower module, declare a blackbox in the Verilog top
module, synthesize them separately with XST, and glue them together with
NGDBUILD?
Also, in addition to the VHDL module, can I also attach an EDIF module
to the Verilog top module in NGDBUILD?
Has anyone done any of these, and are there things I should watch out
for?
Thanks,
Kevin Brace (Don't respond to me directly, respond within the
newsgroup.)
Article: 39898"Tim" <tim@rockylogic.com.nooospam.com> writes: > Linux support seems to be leaking out. See the X web page. Woo hoo! And though they're just running with Wine for now, they say they'll have native Linux tools in 2003.Article: 39899
Johann Glaser <Johann.Glaser@gmx.at> writes: > Could Xilinx please release the bitgen, par, > map, ... executables which are necessary for my task to be downloaded? Ain't gonna happen. They are not going to spend even the tiniest amount of money and effort to support new designs using the original Spartan family with free tools. The only way you're going to get what you need for those parts is to buy the real software or the student edition. Save yourself a bunch of hassle and switch to the Spartan II.
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