Messages from 39975

Article: 39975
Subject: Re: CPLD PROJECT
From: Kevin Brace <ihatespam99kevinbraceusenet@ihatespam99hotmail.com>
Date: Fri, 22 Feb 2002 15:58:58 -0600
Links: << >> << T >> << A >>

One more thing I forgot to mention. . .
There is nothing wrong to use Verilog with FPGA/CPLD.
XST (ISE WebPACK's synthesis tool) supports Verilog fine, and I think it
is far less buggier than Mentor Graphics' LeonardoSpectrum.



Kevin Brace (Don't respond to me directly, respond within the
newsgroup.)

Article: 39976
Subject: Re: CPLD PROJECT
From: kayrock66@yahoo.com (Jay)
Date: 22 Feb 2002 14:00:09 -0800
Links: << >> << T >> << A >>

Web pack is great and its free.  And you won't fit a CPU into a CPLD
(or much of one anyway).

yoram@puc.cl (Yoram Rovner) wrote in message news:<62ef4351.0202220559.132a1553@posting.google.com>...
> Hi:
> 
> I am a newbie on fpga issues and I need some recomendations. I am
> planning to develop a cpu in a cpld. I have XESS XS95 board v.1.3 and
> the student edition of Xilinx Foundation 1.5. I had some experiences
> in programing with verilog so i will like to do this cpu in that
> language. I have heard that Xilinx foundation student edition do not
> provide a good tool for developing with verilog (i mean error reports,
> etc). Would be better to use Webpack ise?, is there another
> software(maybe free or low cost) that is recommended to use?
> 
> 
> Thanks,
> 
> 
> Yoram Rovner

Article: 39977
Subject: Re: Linux tools
From: Petter Gustad <newsmailcomp1@gustad.com>
Date: Fri, 22 Feb 2002 22:04:24 GMT
Links: << >> << T >> << A >>

Uwe Bonnes <bon@elektron.ikp.physik.tu-darmstadt.de> writes:

> Jan Pech <j.pech@ieee.org> wrote:
> :> http://www.xilinx.com/prs_rls/software/0225_Em_Linux.html
> 
> : But it's not native Linux application.... It's only Windows version that can
> : be used under Wine:(
> 
> Where's the difference?
> 
> The Windows API is a library like Motif, lesstif, qt, gnome. Is a Motif
> program  compiled on Win32 not a native Windows application? Is a Gnome
> programm running on you KDE Desktop not a native Linux programm?
> 
> Understand the concept of Wine.

One important (at least to me) difference between the Windows version
(and I assume this includes the Linux/Wine version too?) and the
Solaris version is that you can do run multiple par iterations across
a cluster of machines under Solaris.

Petter
-- 
________________________________________________________________________
Petter Gustad   8'h2B | (~8'h2B) - Hamlet in Verilog   http://gustad.com

Article: 39978
Subject: Re: How can I disable clock buffer (BUFG) insertion in Xilinx Foundation F3.1i?
From: "Theron Hicks" <hicksthe@egr.msu.edu>
Date: Fri, 22 Feb 2002 17:13:41 -0500
Links: << >> << T >> << A >>


"Falk Brunner" <Falk.Brunner@gmx.de> wrote in message
news:a569i4$r7dc$1@ID-84877.news.dfncis.de...
> "JHL" <jaehwanida@orgio.net> schrieb im Newsbeitrag
> news:jyqd8.135$Az6.595@news.hananet.net...
> > Hello everyone!
> >
> > I now program virtex(XCV50-4BG256) using VHDL.
> > Because I use many clock signal in my design, when I make my VHDL source
>
> At first, try to use as less clock signals as possible. Forget about all
> those old coding styles from the TTL aera, they dont work well with FPGAs.
> Use clock enables instead. Read the coding style guide from Xilinx.

Where would I find such a guide?

 Or the
> actuall Tech-exclusive on the homepage.

And where might I find the Tech-exclusive?

>
> > synthesized into the chip, I often receive some error messages, which
say
> to
> > me that it is impossible to map
> > my source to this chip because of lack of CLK buffer resource.
>
> If you really need more clock, you can disable the BUFG usage in the
> synthesis constraints. Switch to the versions view, then click right on
your
> version, in the pop-up you will find a point synthesis constraint. In the
> next window you will find a tab called "port", there you can select the
BUFG
> insertion or not.
>
> --
> MfG
> Falk
>
>
>
>

Article: 39979
Subject: Re: How can I disable clock buffer (BUFG) insertion in Xilinx Foundation F3.1i?
From: "Falk Brunner" <Falk.Brunner@gmx.de>
Date: Fri, 22 Feb 2002 23:36:46 +0100
Links: << >> << T >> << A >>

"Theron Hicks" <hicksthe@egr.msu.edu> schrieb im Newsbeitrag
news:a56e9d$1i0c$1@msunews.cl.msu.edu...
>
> > At first, try to use as less clock signals as possible. Forget about all
> > those old coding styles from the TTL aera, they dont work well with
FPGAs.
> > Use clock enables instead. Read the coding style guide from Xilinx.
>
> Where would I find such a guide?

www.xilinx.com
support -> documentation

>  Or the
> > actuall Tech-exclusive on the homepage.
>
> And where might I find the Tech-exclusive?

support

--
MfG
Falk

Article: 39980
Subject: Re: Orca FPSC synthesizing issue
From: arvindk@xebeo.com (Arvind Kumar)
Date: 22 Feb 2002 14:41:43 -0800
Links: << >> << T >> << A >>

Hi,
  If I understood correctly, you are trying to use the core inside
FPSC and generating the netlist. While synthesizing the design,
synthesis tool will consider it as a blackbox. You might want to try
this. Goto ORCA Foundry and before running NGDbuild, give the path for
PCI core netlist. and then take the design through P&R flow. I have a
feeling it will work. The problem may be that orca foundry is not able
to see the netlist for core. In ORCA Foundry, you have to specify the
path.
Hope this helps..
Arvind Kumar
FPGA Design Engineer,
Xebeo Communications, Inc.
One Cragwood Rd. Suite 100
S. Plainfield, NJ 07080
USA



Carsten Heise <c_heise@web.de> wrote in message news:<1103_1014120452@news.tu-bs.de>...
> Hello,
> 
> I try to use an Orca FPSC with an integrated PCI-Core (its an ASIC on the same chip as the FPGA area).
> The functional design was made in scematic capture in Viewlogic's Viewdraw and the PCI-Core (that is
> represented by a VHDL netlist) was included as a symbol. The next step was to create an EDIF netlist.
> 	I want to use FPGA Express to synthesize the whole design with the PCI-Core. To check the
> combining of the PCI-Core with a schematic, I just created one with an OR gate connected with the symbol
> of the PCI-Core. After this Icreated an EDIF netlist from the schematic and added the netlist and the
> VHDL netlist of the Core to a FPGA Express project.
> First problem was a warning:
> Warning: Cannot link cell 'OR3TP12_INTF/OR3TP12_CORE_INST' to its reference design 'or3tp12_core6_ts'.  (FPGA-LINK-2)
> I could prevent this warning by adding an architecture to the entity 'or3tp12_core6_ts'. After the design
> was synthesized, I exported an EDIF netlist for the use in the Orca Foundry to place-and-route the design.
> There an error occured called
> ERROR - ngdbuild: logical root block 'NUR_CORE' with type 'NUR_CORE' is unexpanded
> Next, I had a look at the exported netlist and found it nearly empty.
> 
> I don't have any explanation for this. I hope somebody can give me a hint.
> 
> Best Regards
> 
> Carsten
> 
> Edif netlist of the schematic design:
> 
> (edif nur_core
>   (edifVersion 2 0 0)
>   (edifLevel 0)
>   (keywordMap (keywordLevel 0))
>   (status
>     (written
>       (timeStamp 2002 2 19 10 28 25)
>       (program "VIEWlogic's edifneto" (version "7.5.p (Nov  4 1999)"))))
>   (library NUR_CORE
>     (edifLevel 0)
>     (technology (numberDefinition (scale 1 (E 1 -12) (unit CAPACITANCE))))
> 
>     (cell (rename ORCA_OR2_1 "OR2")
>       (cellType GENERIC)
>         (status (written
>          (timeStamp 2001 1 25 4 46 46)))
>       (userData VL_PLATFORM_CODE (string "K 310014272500 OR2")
>         (owner "Viewlogic_Systems"))
>       (userData LIBNAME
>         (string "ORCA")
>           (owner "Viewlogic_Systems"))
>       (view view_1
>         (viewType NETLIST)
>         (interface
>           (port A
>             (direction INPUT))
>           (port B
>             (direction INPUT))
>           (port Z
>             (direction OUTPUT))
>           (property (rename &_DEL_A_Z_F_2 "@DEL_A_Z_F") (string "100PS") (owner "Viewlogic_Systems"))
>           (property (rename &_DEL_A_Z_R_3 "@DEL_A_Z_R") (string "100PS") (owner "Viewlogic_Systems"))
>           (property (rename &_DEL_B_Z_F_4 "@DEL_B_Z_F") (string "100PS") (owner "Viewlogic_Systems"))
>           (property (rename &_DEL_B_Z_R_5 "@DEL_B_Z_R") (string "100PS") (owner "Viewlogic_Systems"))
>           (property LEVEL (string "ORCA") (owner "Viewlogic_Systems")))
>       ))
> 
>     (cell OR3TP12_INTF
>       (cellType GENERIC)
>       (userData VL_PLATFORM_CODE (string "K 184991017000 OR3TP12_INTF")
>         (owner "Viewlogic_Systems"))
>       (view view_1
>         (viewType NETLIST)
>         (interface
>           (port CLK
>             (property FPSC_PAD (string "%34%TRUE%34%") (owner "Viewlogic_Systems"))
>             (direction INPUT)
>             (property VHDL_TYPE (string "STD_LOGIC") (owner "Viewlogic_Systems")))
>           (port RSTN
>             (property FPSC_PAD (string "%34%TRUE%34%") (owner "Viewlogic_Systems"))
>             (direction INPUT)
>             (property VHDL_TYPE (string "STD_LOGIC") (owner "Viewlogic_Systems")))
>           (port (array  (rename AD_63_0__6 "AD[63:0]") 64 )
>             (property FPSC_PAD (string "%34%TRUE%34%") (owner "Viewlogic_Systems"))
>             (direction INOUT)
>             (property VHDL_TYPE (string "STD_LOGIC_VECTOR") (owner "Viewlogic_Systems")))
>           (port (array  (rename C_BEN_7_0__7 "C_BEN[7:0]") 8 )
>             (property FPSC_PAD (string "%34%TRUE%34%") (owner "Viewlogic_Systems"))
>             (direction INOUT)
>             (property VHDL_TYPE (string "STD_LOGIC_VECTOR") (owner "Viewlogic_Systems")))
>           (port PAR
>             (property FPSC_PAD (string "%34%TRUE%34%") (owner "Viewlogic_Systems"))
>             (direction INOUT)
>             (property VHDL_TYPE (string "STD_LOGIC") (owner "Viewlogic_Systems")))
>           (port FRAMEN
>             (property FPSC_PAD (string "%34%TRUE%34%") (owner "Viewlogic_Systems"))
>             (direction INOUT)
>             (property VHDL_TYPE (string "STD_LOGIC") (owner "Viewlogic_Systems")))
>           (port IRDYN
>             (property FPSC_PAD (string "%34%TRUE%34%") (owner "Viewlogic_Systems"))
>             (direction INOUT)
>             (property VHDL_TYPE (string "STD_LOGIC") (owner "Viewlogic_Systems")))
>           (port TRDYN
>             (property FPSC_PAD (string "%34%TRUE%34%") (owner "Viewlogic_Systems"))
>             (direction INOUT)
>             (property VHDL_TYPE (string "STD_LOGIC") (owner "Viewlogic_Systems")))
>           (port STOPN
>             (property FPSC_PAD (string "%34%TRUE%34%") (owner "Viewlogic_Systems"))
>             (direction INOUT)
>             (property VHDL_TYPE (string "STD_LOGIC") (owner "Viewlogic_Systems")))
>           (port IDSEL
>             (property FPSC_PAD (string "%34%TRUE%34%") (owner "Viewlogic_Systems"))
>             (direction INPUT)
>             (property VHDL_TYPE (string "STD_LOGIC") (owner "Viewlogic_Systems")))
>           (port DEVSELN
>             (property FPSC_PAD (string "%34%TRUE%34%") (owner "Viewlogic_Systems"))
>             (direction INOUT)
>             (property VHDL_TYPE (string "STD_LOGIC") (owner "Viewlogic_Systems")))
>           (port REQN
>             (property FPSC_PAD (string "%34%TRUE%34%") (owner "Viewlogic_Systems"))
>             (direction OUTPUT)
>             (property VHDL_TYPE (string "STD_LOGIC") (owner "Viewlogic_Systems")))
>           (port GNTN
>             (property FPSC_PAD (string "%34%TRUE%34%") (owner "Viewlogic_Systems"))
>             (direction INPUT)
>             (property VHDL_TYPE (string "STD_LOGIC") (owner "Viewlogic_Systems")))
>           (port PERRN
>             (property FPSC_PAD (string "%34%TRUE%34%") (owner "Viewlogic_Systems"))
>             (direction INOUT)
>             (property VHDL_TYPE (string "STD_LOGIC") (owner "Viewlogic_Systems")))
>           (port SERRN
>             (property FPSC_PAD (string "%34%TRUE%34%") (owner "Viewlogic_Systems"))
>             (direction OUTPUT)
>             (property VHDL_TYPE (string "STD_LOGIC") (owner "Viewlogic_Systems")))
>           (port INTAN
>             (property FPSC_PAD (string "%34%TRUE%34%") (owner "Viewlogic_Systems"))
>             (direction OUTPUT)
>             (property VHDL_TYPE (string "STD_LOGIC") (owner "Viewlogic_Systems")))
>           (port REQ64N
>             (property FPSC_PAD (string "%34%TRUE%34%") (owner "Viewlogic_Systems"))
>             (direction INOUT)
>             (property VHDL_TYPE (string "STD_LOGIC") (owner "Viewlogic_Systems")))
>           (port ACK64N
>             (property FPSC_PAD (string "%34%TRUE%34%") (owner "Viewlogic_Systems"))
>             (direction INOUT)
>             (property VHDL_TYPE (string "STD_LOGIC") (owner "Viewlogic_Systems")))
>           (port PAR64
>             (property FPSC_PAD (string "%34%TRUE%34%") (owner "Viewlogic_Systems"))
>             (direction INOUT)
>             (property VHDL_TYPE (string "STD_LOGIC") (owner "Viewlogic_Systems")))
>           (port EJECTSW
>             (property FPSC_PAD (string "%34%TRUE%34%") (owner "Viewlogic_Systems"))
>             (direction INPUT)
>             (property VHDL_TYPE (string "STD_LOGIC") (owner "Viewlogic_Systems")))
>           (port ENUMN
>             (property FPSC_PAD (string "%34%TRUE%34%") (owner "Viewlogic_Systems"))
>             (direction OUTPUT)
>             (property VHDL_TYPE (string "STD_LOGIC") (owner "Viewlogic_Systems")))
>           (port LEDN
>             (property FPSC_PAD (string "%34%TRUE%34%") (owner "Viewlogic_Systems"))
>             (direction OUTPUT)
>             (property VHDL_TYPE (string "STD_LOGIC") (owner "Viewlogic_Systems")))
>           (port MAENN
>             (direction INPUT)
>             (property VHDL_TYPE (string "STD_LOGIC") (owner "Viewlogic_Systems")))
>           (port MA_FULLN
>             (direction OUTPUT)
>             (property VHDL_TYPE (string "STD_LOGIC") (owner "Viewlogic_Systems")))
>           (port MWDATAENN
>             (direction INPUT)
>             (property VHDL_TYPE (string "STD_LOGIC") (owner "Viewlogic_Systems")))
>           (port MW_AFULLN
>             (direction OUTPUT)
>             (property VHDL_TYPE (string "STD_LOGIC") (owner "Viewlogic_Systems")))
>           (port MW_FULLN
>             (direction OUTPUT)
>             (property VHDL_TYPE (string "STD_LOGIC") (owner "Viewlogic_Systems")))
>           (port MRDATAENN
>             (direction INPUT)
>             (property VHDL_TYPE (string "STD_LOGIC") (owner "Viewlogic_Systems")))
>           (port MR_AEMPTYN
>             (direction OUTPUT)
>             (property VHDL_TYPE (string "STD_LOGIC") (owner "Viewlogic_Systems")))
>           (port MR_EMPTYN
>             (direction OUTPUT)
>             (property VHDL_TYPE (string "STD_LOGIC") (owner "Viewlogic_Systems")))
>           (port FIFO_SEL
>             (direction INPUT)
>             (property VHDL_TYPE (string "STD_LOGIC") (owner "Viewlogic_Systems")))
>           (port TAENN
>             (direction INPUT)
>             (property VHDL_TYPE (string "STD_LOGIC") (owner "Viewlogic_Systems")))
>           (port TREQN
>             (direction OUTPUT)
>             (property VHDL_TYPE (string "STD_LOGIC") (owner "Viewlogic_Systems")))
>           (port TWDATAENN
>             (direction INPUT)
>             (property VHDL_TYPE (string "STD_LOGIC") (owner "Viewlogic_Systems")))
>           (port (array  (rename DATATOFPGA_31_0__8 "DATATOFPGA[31:0]") 32 )
>             (direction OUTPUT)
>             (property VHDL_TYPE (string "STD_LOGIC_VECTOR") (owner "Viewlogic_Systems")))
>           (port DATATOFPGAX2
>             (direction OUTPUT)
>             (property VHDL_TYPE (string "STD_LOGIC") (owner "Viewlogic_Systems")))
>           (port DATATOFPGAX3
>             (direction OUTPUT)
>             (property VHDL_TYPE (string "STD_LOGIC") (owner "Viewlogic_Systems")))
>           (port DATATOFPGAX0
>             (direction OUTPUT)
>             (property VHDL_TYPE (string "STD_LOGIC") (owner "Viewlogic_Systems")))
>           (port DATATOFPGAX1
>             (direction OUTPUT)
>             (property VHDL_TYPE (string "STD_LOGIC") (owner "Viewlogic_Systems")))
>           (port (array  (rename DATAFMFPGA_31_0__9 "DATAFMFPGA[31:0]") 32 )
>             (direction INPUT)
>             (property VHDL_TYPE (string "STD_LOGIC_VECTOR") (owner "Viewlogic_Systems")))
>           (port DATAFMFPGAX2
>             (direction INPUT)
>             (property VHDL_TYPE (string "STD_LOGIC") (owner "Viewlogic_Systems")))
>           (port DATAFMFPGAX3
>             (direction INPUT)
>             (property VHDL_TYPE (string "STD_LOGIC") (owner "Viewlogic_Systems")))
>           (port DATAFMFPGAX0
>             (direction INPUT)
>             (property VHDL_TYPE (string "STD_LOGIC") (owner "Viewlogic_Systems")))
>           (port DATAFMFPGAX1
>             (direction INPUT)
>             (property VHDL_TYPE (string "STD_LOGIC") (owner "Viewlogic_Systems")))
>           (port TW_AEMPTYN
>             (direction OUTPUT)
>             (property VHDL_TYPE (string "STD_LOGIC") (owner "Viewlogic_Systems")))
>           (port TW_EMPTYN
>             (direction OUTPUT)
>             (property VHDL_TYPE (string "STD_LOGIC") (owner "Viewlogic_Systems")))
>           (port TRDATAENN
>             (direction INPUT)
>             (property VHDL_TYPE (string "STD_LOGIC") (owner "Viewlogic_Systems")))
>           (port TR_AFULLN
>             (direction OUTPUT)
>             (property VHDL_TYPE (string "STD_LOGIC") (owner "Viewlogic_Systems")))
>           (port TR_FULLN
>             (direction OUTPUT)
>             (property VHDL_TYPE (string "STD_LOGIC") (owner "Viewlogic_Systems")))
>           (port TFIFOCLRN
>             (direction INPUT)
>             (property VHDL_TYPE (string "STD_LOGIC") (owner "Viewlogic_Systems")))
>           (port MFIFOCLRN
>             (direction INPUT)
>             (property VHDL_TYPE (string "STD_LOGIC") (owner "Viewlogic_Systems")))
>           (port TRPCIHOLD
>             (direction INPUT)
>             (property VHDL_TYPE (string "STD_LOGIC") (owner "Viewlogic_Systems")))
>           (port MWPCIHOLD
>             (direction INPUT)
>             (property VHDL_TYPE (string "STD_LOGIC") (owner "Viewlogic_Systems")))
>           (port TRBURSTPENDN
>             (direction INPUT)
>             (property VHDL_TYPE (string "STD_LOGIC") (owner "Viewlogic_Systems")))
>           (port DISCTIMEREXPN
>             (direction OUTPUT)
>             (property VHDL_TYPE (string "STD_LOGIC") (owner "Viewlogic_Systems")))
>           (port PCI_INTAN
>             (direction INPUT)
>             (property VHDL_TYPE (string "STD_LOGIC") (owner "Viewlogic_Systems")))
>           (port FPGA_MBUSYN
>             (direction INPUT)
>             (property VHDL_TYPE (string "STD_LOGIC") (owner "Viewlogic_Systems")))
>           (port FPGA_MSYSERROR
>             (direction OUTPUT)
>             (property VHDL_TYPE (string "STD_LOGIC") (owner "Viewlogic_Systems")))
>           (port FCLK1
>             (direction INPUT)
>             (property VHDL_TYPE (string "STD_LOGIC") (owner "Viewlogic_Systems")))
>           (port FCLK2
>             (direction INPUT)
>             (property VHDL_TYPE (string "STD_LOGIC") (owner "Viewlogic_Systems")))
>           (port PCICLK
>             (direction OUTPUT)
>             (property VHDL_TYPE (string "STD_LOGIC") (owner "Viewlogic_Systems")))
>           (port PCI_RSTN
>             (direction OUTPUT)
>             (property VHDL_TYPE (string "STD_LOGIC") (owner "Viewlogic_Systems")))
>           (port T_ABORT
>             (direction INPUT)
>             (property VHDL_TYPE (string "STD_LOGIC") (owner "Viewlogic_Systems")))
>           (port MR_STOPBURSTN
>             (direction INPUT)
>             (property VHDL_TYPE (string "STD_LOGIC") (owner "Viewlogic_Systems")))
>           (port T_RETRYN
>             (direction INPUT)
>             (property VHDL_TYPE (string "STD_LOGIC") (owner "Viewlogic_Systems")))
>           (port FPGA_SYSERROR
>             (direction INPUT)
>             (property VHDL_TYPE (string "STD_LOGIC") (owner "Viewlogic_Systems")))
>           (port M_READY
>             (direction OUTPUT)
>             (property VHDL_TYPE (string "STD_LOGIC") (owner "Viewlogic_Systems")))
>           (port T_READY
>             (direction OUTPUT)
>             (property VHDL_TYPE (string "STD_LOGIC") (owner "Viewlogic_Systems")))
>           (port PCI_CFG_STAT
>             (direction OUTPUT)
>             (property VHDL_TYPE (string "STD_LOGIC") (owner "Viewlogic_Systems")))
>           (port (array  (rename TCMD_3_0__10 "TCMD[3:0]") 4 )
>             (direction OUTPUT)
>             (property VHDL_TYPE (string "STD_LOGIC_VECTOR") (owner "Viewlogic_Systems")))
>           (port (array  (rename MSTATECNTR_3_0__11 "MSTATECNTR[3:0]") 4 )
>             (direction OUTPUT)
>             (property VHDL_TYPE (string "STD_LOGIC_VECTOR") (owner "Viewlogic_Systems")))
>           (port (array  (rename TSTATECNTR_3_0__12 "TSTATECNTR[3:0]") 4 )
>             (direction OUTPUT)
>             (property VHDL_TYPE (string "STD_LOGIC_VECTOR") (owner "Viewlogic_Systems")))
>           (port (array  (rename BAR_2_0__13 "BAR[2:0]") 3 )
>             (direction OUTPUT)
>             (property VHDL_TYPE (string "STD_LOGIC_VECTOR") (owner "Viewlogic_Systems")))
>           (port TWLASTCYCN
>             (direction OUTPUT)
>             (property VHDL_TYPE (string "STD_LOGIC") (owner "Viewlogic_Systems")))
>           (port TRLASTCYCN
>             (direction OUTPUT)
>             (property VHDL_TYPE (string "STD_LOGIC") (owner "Viewlogic_Systems")))
>           (port MRLASTCYCN
>             (direction OUTPUT)
>             (property VHDL_TYPE (string "STD_LOGIC") (owner "Viewlogic_Systems")))
>           (port PCI_64BIT
>             (direction OUTPUT)
>             (property VHDL_TYPE (string "STD_LOGIC") (owner "Viewlogic_Systems")))
>           (port DELTRN
>             (direction INPUT)
>             (property VHDL_TYPE (string "STD_LOGIC") (owner "Viewlogic_Systems")))
>           (port MWLASTCYCN
>             (direction INPUT)
>             (property VHDL_TYPE (string "STD_LOGIC") (owner "Viewlogic_Systems")))
>           (port TWBURSTPENDN
>             (direction INPUT)
>             (property VHDL_TYPE (string "STD_LOGIC") (owner "Viewlogic_Systems")))
>           (port CFGSHIFTENN
>             (direction INPUT)
>             (property VHDL_TYPE (string "STD_LOGIC") (owner "Viewlogic_Systems")))
>           (port PWRUPRST
>             (property FPSC_PAD (string "%34%TRUE%34%") (owner "Viewlogic_Systems"))
>             (direction INPUT)
>             (property VHDL_TYPE (string "STD_LOGIC") (owner "Viewlogic_Systems")))
>           (property ACCEL (string "VANTAGE") (owner "Viewlogic_Systems"))
>           (property VHDL (string "OR3TP12_INTF") (owner "Viewlogic_Systems"))
>           (property VHDLFILE (string "OR3TP12_INTF.VHD") (owner "Viewlogic_Systems"))
>           (property VHDL_IMPORT_IEEE (string "LIBRARY") (owner "Viewlogic_Systems"))
>           (property (rename VHDL_IMPORT_IEEE_STD_LOGIC_1164_14 "VHDL_IMPORT_IEEE$STD_LOGIC_1164") (string "PACKAGE") (owner "Viewlogic_Systems")))
>       ))
> 
>     (cell NUR_CORE
>       (cellType GENERIC)
>         (status (written
>          (timeStamp 2002 2 19 10 28 13)))
>       (userData VL_PLATFORM_CODE (string "K 94718533990 NUR_CORE")
>         (owner "Viewlogic_Systems"))
>       (view view_1
>         (viewType NETLIST)
>         (interface)
>         (contents
>           (instance OR2
>             (viewRef view_1 (cellRef ORCA_OR2_1))
>             (property LABEL (string "OR2") (owner "Viewlogic_Systems")))
>           (instance (rename PCI_CORE_15 "PCI-CORE")
>             (viewRef view_1 (cellRef OR3TP12_INTF))
>             (property LABEL (string "PCI-CORE") (owner "Viewlogic_Systems")))
>           (net (rename &_MAENN_16 "/MAENN")
>             (joined
>               (portRef Z (instanceRef OR2))
>               (portRef MAENN (instanceRef PCI_CORE_15))))
>           (net (rename &_MA_FULLN_17 "/MA_FULLN")
>             (joined
>               (portRef B (instanceRef OR2))
>               (portRef MA_FULLN (instanceRef PCI_CORE_15))))
>           (net (rename &_MR_EMPTYN_18 "/MR_EMPTYN")
>             (joined
>               (portRef A (instanceRef OR2))
>               (portRef MR_EMPTYN (instanceRef PCI_CORE_15))))
>         )
>       ))
> 
>   )
>   (design NUR_CORE
>     (cellRef NUR_CORE
>       (libraryRef NUR_CORE))
>   )
> )
> 
> 
> Edif netlist exported from FPGA Express:
> 
> (edif  NUR_CORE
>   (edifVersion 2 0 0)
>   (edifLevel 0)
>   (keywordMap
>     (keywordLevel 0)
>   )
>   (status
>     (written
>       (timeStamp 2002 2 19 9 30 19)
>       (program "FPGA Express"
> 	(version "3.3.1.4719")
>       )
>       (author "carsten")
>     )
>   )
>   (library DESIGNS
>     (edifLevel 0)
>     (technology
>       (numberDefinition)
>     )
>     (cell NUR_CORE
>       (cellType GENERIC)
>       (view Netlist_representation
> 	(viewType NETLIST)
> 	(interface)
> 	(contents)
>       )
>     )
>   )
>   (design NUR_CORE
>     (cellRef NUR_CORE
>       (libraryRef DESIGNS)
>     )
>   )
> )

Article: 39981
Subject: Re: Faster designs
From: arvindk@xebeo.com (Arvind Kumar)
Date: 22 Feb 2002 14:56:00 -0800
Links: << >> << T >> << A >>

Hi,
  If I were you, I would 
    1. generate Timing report from Timing Analyzer..
    2. Check the Clock skew to see if some of the clocks are using
local routing        resources..
    3. Goto FPGA Editor and see if the critical paths are distributed
across the        region. If yes, then give the MAXDELAY attribute for
the net. RLOC
       Registers, if required..
    4. I think 6.25ns is surely achievable. 

Good Luck..!!!
Arvind Kumar
FPGA Design Engineer,
Xebeo Communications, Inc.
One Cragwood Road, Suite 100
South Plainfield, NJ 07080
USA

"Craig Ward" <ccward@waitrose.com> wrote in message news:<u75b2r8rif62ed@corp.supernews.com>...
> Hi,
> 
> Can anyone give me advice on how to improve my clock speed in my design.  I
> am using timing constraints before you ask!!.
> The chip is a Virtex2000E and I am using synplify and the latest Xilinx PAR
> (ise 4.1etc).  The delays in my design appear to be caused by a few long
> nets
> (fan out 1 etc).  There is lots of free space on the chip so this is not a
> problem.  My target speed is 6.25ns period and the best I can get to is 7ns
> etc with par effort at maximum.  I have tried re-entrant routing with no
> success.
> 
> The design is still being updated and added to so can anyone tell me how I
> can get better par in general ?  I would imagine that manual placement would
> give me better results in theory but then each time i changed the design I
> would have to repeat this process??  Help!
> 
> Cheers
> Craig

Article: 39982
Subject: Re: Coolrunner and ISP
From: hmurray-nospam@megapathdsl.net (Hal Murray)
Date: Sat, 23 Feb 2002 01:21:46 -0000
Links: << >> << T >> << A >>

>You mean add a PLD to allow me to reprogram my CPLD?  Part of the
>problem is that PLDs are not at all small.  This board is already very
>tight and I have never seen a PLD that came in a small enough package. 
>But I also don't like the idea of adding a PLD for this.  How do I
>in-system reprogram the PLD?  I might have to add muxes though... or
>just forget about using boundary scan chains.  

The idea is to use a small/simple PLD so you can get it right
the first time and won't have to reprogram it.

Put the junk you might want to reprogram in a corner of the CPLD.

Article: 39983
Subject: Re: Coolrunner and ISP
From: rickman <spamgoeshere4@yahoo.com>
Date: Sat, 23 Feb 2002 01:55:20 -0500
Links: << >> << T >> << A >>

Jim Granville wrote:
> 
> rickman wrote:
> >
> > Jim Granville wrote:
> > >
> > > rickman wrote:
> > ...snip...
> > > > The real problem is the lousy support of scan chains by the emulation
> > > > tool vendors.  They don't seem to understand that JTAG ports are for
> > > > anything other than emulation.
> > >
> > >  What about a SPLD like a 16V8, to klude what's needed ?
> > >
> > > - jg
> >
> > You mean add a PLD to allow me to reprogram my CPLD?
> 
> Yes.
> 
> > Part of the problem is that PLDs are not at all small.
> > This board is already very
> > tight and I have never seen a PLD that came in a small enough package.
> 
> Currently smallest is TSSOP20, 6.5mm x 6.5mm.
> 
> > But I also don't like the idea of adding a PLD for this.  How do I
> > in-system reprogram the PLD?
> 
> Why would you need to ?

The same reason that I in system reprogram any of the parts on the
board. Partly because of the falibility of humans (engineers are human,
well most engineers...) and because there is always a different/better
way to do something that doesn't occur until the board has shipped to a
foreign country.  :) 


> 
> > I might have to add muxes though... or
> > just forget about using boundary scan chains.
> 
> Agreed, it will be a compromise.
> 
> SPLD is lower profile, & less error prone than Jumpers, and is
> a little more 'soft' than a hard wired MUX solution.
> 
> Since SCAN+DEBUG is off the radar, as you say, future die versions
> ( or even SW versions :-), may have 'different features'
> 
> -jg

-- 

Rick "rickman" Collins

rick.collins@XYarius.com
Ignore the reply address. To email me use the above address with the XY
removed.

Arius - A Signal Processing Solutions Company
Specializing in DSP and FPGA design      URL http://www.arius.com
4 King Ave                               301-682-7772 Voice
Frederick, MD 21701-3110                 301-682-7666 FAX

Article: 39984
Subject: Re: Coolrunner and ISP
From: rickman <spamgoeshere4@yahoo.com>
Date: Sat, 23 Feb 2002 01:56:39 -0500
Links: << >> << T >> << A >>

Hal Murray wrote:
> 
> >You mean add a PLD to allow me to reprogram my CPLD?  Part of the
> >problem is that PLDs are not at all small.  This board is already very
> >tight and I have never seen a PLD that came in a small enough package.
> >But I also don't like the idea of adding a PLD for this.  How do I
> >in-system reprogram the PLD?  I might have to add muxes though... or
> >just forget about using boundary scan chains.
> 
> The idea is to use a small/simple PLD so you can get it right
> the first time and won't have to reprogram it.
> 
> Put the junk you might want to reprogram in a corner of the CPLD.

Ok, but I still have to program the part when the board is built.  Doing
that to a TSSOP20 in a socket programmer is not fun and is not very
compatible with high volume manufacturing. 


-- 

Rick "rickman" Collins

rick.collins@XYarius.com
Ignore the reply address. To email me use the above address with the XY
removed.

Arius - A Signal Processing Solutions Company
Specializing in DSP and FPGA design      URL http://www.arius.com
4 King Ave                               301-682-7772 Voice
Frederick, MD 21701-3110                 301-682-7666 FAX

Article: 39985
Subject: Re: Coolrunner and ISP
From: rickman <spamgoeshere4@yahoo.com>
Date: Sat, 23 Feb 2002 02:09:50 -0500
Links: << >> << T >> << A >>

Alan Nishioka wrote:
> 
> rickman wrote:
> 
> >That is not the problem.  My problem is that the wiring for the JTAG
> >chain gets very complex.  I have two processors and two PLDs in the
> >chain.  I need to run in five different modes;
> >
> >1) All four devices in one Boundary Scan chain.
> >
> >2) DSP as alone as I can get it for emulation.
> >
> >3) MCU totally alone for emulator that does not work in a chain.
> >
> >4) CPLD driven by MCU for in-system and in-field change to bit file.
> >
> >5) (optional maybe) CPLD in chain driven from header for factory load of
> >bit file.
> >This one might be done in mode 1) or in mode 4)
> >
> 
> I would use three separate JTAG "chains".
> I agree that you want only a single device in a chain for emulation.
> I don't like jumpers either.
> You can bus TCK/TDI/TDO together and have only three separate TMS's.

Maybe you can bus the others, but I don't think you can bus TDO. 

> I was going to suggest connecting the entire chain with resistors and
> overdriving parts of it, but I think three chains will work better (and
> not take a performance hit).
> 
> Alan Nishioka
> alann@accom.com

I spoke with a JTAG vendor and he suggested the multiple chain
solution.  The problem is that I don't have the room to add three
permanent connectors, just one for the DSP emulation.  So either I will
have to use a test fixture to contact test points, or add temp
connectors just for test and then remove them.  Obviously that is not
good for production test.  

I am going to put this off for a while so I can get the rest of the work
done and return to it later.  Maybe I will have a better perspective on
the problem by then. 

-- 

Rick "rickman" Collins

rick.collins@XYarius.com
Ignore the reply address. To email me use the above address with the XY
removed.

Arius - A Signal Processing Solutions Company
Specializing in DSP and FPGA design      URL http://www.arius.com
4 King Ave                               301-682-7772 Voice
Frederick, MD 21701-3110                 301-682-7666 FAX

Article: 39986
Subject: Re: Coolrunner and ISP
From: Jim Granville <jim.granville@designtools.co.nz>
Date: Sat, 23 Feb 2002 20:19:59 +1300
Links: << >> << T >> << A >>

rickman wrote:
> 
> Hal Murray wrote:
> >
> > >You mean add a PLD to allow me to reprogram my CPLD?  Part of the
> > >problem is that PLDs are not at all small.  This board is already very
> > >tight and I have never seen a PLD that came in a small enough package.
> > >But I also don't like the idea of adding a PLD for this.  How do I
> > >in-system reprogram the PLD?  I might have to add muxes though... or
> > >just forget about using boundary scan chains.
> >
> > The idea is to use a small/simple PLD so you can get it right
> > the first time and won't have to reprogram it.
> >
> > Put the junk you might want to reprogram in a corner of the CPLD.
> 
> Ok, but I still have to program the part when the board is built.  Doing
> that to a TSSOP20 in a socket programmer is not fun and is not very
> compatible with high volume manufacturing.

 No, for that you use factory programmed flows, but keep the TSSOP20 
programmer for development.
 Factory pgm is done for med volumes, > 10K region.

 A JTAG MUX is only likely to change with a major silicon rev, on
one of the big devices, and even then, it's likely to be a superset,
not a subset.

 Another option is to use a higher density JTAG connector, and share
as many pins as possible, but do a separate chain design.

 2mm pitch connectors are quite small, but avoid the price bite of the
really fine pitch devices.

-jg

Article: 39987
Subject: Implementing MD5 in hardware (Handel C, VHDL)
From: moriartl@tcd.ie (LM)
Date: 23 Feb 2002 00:35:16 -0800
Links: << >> << T >> << A >>

Has anyone tried to implement MD5 or DES in Handel C, or in VHDL? 
What was your approach?  If porting from c code to Handel C, what
particular problems did you encounter?  Thank you.

Article: 39988
Subject: Question about multiple Virtex DLLs locking management after configuration
From: "jean-francois hasson" <jfhasson@club-internet.fr>
Date: Sat, 23 Feb 2002 11:29:03 +0100
Links: << >> << T >> << A >>

Hi,

I am working with a Virtex XCV600 dealing with three different clocks each
involving a DLL. After configuration I woul like to be sure the all the DLLs
are locked before any other operation. Can I use the delay until locked
(STARTUP_WAIT) property of each DLL and everything will be fine or do I have
to use some logic between the different locked signals ?

Thanks,

JF

Article: 39989
Subject: Re: Coolrunner and ISP
From: rickman <spamgoeshere4@yahoo.com>
Date: Sat, 23 Feb 2002 09:44:30 -0500
Links: << >> << T >> << A >>

Jim Granville wrote:
> 
> rickman wrote:
> >
> > Hal Murray wrote:
> > >
> > > >You mean add a PLD to allow me to reprogram my CPLD?  Part of the
> > > >problem is that PLDs are not at all small.  This board is already very
> > > >tight and I have never seen a PLD that came in a small enough package.
> > > >But I also don't like the idea of adding a PLD for this.  How do I
> > > >in-system reprogram the PLD?  I might have to add muxes though... or
> > > >just forget about using boundary scan chains.
> > >
> > > The idea is to use a small/simple PLD so you can get it right
> > > the first time and won't have to reprogram it.
> > >
> > > Put the junk you might want to reprogram in a corner of the CPLD.
> >
> > Ok, but I still have to program the part when the board is built.  Doing
> > that to a TSSOP20 in a socket programmer is not fun and is not very
> > compatible with high volume manufacturing.
> 
>  No, for that you use factory programmed flows, but keep the TSSOP20
> programmer for development.
>  Factory pgm is done for med volumes, > 10K region.

So what do I use for ~1K/year volumes?  Adding this PLD complicates the
programming of the board a lot. 

>  A JTAG MUX is only likely to change with a major silicon rev, on
> one of the big devices, and even then, it's likely to be a superset,
> not a subset.

Unless we find a mistake or we realize something that we overlooked... 
I can't remember the last time that there were NO changes throughout a
product life.  

>  Another option is to use a higher density JTAG connector, and share
> as many pins as possible, but do a separate chain design.
> 
>  2mm pitch connectors are quite small, but avoid the price bite of the
> really fine pitch devices.
> 
> -jg

I have been wracking my brain to come up with a way to make this all
fit.  A 2mm connector still does not save me enough space to have three
scan chains and the extra signals for the second emulator.  Remember,
this is only 20% smaller than a .1" connector.  Also this becomes
totally incompatible with the DSP emulator cable which my customers will
need to use.  

But even so, this does not tell me how to program the PLD.  Unless you
are saying to have FOUR scan chains with the PLD being one that NEVER is
combined with the other three.  

-- 

Rick "rickman" Collins

rick.collins@XYarius.com
Ignore the reply address. To email me use the above address with the XY
removed.

Arius - A Signal Processing Solutions Company
Specializing in DSP and FPGA design      URL http://www.arius.com
4 King Ave                               301-682-7772 Voice
Frederick, MD 21701-3110                 301-682-7666 FAX

Article: 39990
Subject: Re: Beginner Altera Questions
From: "Peter Ormsby" <faepete.deletethis@mediaone.net>
Date: Sat, 23 Feb 2002 15:16:45 GMT
Links: << >> << T >> << A >>


Al Williams <alw@al-williams.com> wrote in message
news:a9835df1.0202221032.11d1ab7b@posting.google.com...
> Thanks Pete.
>
> I had heard Quartus now supported the low end but it wasn't clear to
> me if that was only the full version. Sigh. I'll have to go learn that
> too now :-)
>
> Thanks again -- I'll try the registry fix.

Ooops, it looks like they changed plans again.  It looks like the MAX
devices are NOT in the Quartus II WE yet (Still need to use MaxPlusII).  On
the positive side, the latest Quartus II WE DOES now support the ACEX 1K
family.

http://www.altera.com/products/software/sfw-quarwebmain.html

-Pete-

Article: 39991
Subject: Re: Pin assignments in QUARTUS
From: guiducci@cern.ch (Luigi)
Date: 23 Feb 2002 08:48:05 -0800
Links: << >> << T >> << A >>

Hi
thinking about some specific forum etc. about Altera Quartus and so on
(and Altera products, in general), I really agree. I'm quite new in
the field of FPGA/CPLD designing, and what I noticed is that it's easy
to find find thunderstorms of xilinx related discussion, not the same
with altera.
So, let us novices know!
Thanks for advices

Luigi

Article: 39992
(removed)

Article: 39993
Subject: Re: Need largest CPLD devices?
From: Andy Main <andymain@blueyonder.co.uk>
Date: Sat, 23 Feb 2002 18:38:59 GMT
Links: << >> << T >> << A >>

>
> Well, it looks like you work for a company, so burning a few buggy
> anti-fuse FPGAs won't cost you anything (It will cost the company
> something.).

Quicklogic lets you burn up to 10 webASICs for free!!  (we have been a very
happy customer at my workplace - save 20k on a new die just to test!)

Andy Main

Article: 39994
Subject: Re: Coolrunner and ISP
From: hmurray-nospam@megapathdsl.net (Hal Murray)
Date: Sat, 23 Feb 2002 21:04:52 -0000
Links: << >> << T >> << A >>

>>  A JTAG MUX is only likely to change with a major silicon rev, on
>> one of the big devices, and even then, it's likely to be a superset,
>> not a subset.
>
>Unless we find a mistake or we realize something that we overlooked... 
>I can't remember the last time that there were NO changes throughout a
>product life.  

I thought the idea was to use a (small) PLD to juggle the JTAG chain.
That seems simple enough so that the risk of not being able to
(easily) reprogram that PLD during the life of a board is worth taking.



>I have been wracking my brain to come up with a way to make this all
>fit.  A 2mm connector still does not save me enough space to have three
>scan chains and the extra signals for the second emulator.  Remember,
>this is only 20% smaller than a .1" connector.  Also this becomes
>totally incompatible with the DSP emulator cable which my customers will
>need to use.  

That's what they are paying you for.  :)

My reading is that JTAG still has a lot of growing up to do.  Until
it lives up to the hype, board designers are going to get stuck with 
crap like this.

I think the best you can do is one JTAG connector and some way
to select the device you want to talk to and bypass the ones
that will confuse the development software.  The straw man
is a connector with all the TDI/TDO signals so you can add
jumpers as appropriate.

Be sure to check the fine print on the "standard" JTAG
conector for each development system you plan to use.  The
2 or 3 that I've worked with have been slightly different.

Don't forget to pay attention to the clocks.


Does anybody know if JTAG works as expected for boundary scan
when several different devices are on the chain?  Say a DSP
and an FPGA?

-- 
These are my opinions, not necessarily my employer's.  I hate spam.

Article: 39995
Subject: Re: Replacing expensive configuration SPROM
From: "Mark van de Belt" <mark@nijenrode.demon.nl.spam.invalid>
Date: Sat, 23 Feb 2002 22:42:15 +0100
Links: << >> << T >> << A >>

I think there is an appnote on the xilinx website about the configuration
from a parallel (E)PROM and a small CPLD.

The cheapest option is to do it from the processor (parallel interface)
since often the interface to the data lines from the processor is needed
after configuration anyway. The interfacing is very simple (use the WR# as
the CCLK, and just perform writes to the right adress (activate the CS#)).

"Manfred Kraus" <newsreply@cesys.com> wrote in message
news:a55nj2$4t1hd$1@ID-22088.news.dfncis.de...
> Has anybody tried to get rid of the Xilinx SPROMS ?
> They are immoral expensive !
> Could be a small CPLD + Flash memory a cheaper solution ?
>
> - Manfred
>
>
>

Article: 39996
Subject: Re: Coolrunner and ISP
From: James Horn <jimhorn@svn.net>
Date: 23 Feb 2002 15:01:10 -0800
Links: << >> << T >> << A >>

What we've done (due to an emulator's insisting on the CPU being the only 
device on its chain) is to tie the TDIs together, the TDOs, and the TCKs 
as well.  Then each TMS comes to its own pin.

The bad news is that you can only emulate or otherwise do boundary scan on 
only one device at a time (by selecting its TMS).  The good news is that 
you *can* control each device independantly.  And if you only have a 
limited number of devices, the number of TMS lines is reasonable.  Of 
course, you can put a number of devices on a single chain and treat all 
their TMS lines as if that chain was a single device.

The trick is that TDO is High-Z if TMS isn't asserted.

Best to you and your designs!

Jim Horn, WB9SYN/6

PS: I'm not affiliated with them, but give the folks at Corelis or JTAG 
Tech a call - they're full of good suggestions on this subject.  Their App 
notes and published articles are well worth while.

Article: 39997
Subject: Re: Coolrunner and ISP
From: hmurray-nospam@megapathdsl.net (Hal Murray)
Date: Sun, 24 Feb 2002 00:51:27 -0000
Links: << >> << T >> << A >>

> The trick is that TDO is High-Z if TMS isn't asserted.

Neat/thanks.

Is that true for all parts using JTAG?  (Or just some/most
of them?)

I just took a quick scan at a few data sheets.  One said the TDO
pin could go tri-state but didn't give any hints (or timing diagrams)
on how to do it.  The other said it was pure output - no suggestion
of any disable.

-- 
These are my opinions, not necessarily my employer's.  I hate spam.

Article: 39998
Subject: Re: Coolrunner and ISP
From: Jim Granville <jim.granville@designtools.co.nz>
Date: Sun, 24 Feb 2002 16:43:34 +1300
Links: << >> << T >> << A >>

Hal Murray wrote:
> 
> >>  A JTAG MUX is only likely to change with a major silicon rev, on
> >> one of the big devices, and even then, it's likely to be a superset,
> >> not a subset.
> >
> >Unless we find a mistake or we realize something that we overlooked...
> >I can't remember the last time that there were NO changes throughout a
> >product life.
> 
> I thought the idea was to use a (small) PLD to juggle the JTAG chain.
> That seems simple enough so that the risk of not being able to
> (easily) reprogram that PLD during the life of a board is worth taking.

That's correct, the secret is the Kiss principle.

 We have done many designs using uC/SPLDs (as more complex things than 
JTAG MUXs), and the code tends to be as stable as a PCB layout.
 The same cannot be said for the adjacent Microcontroller :-)

-jg

Article: 39999
Subject: Re: How can I disable clock buffer (BUFG) insertion in Xilinx Foundation F3.1i?
From: "JHL" <jaehwanida@orgio.net>
Date: Sun, 24 Feb 2002 14:22:04 +0900
Links: << >> << T >> << A >>


> If you really need more clock, you can disable the BUFG usage in the
> synthesis constraints. Switch to the versions view, then click right on
your
> version, in the pop-up you will find a point synthesis constraint. In the
> next window you will find a tab called "port", there you can select the
BUFG
> insertion or not.

I cat not find "synthesis constraint"  in Project Manager of Xilinx
Foundation F3.1i.
What manu shows me viersions view you tell me in Xilinx Foundation F3.1i?
What is synthesis constraint?
I know olny "contstraints Editor" of xilinx Foundation F3.1i.

Site Home Archive Home FAQ Home How to search the Archive How to Navigate the Archive
Compare FPGA features and resources

Authors:A B C D E F G H I J K L M N O P Q R S T U V W X Y Z

Custom Search