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Hi: I have a XESS v.1.3 board. I am using webpack 4.1 to develop my projects. I am trying to add a verilog source code to a schematic symbol. I have made what the webpack 4.1 tutorial says but i cannot include it on the symbol library. Please help me Thanks, Yoram RovnerArticle: 40101
This is a multi-part message in MIME format. --------------95CE9D25314ECCF50DBFA838 Content-Type: multipart/alternative; boundary="------------3B7F4DD2DACA0E3C85967EF6" --------------3B7F4DD2DACA0E3C85967EF6 Content-Type: text/plain; charset=us-ascii Content-Transfer-Encoding: 7bit You may also want to check that the STARTUPCLK is set to JTAGCLK. You do not need to have the design with the BSCAN macro. This is also irrelevant as to the Mode pins. Dave Xilinx FAE from Insight SANKET wrote: > Hi Kim, > > Though very elementary---please check the "Properties" in " Generate > Programming File" in "Process" window.Here in the "Startup Options" > please check the "Drive DONE pin high". > > All the above,assuming you are using 4.1i ISE or Alliance. > > Regards, > SANKET. > > derive@hotmail.com (Mik Kim) wrote in message news:<a35ed87e.0202251556.784566b3@posting.google.com>... > > Hello, > > > > I'm trying to use Impact to download the bit file to Spartan 2E 100 > > PQ208. I know the JTAG hardware (cable, parallel port, PC) are ok > > since I am able to do it for Spartan XL. When I try it with Spartan > > 2E, it tries to download it, but consistently fails with "done pin did > > not go high" error. When I check the CCLK for SPROM, it is continually > > toggling. > > > > Spartan XL requires the FPGA configured through PROM (or otherwise) > > with BSCAN before the JTAG download would work. For Spartan 2, the > > Xilinx note states > > > > "Virtex and Spartan-II Boundary Scan Code > > NOTE: Basic boundary scan operations are always available in these > > devices. > > BSCAN_VIRTEX/BSCAN_SPARTAN2 is connected to internal logic only." > > > > http://support.xilinx.com/xlnx/xil_ans_display.jsp?iLanguageID=1&iCountryID=1&getPagePath=2805 > > > > But is this true? Do I need to configure the FPGA with BSCAN before > > downloading the bit file to FPGA?Article: 40102
Hi!
I want to make a BDM interface cable for CPU32 (ICD) and I found a
schematic with GAL16V8. I have also a OPAL file for this GAL.
How can I convert this .opl file to standard JEDEC file (I have
LabTool-48)?
The file:
[ilko@mbox]$ cat icd.opl
begin header
end header
begin definition
device GAL16V8;
ues 0000000000000000;
inputs
DSI=2,DSCLK=3,BREAK=4,RESET=5,
OE=6,M_FREEZE=7,M_DSO=8,SW=9,BERR=11;
outputs (com)
M_BERR=19,M_DSCLK=18,DSO=16,FREEZE=14,MAGIC=12;
feedback (com)
M_DSI=17,M_RESET=15,FF_BREAK=13;
end definition
begin equations
M_DSI = DSI;
M_DSI.oe = M_FREEZE & OE;
M_DSCLK = DSCLK & FF_BREAK & M_RESET;
FF_BREAK = BREAK | ( FF_BREAK & ( M_FREEZE | M_DSI ) );
M_RESET = RESET;
M_RESET.oe = /RESET;
M_BERR = /BERR;
M_BERR.oe = BERR;
FREEZE = M_FREEZE;
DSO = M_DSO;
MAGIC = 0;
end equations
Article: 40103Hi, anybody here knows where I could get the vhdl code for a SCSI controller ? Any links to similar projects ? cheers & thanks a lot.Article: 40104
Leon Qin wrote: > ZhengLin <zdzlin@163.com> wrote in message news:<ee74e16.10@WebX.sUN8CHnE>... > > Actel's FPGA can be programed only once, or it's prom can only be programed only once, but Xilinx's new part, such as spartan 2, can use a flash to program the fpga, if you don't have much experience in fpga design, I support you'd better not use actel's device for your first design! > > Actel's ProAsic And ProAsicPlus fpga can be programed many times! I have a few questions regarding this, if anyone can help.... Can it be done using a JTAG or download cable? - All I've seen is the method using a silicon sculptor, although I don't know what this is! Can use your own software, or is its just their own? NB these questions also relate to Quicklogic's pASICs too. Thanks for any response. Andy MainArticle: 40105
I am interfacing a 256MB SDRAM to a Spartan2. 1) As I don't know yet at which frequency my RAM controller will run on the FPGA, I am wondering if I can link directly the clk input to a FPGA I/O pin. I don't expect this frequency to be over 66ish Mhz. 2) Do I need to use the Board Level Deskew method described on Xilinx web site(XAPP174) ? I have only one RAM chip which should be close to the FPGA. 3) By the way, what means on the RAM spec that some supply pins (VddQ and VssQ for this Micron chip) are "isolated DQ power (or gnd) to the die ..." Shall I put some capacitors there? Regards, StephaneArticle: 40106
A small problem report for the benefit of other RPM floorplanners moving to
Virtex-II.
I set out to implement an 8Rx1C of CLBs 32x32 SP SRAM RPM out of RAM32X1Ss
and got derailed, despite previous successes doing the same thing with
XC4000 RAM32X1's and Virtex RAM32X1Ss.
To match the pitch of an adjacent adder RPM, I placed ram.{r0, r1 ,r2, ...,
r31} at RLOCs {X0Y0, X1Y0, X0Y1, ..., X1Y15}. This failed in PAR. From my
problem report:
>Problem Description:
>---------------------------------------
>I am designing a speed and area optimized datapath, using RPMs. I am
>trying to build a dense array of RAM32X1S slices. The software is
>failing to route the A4 signal internal to RAM32X1S (e.g. which
>connects the slice's BXOUT port to its SLICEWE0 port) whenever I place
>a RAM32X1S instance at any SLICE_XxYy where x is odd! I get the error:
>
>WARNING:Route:47 - The signal "ram/A4'" is not completely routed.
>
As I narrowed my test case down, I found 4.1i failed to PAR a design with
even a single RAM32X1S placed at an odd X slice, e.g. SLICE_X5Y4.
After a perfectly satisfactory back and forth with Xilinx tech support, I
have learned/confirmed that:
1. due to not unreasonable CLB routing limitations, while the Virtex-II
hardware can support a RAM32X4S in a CLB, it cannot support four independent
RAM32X1Ss in a CLB, and
2. if you attempt to RLOC four RAM32X1Ss into a single CLB, and they have
IDENTICAL ADDRESS AND CONTROL SIGNALS, (e.g. 100% equivalent to a RAM32X4S),
4.1i PAR FAILS even though the hardware (apparently) can support this
configuration.
One workaround I found was to build the RPM out of 16 RAM32X2Ss at X0Y0,
X0Y1, ..., X0Y15. RAM32X2Ss seem to obey RLOC constraints. Good.
It is interesting to note that even with the (wonderful -- thank you Xilinx,
thank you) XxYy slice addressing in Virtex-II, certain primitives (like
RAM32s) cannot fall on arbitrary x coordinates -- only even ones.
*** It would be nice if the documentation for built-up primitives like
RAM32X2S, etc. documented both the layout pitch of the primitive (in this
case, slices X0Y0 and X1Y0) and placement restrictions (in this case, x not
odd). ***
Jan Gray, Gray Research LLC
Article: 40107Ilko Iliev wrote: > > Hi! > I want to make a BDM interface cable for CPU32 (ICD) and I found a > schematic with GAL16V8. I have also a OPAL file for this GAL. > How can I convert this .opl file to standard JEDEC file (I have > LabTool-48)? > > The file: > [ilko@mbox]$ cat icd.opl > begin header > > end header > > begin definition > device GAL16V8; > ues 0000000000000000; > inputs > DSI=2,DSCLK=3,BREAK=4,RESET=5, > OE=6,M_FREEZE=7,M_DSO=8,SW=9,BERR=11; > outputs (com) > M_BERR=19,M_DSCLK=18,DSO=16,FREEZE=14,MAGIC=12; > feedback (com) > M_DSI=17,M_RESET=15,FF_BREAK=13; > end definition > > begin equations > M_DSI = DSI; > M_DSI.oe = M_FREEZE & OE; > > M_DSCLK = DSCLK & FF_BREAK & M_RESET; > > FF_BREAK = BREAK | ( FF_BREAK & ( M_FREEZE | M_DSI ) ); > > M_RESET = RESET; > M_RESET.oe = /RESET; > > M_BERR = /BERR; > M_BERR.oe = BERR; > > FREEZE = M_FREEZE; > > DSO = M_DSO; > > MAGIC = 0; > > end equations 1) Download Atmel WinCUPL 2) Recode the OPAL to CUPL, thus, and paste into a example CUPL header PIN 1 = DSI; PIN 2 = DSCLK; PIN 19 = M_BERR; FF_BREAK = BREAK # ( FF_BREAK & ( M_FREEZE # M_DSI ) ); M_RESET.oe = !RESET; 3) Create test vectors in cupl, to confirm logic operation 4) Compile, Pgm and Vector test, an ATF16V8BQL -jgArticle: 40108
Off the top of my head, 2 options... 1) You can invert it with one pass through your part then bring it back in and make your tools happy. OR 2) Use synchronous reset scheme, then the sense of the reset does not matter, its just combinationally combined and brought in the D pin of your flop. Regards > > Hi, > > What to do when I have negative reset (as usual with uP) > and I connect reset signal to fpga, but internal ffs wants to > get positive reset (f.e. MAX3000). When I place inverter > and all ffs are feed from inverted signal I got messages > 'non global signal usage may result'. > > jerryArticle: 40109
I have given up trying to get hold of it. I am now hooked on NIOS ver 2.0. Excellent IP. Victor "emanuel stiebler" <emu@ecubics.com> wrote in message news:3C7BC3B1.F2F45A81@ecubics.com... > Hi, > anybody here is using it ? Care to comment ? > > ThanksArticle: 40110
"Peter Alfke" <palfke@earthlink.net> schrieb im Newsbeitrag news:3C7C3423.F9B7325B@earthlink.net... > Xilinx is shipping today - and has been shipping for many months - FPGAs with > such a memory capacity. The Virtex-II family started shipping more than a > year ago. > Let's keep this newsgroup clean, without confusing anybody's future plans > with reality. Otherwise we get into arguments like: "My dream is much better > than your dream". And that serves nobody. ;-)))))))))) Also, I dont think it is commercial sensefull, to "waste" such a big FPGA as as ROM. -- MfG FalkArticle: 40111
Does anyone have QL32013-1PL83C parts they would like to sell? I am in 'crunch mode' and the delivery time is > 3 weeks. Thanks, Warren Wisnewski waw@excaliburs.comArticle: 40112
You may also be interested in checking out the Forums that Xilinx runs. You can find them at http://support.xilinx.com and then by clicking on the 'Forums' link. There's even a link to this very NG. -HobsonArticle: 40113
Victor Schutte wrote: > > I have given up trying to get hold of it. Care to elaborate a little further ? > I am now hooked on NIOS ver 2.0. > Excellent IP. I'll check ;-) cheers & thanksArticle: 40114
We have an upcoming design that will need to support LVDS point-to-point and point-to-multipoint. So we would like to have the programmable LVDS terminations in the FPGA. So far, the only device currently shipping that I have seen this in is the Orca Series 4. Any other devices support this? Xilinx doesn't seem to. Altera will with the Stratix series, but that may be a while. Thanks for any information, Brady Gaughan Airnet CommunicationsArticle: 40115
Steve, Clocks up to 167 MHz (333 Mb/s DDR) are do-able without too much trouble, although Signal Integrity is a challenge with anyone's chip running this fast using HSTL. (Bypassing, cross-talk, wire delays, timings, etc). Beyond 167 MHz, things get more difficult, and a little over 200 MHz, the HSTL standard runs out of gas. For over 200 MHz, LVDS is required in Virtex II (differential standard). Some people have generated 250 MHz single ended clocks using LVDCI 50 ohms to drive an HSTL input with sufficient margins. There are a number of customers pushing 180 MHz, but the SI requirements are pretty tough, and everything must be simulated before committing to a pcb. Actually, I would strongly encourage all designs to have their SI checked before going to a pcb.... Austin Steve Holroyd wrote: > I've pretty much came to the decision to use the Virtex-II device. > The DCI feature means I don't need thousands of series resistors > everywhere to guarantee timing (plus it has a lot more RAM). > > The HSTL I/O standard appears to be the fastest (from using the > Virtex-II ibis model). Anybody used/verified this ibis model? Any > advice? I've noticed some of these new fast (300MHz+) DDR/QDR SRAMs > have HSTL I/O levels. > > Thanks, > Steve > > rickman <spamgoeshere4@yahoo.com> wrote in message news:<3C6F58FB.1E11DA9B@yahoo.com>... > > I see that this question has met with no reply after two weeks. I guess > > that is the answer... > > > > > > > > Russell Shaw wrote: > > > > > > Guy Schlacter wrote: > > > > > > > > QuartusII v2.0 just released Friday and has been producing very good > > > > results for both this new family and ApexII. > > > > > > When is Quartus web edition going to include Acex 1k devices? > > > > > > > As far as GATE COUNTING, every vendor and family uses differnet > > > > nomenclature. For the user, you are best off descregarding gate counts > > > > and comparing > > > > 4input LUTs > > > > Available Memory counts > > > > Other dedicated Resources Multipliers etc. > > > > > > > > Best of Luck, > > > > Guy Schlacter > > > > Altera Corp. > > > > > > > > "Steve Holroyd" <spholroyd@iee.org> wrote in message > > > > news:b623f4cf.0201111039.2a16155@posting.google.com... > > > > > > > > > I am currently task of recommending the largest, fastest and most > > > > > memory FPGA that's readily available the first half of this year for a > > > > > FPGA Array Card. > > > > > > > > > > The choices have been narrowed down to two families Altera's APEX-II > > > > > (EP2A70) and XILINX Virtex-II (XC2V6000). > > > > > > > > > > Which can operate at the highest speed? > > > > > > > > > > Steve > > > > > > > > -- > > > > Posted via Mailgate.ORG Server - http://www.Mailgate.ORG > > > > > > -- > > > ___ ___ > > > / /\ / /\ > > > / /__\ Russell Shaw, B.Eng, M.Eng(Research) / /\/\ > > > /__/ / Victoria, Australia, Down-Under /__/\/\/ > > > \ \ / \ \/\/ > > > \__\/ \__\/ > > > > -- > > > > Rick "rickman" Collins > > > > rick.collins@XYarius.com > > Ignore the reply address. To email me use the above address with the XY > > removed. > > > > Arius - A Signal Processing Solutions Company > > Specializing in DSP and FPGA design URL http://www.arius.com > > 4 King Ave 301-682-7772 Voice > > Frederick, MD 21701-3110 301-682-7666 FAXArticle: 40116
Take any file and encrypt it. The file is the input and the encrypted file is the output. By his theory he can build a truth table for that. Bet him he can't do it and put me down for $5. If he can then he'll be very rich!!! Steve "Madhu" <pp_madhavi@yahoo.com> wrote in message news:c074a7b1c70d79729ac318bbc52aa174.67011@mygate.mailgate.org... > Hi all, > here is an argument with one of my friend who is a mechanical engineer > and writing S/W. > He argues that if the input and output waveforms are given he can > write a tool which generates a digital circuit for those inputs and > outputs. He knows about truth tables and gates. > He is not convinced when I told all digital circuits are not just > combinational. > Then I asked him whether he can generate a C program if the inputs and > outputs are given. But he says that it is obsurd that I am comparing a > language with digital design. > Still he believes in what he says. > So friends, please do respond. > Thank you > Madhu > > > -- > Posted via Mailgate.ORG Server - http://www.Mailgate.ORG >Article: 40118
I can help elaborate on this one. I've seen both kits, and have been won over by Nios myself. A coworker of mine ordered his MicroBlaze kit last year and it took over two months to show up. While I found that the Insight development board was a pretty good softcore CPU development platform (as is the Nios dev board), the MicroBlaze product itself is a bit (to say the least) lacking. After receiving the kit and opening it up we found no MicroBlaze CD! It showed up in a separate mailing on a generic CD-R, as if it were burned on some engineer's cubicle CD burner. These tidbits aside, the MicroBlaze design flow is entirely script based - without any GUI. Nios is also script based, but it is all abstracted in their system builder software. In order to get a basic m-blaze system with CPU and a couple peripherals (UART, general purpose IO), a couple of pages of typing are required to instantiate everything! One goof up and no system for you! The Nios kit GUI lets you make an equivalent system in seconds. -- Jesse Kempa emanuel stiebler <emu@ecubics.com> wrote in message news:<3C7D300C.3B5534A1@ecubics.com>... > Victor Schutte wrote: > > > > I have given up trying to get hold of it. > > Care to elaborate a little further ? > > > I am now hooked on NIOS ver 2.0. > > Excellent IP. > > I'll check ;-) > > cheers & thanksArticle: 40120
read below... Stéphane Guyetant <sguyetanREMOVE@irisa.fr> wrote in message news:<3C7D23B3.9D2FDF38@irisa.fr>... > I am interfacing a 256MB SDRAM to a Spartan2. > > 1) > As I don't know yet at which frequency my RAM controller will run on the > FPGA, I am wondering if I can link directly the clk input to a FPGA I/O > pin. > I don't expect this frequency to be over 66ish Mhz. No, this isn't the best way to do it, regardless of frequency (look under hold violations). And you should be so lucky to get a 66MHz auto P&R sdram controller. > 2) > Do I need to use the Board Level Deskew method described on Xilinx web > site(XAPP174) ? > I have only one RAM chip which should be close to the FPGA. Yes, this is the way to do it (if I'm thinking about the same XAPP.) The issue is that the clock distribution network on the die puts a large and variable delay between the clock input pin on the Spartan and the flop clock port. You need to deskew to match the board clock edges. > 3) > By the way, what means on the RAM spec that some supply pins (VddQ and > VssQ for this Micron chip) are "isolated DQ power (or gnd) to the die > ..." > Shall I put some capacitors there? I don't have the spec in front of me, but I would venture to guess that these are the supply pins for those beefy data line drivers. They are seperate on the DIMM because they don't want to upset the rest of the sdram die when all those outputs start pouring electrons into your bus capacitance all at once. And yes, I would bypass these pins and them bring them directly to your power plane. > > Regards, > Stephane Regards!Article: 40121
Falk Brunner <Falk.Brunner@gmx.de> wrote in message news:a5jfji$831h0$1@ID-84877.news.dfncis.de... > "Peter Alfke" <palfke@earthlink.net> schrieb im Newsbeitrag > news:3C7C3423.F9B7325B@earthlink.net... > > > Xilinx is shipping today - and has been shipping for many months - FPGAs > with > > such a memory capacity. The Virtex-II family started shipping more than a > > year ago. > > Let's keep this newsgroup clean, without confusing anybody's future plans > > with reality. Otherwise we get into arguments like: "My dream is much > better > > than your dream". And that serves nobody. > > ;-)))))))))) > > Also, I dont think it is commercial sensefull, to "waste" such a big FPGA as > as ROM. > > -- > MfG > Falk Falk, Peter, Look, just because it isn't easy to implement something in a Xilinx part doesn't mean that it's not a valid solution. There's a hint of some uneven treatment going on when suggesting that someone looking at Stratix is dreaming while comments about an Virtex device with 3.125 Gbps HSSI are dropped all over this newsgroup without any questions being raised. The Stratix design tools are here (Synplicity, Leonardo Spectrum, Quartus II, Modelsim, App Notes, White papers, etc.). The devices will be here before most design cycles starting today will require parts. The 300 MHz, 2Mb ROM fits easily into a medium sized Stratix device. What, exactly, was wrong with my suggestion that Antonio take a look at the part? He's looking for a solution - I offered him one that may or may not work for him (that's his decision to make) - and I get jumped on by the two of you. I'll say this again: Just because it isn't easy to implement something like this in a Xilinx part doesn't mean it's not a valid solution. There's more than one programmable logic vendor out there (and more than just two, too) despite what you might think from reading this group. -Pete-Article: 40123
Peter Ormsby wrote: > Falk, Peter, > > Look, just because it isn't easy to implement something in a Xilinx part > doesn't mean that it's not a valid solution. There's a hint of some uneven > treatment going on when suggesting that someone looking at Stratix is > dreaming while comments about an Virtex device with 3.125 Gbps HSSI are > dropped all over this newsgroup without any questions being raised. Hold it. I ( we ) have been extremely quiet about that exciting new Xilinx family. Altera prefers to pre-announce their upcoming family. Different marketing style... But allow me to point out that the pre-announcement of Excalibur and its seriously delayed shipment did not exactly enhance Altera's credibility. People have memory. More fundamentally: I don't think the obviously ridiculous 2 Megabit ROM requirement originally posted in this newsgroup is a good cause for ventilating our sibling rivalry. Let's fight over something better! We all can dream, but I will continue to recommend solutions that the user can get his/her hands on. Call that conservative or realistic, that's fine with me. Peter Alfke, Xilinx ApplicationsArticle: 40124
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