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"Paul" <dorron@hotmail.com> schrieb im Newsbeitrag news:2842f801.0202180615.f8c8a3b@posting.google.com... > Now I know which signal is failing, but I can not constraint it ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ > because it is an internal path (not an I/O pin) and I dont know what > is the name of this signal after Synthesis so I can not constrain it. ^^^^^^^^^^^^^^^^^^ ????? This doesnt make sense. How do you know which signal causes the trouble?? -- MfG FalkArticle: 39751
hi, Do Altera FPGAs (Apex 20KE) come with specifically provided multipliers or do the multipliers in your design need to be considered as part of the total gate count ? Thanks, PrashantArticle: 39752
This is a multi-part message in MIME format. --------------809BD4D65C39668992C2B7CD Content-Type: text/plain; charset=us-ascii Content-Transfer-Encoding: 7bit Paul, Firstly, constrain the clocks in the design. Then the IO timing to control your tCO and tSU requirements. After that control the clock to clock timing (if you have multiple clocks). If your design is synchronous then no problems - if not then watch out! A higher effort does not mean that it will give you better results if you do no timing constraining, as the PAR engine knows nothing of your design - it does default enumeration and in which case may optimise a path that is not critical to your design. In short - always use timing constraints - even if they are slow ones, as this will result in shorter compile times! Dave Paul wrote: > Hy!!! > > I'm developing some design in a Xiling VirtexE 100, until now > everything used to work O.K., but since the design is becomming bigger > (now i'm using something like 90 % of the slices) I am having some > problems with the place & route tool. Things that already worked stop > working. With the same synthesis result and diferent PAR strategies > sometimes I get it to work. It is very strange that higher effort not > always means better results. Sometimes it worked with medium effort > PAR and failed by highest effort :-( !?!? > > Now I know which signal is failing, but I can not constraint it > because it is an internal path (not an I/O pin) and I dont know what > is the name of this signal after Synthesis so I can not constrain it. > Could someone help me? > > Thanks in advance, > Paul.Article: 39753
Ray Andraka wrote: > > Exactly. In fact, all the LFSR is is a special case of the CRC hardware. I did't want to > confuse the issue, but as you say, you can create a parallel version of the LFST that appears at > the outputs to advance N clocks in a single clock. > I'm wondering if it in a VirtexII would makes sense to use a multiplier, AFIAR a normal way to generate random numbers in SW is something like x[n+1] = (x[n]*a + b) % c -Lasse > jrc wrote: > > > It is pretty easy to contruct a state-machine to mimic the effects of > > a LFSR shift register that has been clocked an arbitrary number of > > times. To use your example the normal logic for X^3+X^2+1 using four > > flip-flops is: > > > > ff0=ff3^ff2^1 (xnor the last two flip-flops in the shift register) > > ff1=ff0 (shift) > > ff2=ff1 (shift) > > ff3=ff2 (shift) > > > > For each clock, the following design will produce the same four bit > > sequence produced by clocking the orignal design four times: > > > > ff0=ff3^ff2^ff0 (three term xor) > > ff1=ff1^ff0^1 (xnor) > > ff2=ff2^ff1^1 (xnor) > > ff3=ff3^ff2^1 (xnor) > > > > So the bit sequence for ff0 the upper design is: > > > > 0111011001010000111... > > > > The bit sequence for the four flip-flops on second design is: > > > > 3210 > > ---- > > 0111 > > 0110 > > 0101 > > 0000 > > 1110 > > ... > > > > I always called this generating pseudorandom in parallel. It is used a > > lot in communications work. Once you get the knack you can generate > > any sequence in any width. If you add flip-flops you can actually > > generate this sequence 8 bits at a time or even wider. > > > > JRC > > > > Ray Andraka <ray@andraka.com> wrote in message news:<3C62A21F.C8BFFA23@andraka.com>... > > > No. The neighboring bits, when taken a byte at a time from an LFSR are time shifted copies > > > of previous bits. If you take more than 1 bit per clock from an LFSR, you lose the uniform > > > white properties. Consider the 4 bit LFSR X^3+X^2+1: > > > > > > 0000 > > > 0001 > > > 0011 > > > 0111 > > > 1110 > > > 1101 > > > 1011 > > > 0110 > > > 1100 > > > 1001 > > > 0010 > > > 0101 > > > 1010 > > > 0100 > > > 1000 > > > 0000 > > > > > > Note that only the right most bit is random, the other bits are the same as the rightmost > > > but delayed by 1,2 and 3 clocks. If you use more than one bit per clock from an LFSR, you > > > wind up with a correlation that colors the output and destroys the uniform random > > > properties. The bottom line is that an LFSR at 100MHz produces a random BIT stream at 100 > > > MHz, not a byte stream. To get a random byte stream, you need to clock the LFSR 8 times > > > between samples so as to get new bit values (uncorrelated to any bits in previous sample) > > > in all 8 bits, which gives you a random byte stream of 100/8= 12.5 MHz. > > > > > > vt313@comsys.ntu-kpi.kiev.ua wrote: > > > > > > > In the LSFR bitstream the bytes of neighboring bits, > > > > considered as signed vectors, are practically > > > > uncorrelated, and belong to the interval (-1.0 : 1.0). > > > > Therefore LSFR generator at 100 MHz > > > > provides the byte stream at 100 MHz. > > > > > > > > If you add couples of neigboring > > > > sampling bytes from LSFR, > > > > then you get the approximation > > > > of the "triangle" distribution. > > > > > > > > If you want the Gaussian distribution, > > > > then you would add n>10 neigboring > > > > sampling bytes from LSFR, > > > > and get the rather exact approximation > > > > of the Gaussian distribution. > > > > > > > > Anatoli S. > > > > > > -- > > > --Ray Andraka, P.E. > > > President, the Andraka Consulting Group, Inc. > > > 401/884-7930 Fax 401/884-7950 > > > email ray@andraka.com > > > http://www.andraka.com > > > > > > "They that give up essential liberty to obtain a little > > > temporary safety deserve neither liberty nor safety." > > > -Benjamin Franklin, 1759 > > -- > --Ray Andraka, P.E. > President, the Andraka Consulting Group, Inc. > 401/884-7930 Fax 401/884-7950 > email ray@andraka.com > http://www.andraka.com > > "They that give up essential liberty to obtain a little > temporary safety deserve neither liberty nor safety." > -Benjamin Franklin, 1759 -- ---------------------------- - Lasse Langwadt Christensen - Aalborg - DanmarkArticle: 39754
Anyone know where the XDL documentation has got to ? In my 2.1i installation it was in the `userware' directory but this doesn't seem to exist for 3.3i & 4.1i.Article: 39755
Hi, Last time I purchased a XC9572 CPLD and an SC2S100 Spartan-II chip. I applied a 5V to it's VCCO. I want to know how to decide whether the chip has been spoiled. Thanks.Article: 39756
Hello, Mr. sharat babu thanks for your response. I appreciate your support, but I don't see how this can be applied using Xilinx System Generator. Usually, I declare a port using the MatlabIO module which is supplied with the System Generator toolbox. There I can select only between signed and unsigned data types; obviously they don't know a high-Z state. If your proposal really works with SystemGenerator, could you please help me a little further maybe attach a simulink.mdl which demonstrates it? Any help appreciated... Bernhard Holzmayer "sharat babu" <asicbaba@rediffmail.com> schrieb im Newsbeitrag news:795784f8.0202162102.2482e1c2@posting.google.com... | hello Mr.Bernhard Holzmayer | | the solution for your problem is declare the port as | std_logic__vectorthen you can directly asssign it as "zzzzzz". | | sharat babu | | "Bernhard Holzmayer" <Holzmayer.Bernhard@foerstergroup.de> wrote in message news:<a4fu7f$1f2fr7$1@ID-131763.news.dfncis.de>... | > Hello. | > | > While doing my first steps with Xilinx System Generator (V2.1), I | > hit a | > (maybe trivial) problem: | > | > I have a port / pin, which is both, input and output. | > It must be written depending on a flag's state, being high-Z | > otherwise. | > In VHDL it would be something like the following: | > ... | > ...process(flag, data) | > begin | > if (flag = '1') then | > port <= "ZZZZZZZZ"; | > else | > port <= data; | > end if; | > end process; | > | > Help me: how can I set this port into the high-Z state using SysGen? | > Does anyone know this ??? | > | > BernhardArticle: 39757
Hi, I was wondering if you managed to resolve your problem with the halfband filter? best regards Chris Yury wrote: > newman5382@aol.com (newman) wrote in message news:<e6038423.0201180501.c52e394@posting.google.com>... > > yuryws@optonline.com (Yury) wrote in message news:<fb9fd058.0201172014.12b797fa@posting.google.com>... > > > Implemented 1/2 Band 51-tap FIR using Coregen + Foundation. > > > Pre-synthesis simulation looks excellent, however when the filter is > > > loaded into Spartan-II the output looks like complete random junk. All > > > timing is met. > > > > > > Does anyone have a similar experience or an idea for a potential > > > problem area? > > > > > > Thanks. > > > > I have not used this Coregen IP, but you mentioned that the > > Pre-synthesis simulations look excellent. How about post PAR > > simulations? One can also do an inbetween post PAR simulation without > > the SDF if need be. The reason I mention this is maybe the > > constraints need a little bit more work. > > > > Are you sure the digital input data is frequency limited to within > > your > > digital filter's specifications? > > > > Are you using DLL's?, they have min/max frequency and jitter > > specifications. > > > > Newman > > I stimulate the pre-synthesis design with a certain input data stream. > I use the same stream as an input to a tool called Elanix (used for > signal processing). The pre-synthesis output of Xilinx and the output > of Elanix agree clock for clock for 64K samples (which indicates to me > that the design is correct). I am starting to suspect the descrepancy > between the Coregen model of the FIR and its behavioral VHDL > description provided by the same Coregen. > I have to do the post routing functional and/or timing simulation, but > I have not gotten to it yet. > > DLLs are rock solid, their jitter is minimal (could not affetct the > spectrum). > > The frequency content of the input data is irrelevant, since I compare > the output of the Xilinx filter to that of an independent filter > simulator. Even if the data is out of band the output smaples still > should agree. > > Thanks -- Dr Chris Dick Xilinx DSP Group Manager DSP Chief Architect Xilinx Inc 2100 Logic Drive San Jose CA 95124 Phone: 408.879.5377 Fax: 408.626.6440 eFax: 508.355.7668Article: 39758
Hi, Is there anyone knows the maximum # of logic level for Xilinx FPGA? Because I remeber if the # of logic level is too large will affect the performance of the design.Article: 39759
Hi all,
depending on the mode pins, the cclk can be an input or an output.
What we like to do is the following:
1.) During normal startup, we select serial master mode
2.) During normal operation we have the possibility to update
the serial configuration eeprom through the atmel I2C like
serial interface. In other words, we download a new config
uration. It will take place on the next configuration cycle.
Question: In master serial mode cclk is an output. Can it made
an input by simple changing to slave serial mode on
the mode pins, without really starting a new confi-
guration??
When exactly changes the direction of the cclk pin?
best regards
markus
Article: 39760
Hello,
I try to use an Orca FPSC with an integrated PCI-Core (its an ASIC on the same chip as the FPGA area).
The functional design was made in scematic capture in Viewlogic's Viewdraw and the PCI-Core (that is
represented by a VHDL netlist) was included as a symbol. The next step was to create an EDIF netlist.
I want to use FPGA Express to synthesize the whole design with the PCI-Core. To check the
combining of the PCI-Core with a schematic, I just created one with an OR gate connected with the symbol
of the PCI-Core. After this Icreated an EDIF netlist from the schematic and added the netlist and the
VHDL netlist of the Core to a FPGA Express project.
First problem was a warning:
Warning: Cannot link cell 'OR3TP12_INTF/OR3TP12_CORE_INST' to its reference design 'or3tp12_core6_ts'. (FPGA-LINK-2)
I could prevent this warning by adding an architecture to the entity 'or3tp12_core6_ts'. After the design
was synthesized, I exported an EDIF netlist for the use in the Orca Foundry to place-and-route the design.
There an error occured called
ERROR - ngdbuild: logical root block 'NUR_CORE' with type 'NUR_CORE' is unexpanded
Next, I had a look at the exported netlist and found it nearly empty.
I don't have any explanation for this. I hope somebody can give me a hint.
Best Regards
Carsten
Edif netlist of the schematic design:
(edif nur_core
(edifVersion 2 0 0)
(edifLevel 0)
(keywordMap (keywordLevel 0))
(status
(written
(timeStamp 2002 2 19 10 28 25)
(program "VIEWlogic's edifneto" (version "7.5.p (Nov 4 1999)"))))
(library NUR_CORE
(edifLevel 0)
(technology (numberDefinition (scale 1 (E 1 -12) (unit CAPACITANCE))))
(cell (rename ORCA_OR2_1 "OR2")
(cellType GENERIC)
(status (written
(timeStamp 2001 1 25 4 46 46)))
(userData VL_PLATFORM_CODE (string "K 310014272500 OR2")
(owner "Viewlogic_Systems"))
(userData LIBNAME
(string "ORCA")
(owner "Viewlogic_Systems"))
(view view_1
(viewType NETLIST)
(interface
(port A
(direction INPUT))
(port B
(direction INPUT))
(port Z
(direction OUTPUT))
(property (rename &_DEL_A_Z_F_2 "@DEL_A_Z_F") (string "100PS") (owner "Viewlogic_Systems"))
(property (rename &_DEL_A_Z_R_3 "@DEL_A_Z_R") (string "100PS") (owner "Viewlogic_Systems"))
(property (rename &_DEL_B_Z_F_4 "@DEL_B_Z_F") (string "100PS") (owner "Viewlogic_Systems"))
(property (rename &_DEL_B_Z_R_5 "@DEL_B_Z_R") (string "100PS") (owner "Viewlogic_Systems"))
(property LEVEL (string "ORCA") (owner "Viewlogic_Systems")))
))
(cell OR3TP12_INTF
(cellType GENERIC)
(userData VL_PLATFORM_CODE (string "K 184991017000 OR3TP12_INTF")
(owner "Viewlogic_Systems"))
(view view_1
(viewType NETLIST)
(interface
(port CLK
(property FPSC_PAD (string "%34%TRUE%34%") (owner "Viewlogic_Systems"))
(direction INPUT)
(property VHDL_TYPE (string "STD_LOGIC") (owner "Viewlogic_Systems")))
(port RSTN
(property FPSC_PAD (string "%34%TRUE%34%") (owner "Viewlogic_Systems"))
(direction INPUT)
(property VHDL_TYPE (string "STD_LOGIC") (owner "Viewlogic_Systems")))
(port (array (rename AD_63_0__6 "AD[63:0]") 64 )
(property FPSC_PAD (string "%34%TRUE%34%") (owner "Viewlogic_Systems"))
(direction INOUT)
(property VHDL_TYPE (string "STD_LOGIC_VECTOR") (owner "Viewlogic_Systems")))
(port (array (rename C_BEN_7_0__7 "C_BEN[7:0]") 8 )
(property FPSC_PAD (string "%34%TRUE%34%") (owner "Viewlogic_Systems"))
(direction INOUT)
(property VHDL_TYPE (string "STD_LOGIC_VECTOR") (owner "Viewlogic_Systems")))
(port PAR
(property FPSC_PAD (string "%34%TRUE%34%") (owner "Viewlogic_Systems"))
(direction INOUT)
(property VHDL_TYPE (string "STD_LOGIC") (owner "Viewlogic_Systems")))
(port FRAMEN
(property FPSC_PAD (string "%34%TRUE%34%") (owner "Viewlogic_Systems"))
(direction INOUT)
(property VHDL_TYPE (string "STD_LOGIC") (owner "Viewlogic_Systems")))
(port IRDYN
(property FPSC_PAD (string "%34%TRUE%34%") (owner "Viewlogic_Systems"))
(direction INOUT)
(property VHDL_TYPE (string "STD_LOGIC") (owner "Viewlogic_Systems")))
(port TRDYN
(property FPSC_PAD (string "%34%TRUE%34%") (owner "Viewlogic_Systems"))
(direction INOUT)
(property VHDL_TYPE (string "STD_LOGIC") (owner "Viewlogic_Systems")))
(port STOPN
(property FPSC_PAD (string "%34%TRUE%34%") (owner "Viewlogic_Systems"))
(direction INOUT)
(property VHDL_TYPE (string "STD_LOGIC") (owner "Viewlogic_Systems")))
(port IDSEL
(property FPSC_PAD (string "%34%TRUE%34%") (owner "Viewlogic_Systems"))
(direction INPUT)
(property VHDL_TYPE (string "STD_LOGIC") (owner "Viewlogic_Systems")))
(port DEVSELN
(property FPSC_PAD (string "%34%TRUE%34%") (owner "Viewlogic_Systems"))
(direction INOUT)
(property VHDL_TYPE (string "STD_LOGIC") (owner "Viewlogic_Systems")))
(port REQN
(property FPSC_PAD (string "%34%TRUE%34%") (owner "Viewlogic_Systems"))
(direction OUTPUT)
(property VHDL_TYPE (string "STD_LOGIC") (owner "Viewlogic_Systems")))
(port GNTN
(property FPSC_PAD (string "%34%TRUE%34%") (owner "Viewlogic_Systems"))
(direction INPUT)
(property VHDL_TYPE (string "STD_LOGIC") (owner "Viewlogic_Systems")))
(port PERRN
(property FPSC_PAD (string "%34%TRUE%34%") (owner "Viewlogic_Systems"))
(direction INOUT)
(property VHDL_TYPE (string "STD_LOGIC") (owner "Viewlogic_Systems")))
(port SERRN
(property FPSC_PAD (string "%34%TRUE%34%") (owner "Viewlogic_Systems"))
(direction OUTPUT)
(property VHDL_TYPE (string "STD_LOGIC") (owner "Viewlogic_Systems")))
(port INTAN
(property FPSC_PAD (string "%34%TRUE%34%") (owner "Viewlogic_Systems"))
(direction OUTPUT)
(property VHDL_TYPE (string "STD_LOGIC") (owner "Viewlogic_Systems")))
(port REQ64N
(property FPSC_PAD (string "%34%TRUE%34%") (owner "Viewlogic_Systems"))
(direction INOUT)
(property VHDL_TYPE (string "STD_LOGIC") (owner "Viewlogic_Systems")))
(port ACK64N
(property FPSC_PAD (string "%34%TRUE%34%") (owner "Viewlogic_Systems"))
(direction INOUT)
(property VHDL_TYPE (string "STD_LOGIC") (owner "Viewlogic_Systems")))
(port PAR64
(property FPSC_PAD (string "%34%TRUE%34%") (owner "Viewlogic_Systems"))
(direction INOUT)
(property VHDL_TYPE (string "STD_LOGIC") (owner "Viewlogic_Systems")))
(port EJECTSW
(property FPSC_PAD (string "%34%TRUE%34%") (owner "Viewlogic_Systems"))
(direction INPUT)
(property VHDL_TYPE (string "STD_LOGIC") (owner "Viewlogic_Systems")))
(port ENUMN
(property FPSC_PAD (string "%34%TRUE%34%") (owner "Viewlogic_Systems"))
(direction OUTPUT)
(property VHDL_TYPE (string "STD_LOGIC") (owner "Viewlogic_Systems")))
(port LEDN
(property FPSC_PAD (string "%34%TRUE%34%") (owner "Viewlogic_Systems"))
(direction OUTPUT)
(property VHDL_TYPE (string "STD_LOGIC") (owner "Viewlogic_Systems")))
(port MAENN
(direction INPUT)
(property VHDL_TYPE (string "STD_LOGIC") (owner "Viewlogic_Systems")))
(port MA_FULLN
(direction OUTPUT)
(property VHDL_TYPE (string "STD_LOGIC") (owner "Viewlogic_Systems")))
(port MWDATAENN
(direction INPUT)
(property VHDL_TYPE (string "STD_LOGIC") (owner "Viewlogic_Systems")))
(port MW_AFULLN
(direction OUTPUT)
(property VHDL_TYPE (string "STD_LOGIC") (owner "Viewlogic_Systems")))
(port MW_FULLN
(direction OUTPUT)
(property VHDL_TYPE (string "STD_LOGIC") (owner "Viewlogic_Systems")))
(port MRDATAENN
(direction INPUT)
(property VHDL_TYPE (string "STD_LOGIC") (owner "Viewlogic_Systems")))
(port MR_AEMPTYN
(direction OUTPUT)
(property VHDL_TYPE (string "STD_LOGIC") (owner "Viewlogic_Systems")))
(port MR_EMPTYN
(direction OUTPUT)
(property VHDL_TYPE (string "STD_LOGIC") (owner "Viewlogic_Systems")))
(port FIFO_SEL
(direction INPUT)
(property VHDL_TYPE (string "STD_LOGIC") (owner "Viewlogic_Systems")))
(port TAENN
(direction INPUT)
(property VHDL_TYPE (string "STD_LOGIC") (owner "Viewlogic_Systems")))
(port TREQN
(direction OUTPUT)
(property VHDL_TYPE (string "STD_LOGIC") (owner "Viewlogic_Systems")))
(port TWDATAENN
(direction INPUT)
(property VHDL_TYPE (string "STD_LOGIC") (owner "Viewlogic_Systems")))
(port (array (rename DATATOFPGA_31_0__8 "DATATOFPGA[31:0]") 32 )
(direction OUTPUT)
(property VHDL_TYPE (string "STD_LOGIC_VECTOR") (owner "Viewlogic_Systems")))
(port DATATOFPGAX2
(direction OUTPUT)
(property VHDL_TYPE (string "STD_LOGIC") (owner "Viewlogic_Systems")))
(port DATATOFPGAX3
(direction OUTPUT)
(property VHDL_TYPE (string "STD_LOGIC") (owner "Viewlogic_Systems")))
(port DATATOFPGAX0
(direction OUTPUT)
(property VHDL_TYPE (string "STD_LOGIC") (owner "Viewlogic_Systems")))
(port DATATOFPGAX1
(direction OUTPUT)
(property VHDL_TYPE (string "STD_LOGIC") (owner "Viewlogic_Systems")))
(port (array (rename DATAFMFPGA_31_0__9 "DATAFMFPGA[31:0]") 32 )
(direction INPUT)
(property VHDL_TYPE (string "STD_LOGIC_VECTOR") (owner "Viewlogic_Systems")))
(port DATAFMFPGAX2
(direction INPUT)
(property VHDL_TYPE (string "STD_LOGIC") (owner "Viewlogic_Systems")))
(port DATAFMFPGAX3
(direction INPUT)
(property VHDL_TYPE (string "STD_LOGIC") (owner "Viewlogic_Systems")))
(port DATAFMFPGAX0
(direction INPUT)
(property VHDL_TYPE (string "STD_LOGIC") (owner "Viewlogic_Systems")))
(port DATAFMFPGAX1
(direction INPUT)
(property VHDL_TYPE (string "STD_LOGIC") (owner "Viewlogic_Systems")))
(port TW_AEMPTYN
(direction OUTPUT)
(property VHDL_TYPE (string "STD_LOGIC") (owner "Viewlogic_Systems")))
(port TW_EMPTYN
(direction OUTPUT)
(property VHDL_TYPE (string "STD_LOGIC") (owner "Viewlogic_Systems")))
(port TRDATAENN
(direction INPUT)
(property VHDL_TYPE (string "STD_LOGIC") (owner "Viewlogic_Systems")))
(port TR_AFULLN
(direction OUTPUT)
(property VHDL_TYPE (string "STD_LOGIC") (owner "Viewlogic_Systems")))
(port TR_FULLN
(direction OUTPUT)
(property VHDL_TYPE (string "STD_LOGIC") (owner "Viewlogic_Systems")))
(port TFIFOCLRN
(direction INPUT)
(property VHDL_TYPE (string "STD_LOGIC") (owner "Viewlogic_Systems")))
(port MFIFOCLRN
(direction INPUT)
(property VHDL_TYPE (string "STD_LOGIC") (owner "Viewlogic_Systems")))
(port TRPCIHOLD
(direction INPUT)
(property VHDL_TYPE (string "STD_LOGIC") (owner "Viewlogic_Systems")))
(port MWPCIHOLD
(direction INPUT)
(property VHDL_TYPE (string "STD_LOGIC") (owner "Viewlogic_Systems")))
(port TRBURSTPENDN
(direction INPUT)
(property VHDL_TYPE (string "STD_LOGIC") (owner "Viewlogic_Systems")))
(port DISCTIMEREXPN
(direction OUTPUT)
(property VHDL_TYPE (string "STD_LOGIC") (owner "Viewlogic_Systems")))
(port PCI_INTAN
(direction INPUT)
(property VHDL_TYPE (string "STD_LOGIC") (owner "Viewlogic_Systems")))
(port FPGA_MBUSYN
(direction INPUT)
(property VHDL_TYPE (string "STD_LOGIC") (owner "Viewlogic_Systems")))
(port FPGA_MSYSERROR
(direction OUTPUT)
(property VHDL_TYPE (string "STD_LOGIC") (owner "Viewlogic_Systems")))
(port FCLK1
(direction INPUT)
(property VHDL_TYPE (string "STD_LOGIC") (owner "Viewlogic_Systems")))
(port FCLK2
(direction INPUT)
(property VHDL_TYPE (string "STD_LOGIC") (owner "Viewlogic_Systems")))
(port PCICLK
(direction OUTPUT)
(property VHDL_TYPE (string "STD_LOGIC") (owner "Viewlogic_Systems")))
(port PCI_RSTN
(direction OUTPUT)
(property VHDL_TYPE (string "STD_LOGIC") (owner "Viewlogic_Systems")))
(port T_ABORT
(direction INPUT)
(property VHDL_TYPE (string "STD_LOGIC") (owner "Viewlogic_Systems")))
(port MR_STOPBURSTN
(direction INPUT)
(property VHDL_TYPE (string "STD_LOGIC") (owner "Viewlogic_Systems")))
(port T_RETRYN
(direction INPUT)
(property VHDL_TYPE (string "STD_LOGIC") (owner "Viewlogic_Systems")))
(port FPGA_SYSERROR
(direction INPUT)
(property VHDL_TYPE (string "STD_LOGIC") (owner "Viewlogic_Systems")))
(port M_READY
(direction OUTPUT)
(property VHDL_TYPE (string "STD_LOGIC") (owner "Viewlogic_Systems")))
(port T_READY
(direction OUTPUT)
(property VHDL_TYPE (string "STD_LOGIC") (owner "Viewlogic_Systems")))
(port PCI_CFG_STAT
(direction OUTPUT)
(property VHDL_TYPE (string "STD_LOGIC") (owner "Viewlogic_Systems")))
(port (array (rename TCMD_3_0__10 "TCMD[3:0]") 4 )
(direction OUTPUT)
(property VHDL_TYPE (string "STD_LOGIC_VECTOR") (owner "Viewlogic_Systems")))
(port (array (rename MSTATECNTR_3_0__11 "MSTATECNTR[3:0]") 4 )
(direction OUTPUT)
(property VHDL_TYPE (string "STD_LOGIC_VECTOR") (owner "Viewlogic_Systems")))
(port (array (rename TSTATECNTR_3_0__12 "TSTATECNTR[3:0]") 4 )
(direction OUTPUT)
(property VHDL_TYPE (string "STD_LOGIC_VECTOR") (owner "Viewlogic_Systems")))
(port (array (rename BAR_2_0__13 "BAR[2:0]") 3 )
(direction OUTPUT)
(property VHDL_TYPE (string "STD_LOGIC_VECTOR") (owner "Viewlogic_Systems")))
(port TWLASTCYCN
(direction OUTPUT)
(property VHDL_TYPE (string "STD_LOGIC") (owner "Viewlogic_Systems")))
(port TRLASTCYCN
(direction OUTPUT)
(property VHDL_TYPE (string "STD_LOGIC") (owner "Viewlogic_Systems")))
(port MRLASTCYCN
(direction OUTPUT)
(property VHDL_TYPE (string "STD_LOGIC") (owner "Viewlogic_Systems")))
(port PCI_64BIT
(direction OUTPUT)
(property VHDL_TYPE (string "STD_LOGIC") (owner "Viewlogic_Systems")))
(port DELTRN
(direction INPUT)
(property VHDL_TYPE (string "STD_LOGIC") (owner "Viewlogic_Systems")))
(port MWLASTCYCN
(direction INPUT)
(property VHDL_TYPE (string "STD_LOGIC") (owner "Viewlogic_Systems")))
(port TWBURSTPENDN
(direction INPUT)
(property VHDL_TYPE (string "STD_LOGIC") (owner "Viewlogic_Systems")))
(port CFGSHIFTENN
(direction INPUT)
(property VHDL_TYPE (string "STD_LOGIC") (owner "Viewlogic_Systems")))
(port PWRUPRST
(property FPSC_PAD (string "%34%TRUE%34%") (owner "Viewlogic_Systems"))
(direction INPUT)
(property VHDL_TYPE (string "STD_LOGIC") (owner "Viewlogic_Systems")))
(property ACCEL (string "VANTAGE") (owner "Viewlogic_Systems"))
(property VHDL (string "OR3TP12_INTF") (owner "Viewlogic_Systems"))
(property VHDLFILE (string "OR3TP12_INTF.VHD") (owner "Viewlogic_Systems"))
(property VHDL_IMPORT_IEEE (string "LIBRARY") (owner "Viewlogic_Systems"))
(property (rename VHDL_IMPORT_IEEE_STD_LOGIC_1164_14 "VHDL_IMPORT_IEEE$STD_LOGIC_1164") (string "PACKAGE") (owner "Viewlogic_Systems")))
))
(cell NUR_CORE
(cellType GENERIC)
(status (written
(timeStamp 2002 2 19 10 28 13)))
(userData VL_PLATFORM_CODE (string "K 94718533990 NUR_CORE")
(owner "Viewlogic_Systems"))
(view view_1
(viewType NETLIST)
(interface)
(contents
(instance OR2
(viewRef view_1 (cellRef ORCA_OR2_1))
(property LABEL (string "OR2") (owner "Viewlogic_Systems")))
(instance (rename PCI_CORE_15 "PCI-CORE")
(viewRef view_1 (cellRef OR3TP12_INTF))
(property LABEL (string "PCI-CORE") (owner "Viewlogic_Systems")))
(net (rename &_MAENN_16 "/MAENN")
(joined
(portRef Z (instanceRef OR2))
(portRef MAENN (instanceRef PCI_CORE_15))))
(net (rename &_MA_FULLN_17 "/MA_FULLN")
(joined
(portRef B (instanceRef OR2))
(portRef MA_FULLN (instanceRef PCI_CORE_15))))
(net (rename &_MR_EMPTYN_18 "/MR_EMPTYN")
(joined
(portRef A (instanceRef OR2))
(portRef MR_EMPTYN (instanceRef PCI_CORE_15))))
)
))
)
(design NUR_CORE
(cellRef NUR_CORE
(libraryRef NUR_CORE))
)
)
Edif netlist exported from FPGA Express:
(edif NUR_CORE
(edifVersion 2 0 0)
(edifLevel 0)
(keywordMap
(keywordLevel 0)
)
(status
(written
(timeStamp 2002 2 19 9 30 19)
(program "FPGA Express"
(version "3.3.1.4719")
)
(author "carsten")
)
)
(library DESIGNS
(edifLevel 0)
(technology
(numberDefinition)
)
(cell NUR_CORE
(cellType GENERIC)
(view Netlist_representation
(viewType NETLIST)
(interface)
(contents)
)
)
)
(design NUR_CORE
(cellRef NUR_CORE
(libraryRef DESIGNS)
)
)
)
Article: 39761
Hy,
I need to introduce some delay in a fpga design. I am trying to use 4
inverters in a row to have some delay but they are optimized by the
sythesis toll (XST). I know with synopsys tolls I have to use the
"dont touch" synthesis attribute, I've been looking the XST
dokumentation but I don't find any information regarding this. ("dont
touch does not work with XST)
Any help?
Thanks,
Paul.
Article: 39762
On Virtex FPGAs you can compel a logic function to a particular CLB (I
think it is somethink like RLOC X,Y where X and Y are row and column in
the CLB array)
If you place an inverter in a corner, you are even able to tune the
delay by setting the physical distance with the other inverter. Thus the
max. delay depends on the size of your FPGA.
Paul wrote:
> Hy,
>
> I need to introduce some delay in a fpga design. I am trying to use 4
> inverters in a row to have some delay but they are optimized by the
> sythesis toll (XST). I know with synopsys tolls I have to use the
> "dont touch" synthesis attribute, I've been looking the XST
> dokumentation but I don't find any information regarding this. ("dont
> touch does not work with XST)
>
> Any help?
>
> Thanks,
> Paul.
Article: 39763
This is a multi-part message in MIME format.
--------------D430349ADA367C4E2D564A80
Content-Type: text/plain; charset=us-ascii
Content-Transfer-Encoding: 7bit
Paul,
Firstly, adding delay like this is not exactly predictable, and may make
your problems worse!
Why do you need to add this form of delay?
If you really must do it then the attribute for XST is 'keep'.
Dave
Paul wrote:
> Hy,
>
> I need to introduce some delay in a fpga design. I am trying to use 4
> inverters in a row to have some delay but they are optimized by the
> sythesis toll (XST). I know with synopsys tolls I have to use the
> "dont touch" synthesis attribute, I've been looking the XST
> dokumentation but I don't find any information regarding this. ("dont
> touch does not work with XST)
>
> Any help?
>
> Thanks,
> Paul.
Article: 39764This is a multi-part message in MIME format. --------------B484B9AC4CE511A68FB34C1C Content-Type: text/plain; charset=us-ascii Content-Transfer-Encoding: 7bit You need to change the library to the following: library UNISIM; use UNISIM.Vcomponents.all; Dave Antonio wrote: > With Aldec I arrange the following RAM structure based on twelve > RAMB4S1, the simulation it's ok, > but when I use this file in Xilinx I've the following error from > ModelSim : > > # ERROR: Could not open library virtex at virtex: No such file or > directory > # ERROR: RAM_12x4096.vhd(27): Library virtex not found. > > OK, I'll try to survive infact XST arrange a black box for it and then > at the end of the > implementation I can see used the RAMB4S1, the problem is that it does > not take the initialization > values so I've zeros in any location. Can you help me to find the > errors and possibly maintaining > the possibility to simulate the project in Aldec ? > > Here's the memory structure : > > --------------------------------------------------------------------------------------------------- > -- Design unit header -- > library IEEE; > use IEEE.std_logic_1164.all; > > -- other libraries declarations > -- synopsys translate_off > library VIRTEX; > library IEEE; > use IEEE.vital_timing.all; > -- synopsys translate_on > > entity RAm is > port( > clk : in std_ulogic; > ADDR : in STD_LOGIC_VECTOR(11 downto 0); > dout : out STD_LOGIC_VECTOR(11 downto 0) > ); > end RAm; > > architecture RAm of RAm is > > ---- Component declarations ----- > > component RAMB4_S1 > -- synopsys translate_off > generic( > INIT_00 : BIT_VECTOR := > X"0000000000000000000000000000000000000000000000000000000000000000"; > INIT_01 : BIT_VECTOR := > X"0000000000000000000000000000000000000000000000000000000000000000"; > INIT_02 : BIT_VECTOR := > X"0000000000000000000000000000000000000000000000000000000000000000"; > INIT_03 : BIT_VECTOR := > X"0000000000000000000000000000000000000000000000000000000000000000"; > INIT_04 : BIT_VECTOR := > X"0000000000000000000000000000000000000000000000000000000000000000"; > INIT_05 : BIT_VECTOR := > X"0000000000000000000000000000000000000000000000000000000000000000"; > INIT_06 : BIT_VECTOR := > X"0000000000000000000000000000000000000000000000000000000000000000"; > INIT_07 : BIT_VECTOR := > X"0000000000000000000000000000000000000000000000000000000000000000"; > INIT_08 : BIT_VECTOR := > X"0000000000000000000000000000000000000000000000000000000000000000"; > INIT_09 : BIT_VECTOR := > X"0000000000000000000000000000000000000000000000000000000000000000"; > INIT_0A : BIT_VECTOR := > X"0000000000000000000000000000000000000000000000000000000000000000"; > INIT_0B : BIT_VECTOR := > X"0000000000000000000000000000000000000000000000000000000000000000"; > INIT_0C : BIT_VECTOR := > X"0000000000000000000000000000000000000000000000000000000000000000"; > INIT_0D : BIT_VECTOR := > X"0000000000000000000000000000000000000000000000000000000000000000"; > INIT_0E : BIT_VECTOR := > X"0000000000000000000000000000000000000000000000000000000000000000"; > INIT_0F : BIT_VECTOR := > X"0000000000000000000000000000000000000000000000000000000000000000"; > InstancePath : STRING := "*"; > MsgOn : BOOLEAN := True; > TimingChecksOn : BOOLEAN := True; > Xon : BOOLEAN := True; > thold_ADDR_CLK_negedge_posedge : VitalDelayArrayType(11 downto > 0) := (others => 0.01 ns); > thold_ADDR_CLK_posedge_posedge : VitalDelayArrayType(11 downto > 0) := (others => 0.01 ns); > thold_DI_CLK_negedge_posedge : VitalDelayArrayType(0 downto 0) > := (others => 0.01 ns); > thold_DI_CLK_posedge_posedge : VitalDelayArrayType(0 downto 0) > := (others => 0.01 ns); > thold_EN_CLK_negedge_posedge : VitalDelayType := 0.01 ns; > thold_EN_CLK_posedge_posedge : VitalDelayType := 0.01 ns; > thold_RST_CLK_negedge_posedge : VitalDelayType := 0.01 ns; > thold_RST_CLK_posedge_posedge : VitalDelayType := 0.01 ns; > thold_WE_CLK_negedge_posedge : VitalDelayType := 0.01 ns; > thold_WE_CLK_posedge_posedge : VitalDelayType := 0.01 ns; > tipd_ADDR : VitalDelayArrayType01(11 downto 0) := (others => > (0.0 ns,0.0 ns)); > tipd_CLK : VitalDelayType01 := (0.0 ns,0.0 ns); > tipd_DI : VitalDelayArrayType01(0 downto 0) := (others => (0.0 > ns,0.0 ns)); > tipd_EN : VitalDelayType01 := (0.0 ns,0.0 ns); > tipd_RST : VitalDelayType01 := (0.0 ns,0.0 ns); > tipd_WE : VitalDelayType01 := (0.0 ns,0.0 ns); > tpd_CLK_DO : VitalDelayArrayType01(0 downto 0) := (others => > (0.10000000000000001 ns,0.10000000000000001 ns)); > tpw_CLK_negedge : VitalDelayType := 0.01 ns; > tpw_CLK_posedge : VitalDelayType := 0.01 ns; > tsetup_ADDR_CLK_negedge_posedge : VitalDelayArrayType(11 downto > 0) := (others => 0.01 ns); > tsetup_ADDR_CLK_posedge_posedge : VitalDelayArrayType(11 downto > 0) := (others => 0.01 ns); > tsetup_DI_CLK_negedge_posedge : VitalDelayArrayType(0 downto 0) > := (others => 0.01 ns); > tsetup_DI_CLK_posedge_posedge : VitalDelayArrayType(0 downto 0) > := (others => 0.01 ns); > tsetup_EN_CLK_negedge_posedge : VitalDelayType := 0.01 ns; > tsetup_EN_CLK_posedge_posedge : VitalDelayType := 0.01 ns; > tsetup_RST_CLK_negedge_posedge : VitalDelayType := 0.01 ns; > tsetup_RST_CLK_posedge_posedge : VitalDelayType := 0.01 ns; > tsetup_WE_CLK_negedge_posedge : VitalDelayType := 0.01 ns; > tsetup_WE_CLK_posedge_posedge : VitalDelayType := 0.01 ns > ); > -- synopsys translate_on > port ( > ADDR : in STD_LOGIC_VECTOR(11 downto 0); > CLK : in std_ulogic; > DI : in STD_LOGIC_VECTOR(0 downto 0); > EN : in std_ulogic; > RST : in std_ulogic; > WE : in std_ulogic; > DO : out STD_LOGIC_VECTOR(0 downto 0) > ); > end component; > > ---- Constants ----- > constant VCC_CONSTANT : STD_LOGIC := '1'; > constant GND_CONSTANT : STD_LOGIC := '0'; > > ---- Signal declarations used on the diagram ---- > > signal GND : STD_LOGIC; > signal VCC : STD_LOGIC; > > ---- Configuration specifications for declared components > > -- synopsys translate_off > for U1 : RAMB4_S1 use entity VIRTEX.RAMB4_S1; > -- synopsys translate_on > -- synopsys translate_off > for U10 : RAMB4_S1 use entity VIRTEX.RAMB4_S1; > -- synopsys translate_on > -- synopsys translate_off > for U11 : RAMB4_S1 use entity VIRTEX.RAMB4_S1; > -- synopsys translate_on > -- synopsys translate_off > for U12 : RAMB4_S1 use entity VIRTEX.RAMB4_S1; > -- synopsys translate_on > -- synopsys translate_off > for U2 : RAMB4_S1 use entity VIRTEX.RAMB4_S1; > -- synopsys translate_on > -- synopsys translate_off > for U3 : RAMB4_S1 use entity VIRTEX.RAMB4_S1; > -- synopsys translate_on > -- synopsys translate_off > for U4 : RAMB4_S1 use entity VIRTEX.RAMB4_S1; > -- synopsys translate_on > -- synopsys translate_off > for U5 : RAMB4_S1 use entity VIRTEX.RAMB4_S1; > -- synopsys translate_on > -- synopsys translate_off > for U6 : RAMB4_S1 use entity VIRTEX.RAMB4_S1; > -- synopsys translate_on > -- synopsys translate_off > for U7 : RAMB4_S1 use entity VIRTEX.RAMB4_S1; > -- synopsys translate_on > -- synopsys translate_off > for U8 : RAMB4_S1 use entity VIRTEX.RAMB4_S1; > -- synopsys translate_on > -- synopsys translate_off > for U9 : RAMB4_S1 use entity VIRTEX.RAMB4_S1; > -- synopsys translate_on > > begin > > ---- Component instantiations ---- > > U1 : RAMB4_S1 > -- synopsys translate_off > generic map ( > INIT_00 => X"f0c33cf0f0f00f0ff0f00f0f0f3cc30ffc03fcc003fc033ffcc03fc0033fc03f", > INIT_01 => X"000000000000000000000000000000006a52a92aaa6aa5a995a5565554954a56", > INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000", > INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000", > INIT_04 => X"ffcccc33f3cccc33cc3333cfcc3333ffcf30f30cf30c00ffff0030cf30cf0cf3", > INIT_05 => X"73733939ccccc7c7e3e333339c9ccecefcc0033ff0030ffc3ff0c00ffcc0033f", > INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000", > INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000", > INIT_08 => X"f030300c000f0fcff3f0f000300c0c0ffff00ff30ff0300ff00c0ff0cff00fff", > INIT_09 => X"f81ffa07fa05fa05a05fa05fe05ff81ff300cff3cff3300ff00ccff3cff300cf", > INIT_0A => X"ff00abd5ff002addbb5400ffabd500ff4df3df3004ff4df3cfb2ff200cfbcfb2", > INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000", > INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000", > INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000", > INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000", > INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000" > ) > -- synopsys translate_on > port map( > ADDR => ADDR, > CLK => CLK, > DI(0) => GND, > DO(0) => dout(0), > EN => VCC, > RST => GND, > WE => GND > ); > > U10 : RAMB4_S1 > -- synopsys translate_off > generic map ( > INIT_00 => X"3030cfcfcfcf3030f3f30c0c0c0cf3f33cc33cc30ff00ff0f00ff00f3cc33cc3", > INIT_01 => X"000000000000000000000000000000007ffcf0c0fcf0c000fffcf0c0fcf0c000", > INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000", > INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000", > INIT_04 => X"3cccccc3cfc3c330f330300c3c0c0cc30303ccfc3f33c0c0fcff3303c0cc3f33", > INIT_05 => X"7ffefeeafefaeaa8eaa8a880a8a0800133cc33cc3cc333c03c333cc3cc33fc33", > INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000", > INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000", > INIT_08 => X"ff000000ff0f0f00ff000000ff0f0f00f3cf30f3f3cf00f0f3ff0c3030ff0c30", > INIT_09 => X"91896e76767789e8e8ee159191896e76fc00ffcc0033ff00ffc033fffc00ffc0", > INIT_0A => X"d2d64bd2696b2969696b2d69b42d96b4a55a5aada55a5aa55aa5a55a5aa5a55a", > INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000", > INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000", > INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000", > INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000", > INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000" > ) > -- synopsys translate_on > port map( > ADDR => ADDR, > CLK => CLK, > DI(0) => GND, > DO(0) => dout(5), > EN => VCC, > RST => GND, > WE => GND > ); > > U11 : RAMB4_S1 > -- synopsys translate_off > generic map ( > INIT_00 => X"000ccccc000ccccccccfffffcccfffff33ff33ff33ffffff0033003300333333", > INIT_01 => X"000000000000000000000000000000007cc3c33cc30f3cf0f8c3873cc31e3ce0", > INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000", > INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000", > INIT_04 => X"ccc0c0c3c30303333333333c3f3c3cccc00ff00f0ff0033f03fcf00f0ff00ff0", > INIT_05 => X"3cc3c33cc30c3cc33cc3c33cc31c3cc3c0f03f030f03f0fc00f03f0f3f0fc0fc", > INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000", > INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000", > INIT_08 => X"ff0000f0f00f0f00ff0000f0f00f0f00cfcf0030cc0c30333033cfcff3f3cc0c", > INIT_09 => X"a779615a1a8786e1791e1a87a779615acf33c330cc33cc33330c33ccc330f33c", > INIT_0A => X"922664d9d992b66d499b926464d9d9b6999c98c667717119673971998ee6e667", > INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000", > INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000", > INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000", > INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000", > INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000" > ) > -- synopsys translate_on > port map( > ADDR => ADDR, > CLK => CLK, > DI(0) => GND, > DO(0) => dout(3), > EN => VCC, > RST => GND, > WE => GND > ); > > U12 : RAMB4_S1 > -- synopsys translate_off > generic map ( > INIT_00 => X"0ff3300f0ff000ff0ff000ffff300cff0300fc3fff0300ff03c0ff3fff00c0ff", > INIT_01 => X"0000000000000000000000000000000073633133cc8cc6cee6c6676698198c98", > INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000", > INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000", > INIT_04 => X"f03c3c0f0fc3c3f0c3f0f03f3c0f0ff0c3f3cfc3cfc33cc33c3cf33cf33cc330", > INIT_05 => X"4fb0f20d3cc3cb34cf30f00f2cd3c33ccff3cccc3ccc3330333cf333cff3cccc", > INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000", > INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000", > INIT_08 => X"0f3030ffff0000ff0cf0f0ffcf0000fff0000ffc0fffc00f000ff000f0000ff0", > INIT_09 => X"a5baa5a25a5f5a5f5a055a05a5faa5bac33c0cc30cc33cccc3300cc30cc33c0c", > INIT_0A => X"999966b3999966bb6632996666b39966699a96a69669699a9624694969929624", > INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000", > INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000", > INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000", > INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000", > INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000" > ) > -- synopsys translate_on > port map( > ADDR => ADDR, > CLK => CLK, > DI(0) => GND, > DO(0) => dout(1), > EN => VCC, > RST => GND, > WE => GND > ); > > U2 : RAMB4_S1 > -- synopsys translate_off > generic map ( > INIT_00 => X"ccc00333ccc33333333ccccc33fccccccc33cf33cc333333330c33cc33cc0ccc", > INIT_01 => X"0000000000000000000000000000000040bf02ff33cc3bccc43b44bb23dd33dc", > INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000", > INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000", > INIT_04 => X"000c0c0f0fcfcfff3000000f0c0f0fffcfff303030300ccf0c0cfff3fff33000", > INIT_05 => X"b0ff00f2f3cf30fb30ff00f0f3df30f3c330c33cf33cf00c0ff3cff0c330c33c", > INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000", > INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000", > INIT_08 => X"f0c0c00f0f0f0ff0f000000f0f0f0ff03c3ccc3c33c33c333c333c3cc3c333c3", > INIT_09 => X"39dcc63b63999c669c666399399cc62303c00f03f0fcc0f0fc3ff0fc0f033f0f", > INIT_0A => X"4bb4d2bcb44b2d4b2dc24bd2d2bcb42d177a7ea17ee8e8857ea1e817e885815e", > INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000", > INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000", > INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000", > INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000", > INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000" > ) > -- synopsys translate_on > port map( > ADDR => ADDR, > CLK => CLK, > DI(0) => GND, > DO(0) => dout(2), > EN => VCC, > RST => GND, > WE => GND > ); > > U3 : RAMB4_S1 > -- synopsys translate_off > generic map ( > INIT_00 => X"c3c3c3c3c3c3c3c33c3c3c3c3c3c3c3ccccccccc3333333333333333cccccccc", > INIT_01 => X"0000000000000000000000000000000070f30c30f3ff30f0f0f30830f3ef30f0", > INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000", > INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000", > INIT_04 => X"0ff0f00cf30c0cc33cc3c330cf30300f03c333c33c333c3cc3c033c33c333c33", > INIT_05 => X"6aa9a995a9a595569556566a564a6aa93000f0f00f0f000c0fff0f0ff0f0cff3", > INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000", > INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000", > INIT_08 => X"000000ff000f0fff000000ff000f0fff3cc3c30c3cc3f30f0cf03cc3cf303cc3", > INIT_09 => X"c69e869c9c191879616763e6c69e869c03ccfc33ff3300cccc3f330003cccc3f", > INIT_0A => X"b99d22bb44469dd4d446b9dd22bb4462eeefeff7888e8eee88ce8eee00080888", > INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000", > INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000", > INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000", > INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000", > INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000" > ) > -- synopsys translate_on > port map( > ADDR => ADDR, > CLK => CLK, > DI(0) => GND, > DO(0) => dout(4), > EN => VCC, > RST => GND, > WE => GND > ); > > U4 : RAMB4_S1 > -- synopsys translate_off > generic map ( > INIT_00 => X"ff00ff00ff00ff00ff00ff00ff00ff00ffff0000ffff0000ffff0000ffff0000", > INIT_01 => X"00000000000000000000000000000000ff00ff00ff00ff00ff00ff00ff00ff00", > INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000", > INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000", > INIT_04 => X"ff0c0c00ffcfcf00ff000000ff0f0f00ffff0000ffff0000ffff0000ffff0000", > INIT_05 => X"ff00ff00ff00ff00ff00ff00ff00ff00ff00ff00ff00ff00ff00ff00ff00ff00", > INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000", > INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000", > INIT_08 => X"ff0c0c00ffcfcf00ff000000ff0f0f00ffff0000ffff0000ffff0000ffff0000", > INIT_09 => X"ff00ff00ff00ff00ff00ff00ff00ff00ff00ff00ff00ff00ff00ff00ff00ff00", > INIT_0A => X"ff00ff00ff00ff00ff00ff00ff00ff00ff00ff00ff00ff00ff00ff00ff00ff00", > INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000", > INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000", > INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000", > INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000", > INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000" > ) > -- synopsys translate_on > port map( > ADDR => ADDR, > CLK => CLK, > DI(0) => GND, > DO(0) => dout(11), > EN => VCC, > RST => GND, > WE => GND > ); > > U5 : RAMB4_S1 > -- synopsys translate_off > generic map ( > INIT_00 => X"f00f3fc03fc00ff0f00ffc03fc030ff0f3300ccf0ffff000fff0000f0ccff330", > INIT_01 => X"00000000000000000000000000000000255a5aa5a55a5aa55aa5a55a5aa5a55a", > INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000", > INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000", > INIT_04 => X"30f0f0f30c0c0c3cc3c3c3cf303030f30c0cf0f0cfc30f0f0f0f3c0cf0f0cfc3", > INIT_05 => X"daa5a55a5aa5a55aa55a5aa5a55a5aa40fc30fc3fc3ff03c03f003c03c0f3c0f", > INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000", > INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000", > INIT_08 => X"c33c3c3c3cccccc33cc3c3c3c333333cff3000ff00cfff00ff000cff00fff300", > INIT_09 => X"dad2b4a45b5ad2b2b2b4a525dad2b4a4f00f0ff0f03c0ff0f00fc3f0f00f0ff0", > INIT_0A => X"dfdbb0204d4ff2b2b2b00d4dfbf22404f550500af550500aaff5f550aff5f550", > INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000", > INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000", > INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000", > INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000", > INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000" > ) > -- synopsys translate_on > port map( > ADDR => ADDR, > CLK => CLK, > DI(0) => GND, > DO(0) => dout(6), > EN => VCC, > RST => GND, > WE => GND > ); > > U6 : RAMB4_S1 > -- synopsys translate_off > generic map ( > INIT_00 => X"3fcc003f003fcc033fcc03ff03ffcc03000ff330f00ffff0f0000ff0f3300fff", > INIT_01 => X"00000000000000000000000000000000b44f4ff2f22c2ccb2ccbcbb0b00d0dd3", > INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000", > INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000", > INIT_04 => X"fc3c3c3fc0c0c0f0f0f0f0fc030303c0f0f00000f0fc0000ffffc0f0fffff0fc", > INIT_05 => X"b0cb0db0d30d34d334d34f34f24f2cf2ff33ff3333003f03ff03ff3333003300", > INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000", > INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000", > INIT_08 => X"3ffcfcfcf0c0c0c0fcf0f0f0c0000003000fff00f00ffff0f0000ff0ff000fff", > INIT_09 => X"3fdcc403bfdcc0033ffcc4023fdcc4033fcc003f03ffcc033fcc003f03ffcc03", > INIT_0A => X"2ff0f0f0f040f00f0ff0fdf0f0f0f00b344f4ff0f22c2cc33ccbcbb0f00d0dd3", > INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000", > INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000", > INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000", > INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000", > INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000" > ) > -- synopsys translate_on > port map( > ADDR => ADDR, > CLK => CLK, > DI(0) => GND, > DO(0) => dout(8), > EN => VCC, > RST => GND, > WE => GND > ); > > U7 : RAMB4_S1 > -- synopsys translate_off > generic map ( > INIT_00 => X"0030ffff0000f3ff0030ffff0000f3ff00ff00ff00f000ff00fff0ff00ff00ff", > INIT_01 => X"0000000000000000000000000000000000ff00ff00ff00ff00ff00ff00ff00ff", > INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000", > INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000", > INIT_04 => X"000c0cff00cfcfff000000ff000f0fff00ffffff000000ff00ffffff000000ff", > INIT_05 => X"00ff00ff20ff00ff00ff00fb00ff00ff00f0f0ff00f0f0ff00f0f0ff00f0f0ff", > INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000", > INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000", > INIT_08 => X"000c0cff00cfcfff000000ff000f0fff00ff00ff00f000ff00fff0ff00ff00ff", > INIT_09 => X"00f330ff00f330ff00f330ff00f330ff0030ffff0000f3ff0030ffff0000f3ff", > INIT_0A => X"00ff000f0fff00ff00ff000f0fff00ff00ff00ff00ff00ff00ff00ff00ff00ff", > INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000", > INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000", > INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000", > INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000", > INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000" > ) > -- synopsys translate_on > port map( > ADDR => ADDR, > CLK => CLK, > DI(0) => GND, > DO(0) => dout(10), > EN => VCC, > RST => GND, > WE => GND > ); > > U8 : RAMB4_S1 > -- synopsys translate_off > generic map ( > INIT_00 => X"f0c3f0f0f0f03cf0f0c3f0f0f0f03cf0fff0ffff000f0000ffff0fff0000f000", > INIT_01 => X"00000000000000000000000000000000fbb0b000fff3f330f3303000fff2f220", > INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000", > INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000", > INIT_04 => X"f30c0cf030cfcf00ff0000f3f00f0f30ff0000ff00ffff00ff0000ff00ffff00", > INIT_05 => X"ff30f200dff2fb20fb20b004ffb0f300f00f0ff0f00f0ff0f00f0ff0f00f0ff0", > INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000", > INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000", > INIT_08 => X"f00c0cf300cfcf30f30000ff300f0ff0fff0ffff000f0000ffff0fff0000f000", > INIT_09 => X"f02ccbf0f02ccff0f00ccbf0f02ccbf0f0c3f0f0f0f03cf0f0c3f0f0f0f03cf0", > INIT_0A => X"ff0f0ff0f0bf0f00ff0f02f0f00f0f00fbb0b000fff3f330f3303000fff2f220", > INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000", > INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000", > INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000", > INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000", > INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000" > ) > -- synopsys translate_on > port map( > ADDR => ADDR, > CLK => CLK, > DI(0) => GND, > DO(0) => dout(9), > EN => VCC, > RST => GND, > WE => GND > ); > > U9 : RAMB4_S1 > -- synopsys translate_off > generic map ( > INIT_00 => X"c3cc33f333f3cc3cc3cc30333033cc3cf00ffcc0000ff00f0ff00ffffcc00ff0", > INIT_01 => X"0000000000000000000000000000000046636339399c9cc69cc6c6636339399c", > INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000", > INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000", > INIT_04 => X"0ccccccfc3c3c3f33030303c0c0c0ccf0f0f00000f03f0f0f0f03f0fffff0f03", > INIT_05 => X"63c639639c39c69cc69c63c639639c39330c330ccf33c330333c330ccf33cf33", > INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000", > INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000", > INIT_08 => X"cf0c0c0cf3c3c3cf0c303030cf0f0f0cf00ff0f00f3ff00f0ff0030ff0f00ff0", > INIT_09 => X"e31cc738639ce33cc338c639e31cc738c3cc33c33c03cc3cc3cc3fc33c33cc3c", > INIT_0A => X"df2000ffb24fff00ff000db200fffb04c6636333399c9cccccc6c6633339399c", > INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000", > INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000", > INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000", > INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000", > INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000" > ) > -- synopsys translate_on > port map( > ADDR => ADDR, > CLK => CLK, > DI(0) => GND, > DO(0) => dout(7), > EN => VCC, > RST => GND, > WE => GND > ); > > ---- Power , ground assignment ---- > > GND <= GND_CONSTANT; > VCC <= VCC_CONSTANT; > > end RAm;Article: 39765
Hello, Anyone know of anybody who sells Development and/or prototype boards with a Virtex II 2V3000 or larger on it? I only have seen one with a 2V40 on it. Thanks. Salman -- Salman Sheikh NASA/GSFC Code 564 Greenbelt, MD 20771 301-286-3763 301-286-0220 (fax)Article: 39766
"Falk Brunner" <Falk.Brunner@gmx.de> wrote in message news:a4lm2v$14b2v$1@ID-84877.news.dfncis.de... > "Paul Taylor" <p.taylor@ukonline.co.uk> schrieb im Newsbeitrag > news:pqhb8.3948$Jp6.691987@monolith.news.easynet.net... > > > Maybe next time you invest at least 20% of this work into a reseach > about > > > availability and future support? > > > > When I bought the devices 18 months ago, Spartan-II was either on long > > lead time, or was difficult to obtain, so I was advised the -XL at the > time. > > Hmm, OK this is another story. > > -- > MfG > Falk > > > > I had similar advice as well. TheronArticle: 39767
That is the exact problem I get. However, the post place and route simulation seems to be functional for me. (If I am interpreting it correctly.) I have a request for help in to Xilinx, but so far they have not found a solution for me. "Jonas Weiss" <jweiss@kontronmedical.ch> wrote in message news:3C6CBFDF.EC64A773@kontronmedical.ch... > Hello, > I was just wondering if you got your asynchronous FIFO to work by now. For some > days I'm also trying to get my design using one of these to work, without > success yet (ISE 4.1 & Model Sim XE Starter). I am using continuous read and > write clocks with synchronous enables. > Behavioral simulation works fine, but as soon as I proceed to a post translate > simulation I get 'open' select signals of internal fifo-muxes in the translate > file. > P&R works, just the post P&R simulation is not exactly what I expected it to be, > as if the behavioral model and the coregen netlist were not consistent. > Any new ideas yet? > > Thanks > > Jonas > >Article: 39768
No, you can treat the BlockRAM as an edge-triggered device. You just have to apply the correct inputs (A,D,EN,WE) the appropriate set-up time before the clock. EN and WE have a longer set-up time than A and D, since they are responsible for getting the operation started. Think of all these inputs as inputs to a flip-flop. Peter Alfke ( back from a 2-week trip) ================= "H.L" wrote: > Hello all, > I know that this issue is well discussed in this newsgroup but still I have > some questions. > In a Virtex-E FPGA the setup time for the EN,WE signals are 2.5 ns and 2.2ns > (plz confirm) but the setup time for the address,data is about 1.1ns (plz > confirm). I want to use 3 BRAMs 128x32 in a Virtex-E 600 (speed grade 6) @ > 77 MHz (or clock period=12ns), do I have to keep the "input" signals stable > for 2 clock periods to succeed a correct timing in the read/write operations > or is it totally wrong (except for too slow)? > > Best Regards, > HarrisArticle: 39769
I think I may have missed a significant point about the Coolrunner CPLDs and ISP. I picked the XCR3256XL because I needed to be able to do boundary scan on the board for production test and I wanted to be able to change the design on the fly (meaning from the MCU on the board). But it looks like the only way to program this part is to use the JTAG port. Connecting the JTAG port to the MCU prevents me from using the JTAG port for boundary scan. Am I missing something? Does ISP mean connecting the board to a PC through a JTAG cable? Is that the only way I can program an XPLA3 part? I could replace this part with a 3.3 volt FPGA, but I hate to do that since I expect 3.3 volt FPGAs will be going the way of the dodo bird in a year or two and they are not cheap in the meantime. -- Rick "rickman" Collins rick.collins@XYarius.com Ignore the reply address. To email me use the above address with the XY removed. Arius - A Signal Processing Solutions Company Specializing in DSP and FPGA design URL http://www.arius.com 4 King Ave 301-682-7772 Voice Frederick, MD 21701-3110 301-682-7666 FAXArticle: 39770
I am not clear about what you are trying to do. If you want to create a bit stream, then why do you need to include VHDL for the embedded PCI-Core? This part is already in the silicon and should not be represented in the bit stream. If you are trying to perform simulation, I expect you should do this before you synthesize. You will need some form of model for the PCi-Core. If you translate the schematic to VHDL, then your VHDL for the PCI-Core should be a module in the VHDL that is produced. But the fact that you are trying to produce an EDIF netlist says to me that you are doing the former rather than the later. So why are you trying to include the PCI-Core in the bit stream? Carsten Heise wrote: > > Hello, > > I try to use an Orca FPSC with an integrated PCI-Core (its an ASIC on the same chip as the FPGA area). > The functional design was made in scematic capture in Viewlogic's Viewdraw and the PCI-Core (that is > represented by a VHDL netlist) was included as a symbol. The next step was to create an EDIF netlist. > I want to use FPGA Express to synthesize the whole design with the PCI-Core. To check the > combining of the PCI-Core with a schematic, I just created one with an OR gate connected with the symbol > of the PCI-Core. After this Icreated an EDIF netlist from the schematic and added the netlist and the > VHDL netlist of the Core to a FPGA Express project. > First problem was a warning: > Warning: Cannot link cell 'OR3TP12_INTF/OR3TP12_CORE_INST' to its reference design 'or3tp12_core6_ts'. (FPGA-LINK-2) > I could prevent this warning by adding an architecture to the entity 'or3tp12_core6_ts'. After the design > was synthesized, I exported an EDIF netlist for the use in the Orca Foundry to place-and-route the design. > There an error occured called > ERROR - ngdbuild: logical root block 'NUR_CORE' with type 'NUR_CORE' is unexpanded > Next, I had a look at the exported netlist and found it nearly empty. > > I don't have any explanation for this. I hope somebody can give me a hint. > > Best Regards > > Carsten > > Edif netlist of the schematic design: > > (edif nur_core ...snip... -- Rick "rickman" Collins rick.collins@XYarius.com Ignore the reply address. To email me use the above address with the XY removed. Arius - A Signal Processing Solutions Company Specializing in DSP and FPGA design URL http://www.arius.com 4 King Ave 301-682-7772 Voice Frederick, MD 21701-3110 301-682-7666 FAXArticle: 39771
rickman wrote: >I think I may have missed a significant point about the Coolrunner CPLDs >and ISP. I picked the XCR3256XL because I needed to be able to do >boundary scan on the board for production test and I wanted to be able >to change the design on the fly (meaning from the MCU on the board). But >it looks like the only way to program this part is to use the JTAG port. >Connecting the JTAG port to the MCU prevents me from using the JTAG port >for boundary scan. > Why does connecting the JTAG port to the MCU prevent your from using the JTAG port for boundary scan? You just have to make sure the MCU is not driving the pins during boundary scan. Perhaps you could hold it in reset or use JTAG on the MCU to disable all its pins. I have never used Coolrunner, but I have used Altera CPLD's in a similar fashion. I always design for boundary scan, but I have never had the volume to use it. Alan Nishioka alann@accom.comArticle: 39772
Paul wrote: > I need to introduce some delay in a fpga design. Consider using a shift register. -- Mike TreselerArticle: 39773
This is a multi-part message in MIME format. --------------4D713901ADE0FF89062FFCBC Content-Type: text/plain; charset=us-ascii Content-Transfer-Encoding: 7bit Rick, Just connect the port to the MCU, implement an SVF player in the MCU (details on our web site), and then ensure that the MCU cannot drive when the board is being boundary scanned. Dave rickman wrote: > I think I may have missed a significant point about the Coolrunner CPLDs > and ISP. I picked the XCR3256XL because I needed to be able to do > boundary scan on the board for production test and I wanted to be able > to change the design on the fly (meaning from the MCU on the board). But > it looks like the only way to program this part is to use the JTAG port. > Connecting the JTAG port to the MCU prevents me from using the JTAG port > for boundary scan. > > Am I missing something? Does ISP mean connecting the board to a PC > through a JTAG cable? Is that the only way I can program an XPLA3 part? > I could replace this part with a 3.3 volt FPGA, but I hate to do that > since I expect 3.3 volt FPGAs will be going the way of the dodo bird in > a year or two and they are not cheap in the meantime. > > -- > > Rick "rickman" Collins > > rick.collins@XYarius.com > Ignore the reply address. To email me use the above address with the XY > removed. > > Arius - A Signal Processing Solutions Company > Specializing in DSP and FPGA design URL http://www.arius.com > 4 King Ave 301-682-7772 Voice > Frederick, MD 21701-3110 301-682-7666 FAXArticle: 39774
I'm not sure if I understand what you are trying to accomplish but I'll take a SWAG at answering your question: Step 1) Use the BRAM in synchronous mode Step 2) Drive the inputs to the BRAM with F/F's clocked with the same clock as the BRAM Step 3) Let the P&R tool worry about metting set/hold issues after you've selected a topology that is easily handled by the tool set. Regards! "H.L" <alphaboran@yahoo.com> wrote in message news:<a4t9p2$hog$1@ulysses.noc.ntua.gr>... > Hello all, > I know that this issue is well discussed in this newsgroup but still I have > some questions. > In a Virtex-E FPGA the setup time for the EN,WE signals are 2.5 ns and 2.2ns > (plz confirm) but the setup time for the address,data is about 1.1ns (plz > confirm). I want to use 3 BRAMs 128x32 in a Virtex-E 600 (speed grade 6) @ > 77 MHz (or clock period=12ns), do I have to keep the "input" signals stable > for 2 clock periods to succeed a correct timing in the read/write operations > or is it totally wrong (except for too slow)? > > Best Regards, > Harris
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