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ssy wrote: > in the timer, the counter can be driven by 25Mhz clock or 33Mhz clock, > so I use a controll bit to select them, then use the result to drive > counter > > so when quartus finish his work, he tell me that my design may not > function, and 1300 path can not be operational becasue their clock > skew larger than logic delay. Make sure the 25MHz is assigned to a global clock pin and that the counter output is resynched to the 33 MHz clock before it is read. -- Mike TreselerArticle: 41076
"Kevin Neilson" <kevin_neilson@removethis-yahoo.com> schrieb im Newsbeitrag news:In4m8.78960$702.20204@sccrnsc02... It looks very much like a bug. This cross clock domain analysis isnt working very well. But you should better cross this clock domain without having logic in between . Just drive data with some FlipFlop on on clock domain and capture them directly with FlipFlops on the other. -- MfG FalkArticle: 41077
"Theron Hicks" <hicksthe@egr.msu.edu> schrieb im Newsbeitrag news:a7ac1l$b31$1@msunews.cl.msu.edu... > I have gotten numbers from XPOWER for current requirements. Has anyone any > experience as to what the accuracy of the estimates is? In my case, the I dont. > estimate is about 360mA for my design. The vast majority of that is the > 300mA quiescent current. Is that a reliable number? The chip is a 300 mA quitescent current for a 2s50e??? Hmm, I dont think so. even at max temp/voltage/process, this should be at least 2..3 times lower. Regards FalkArticle: 41078
"Austin Lesea" <austin.lesea@xilinx.com> schrieb im Newsbeitrag news:3C98AF62.C5428F41@xilinx.com... > The amazing thing about the DCMs though, that help you out here, is that the most > any cycle can be from the last cycle is one tap (~65 ps). So the rest of the "big Iam really curious about the jitter of the tap delay value. Over the last 1 1/2 year, I read official numbers from Xilinx, talking about tap delay in the DLL between 40..65 ps. And the low values where in the days of good, old Spartan-II. So, what is the tap delay of the DLL really? -- MfG FalkArticle: 41079
Regarding CPLD/FPGA oscillators - I spent 3+ years doing that with Altera 600 / 900 / 7128 CPLDs with some success. And I'd *highly* recommend against it! All the inverter based oscillators you'll read about (Intel has a fine app note on 'em) assume a simple single-stage inverter. But your IC has several stages from any input pin through the programmable logic array(s) to the output driver and pin. So you *can't* bias it into a linear region. A resistor between the input and output pins will force it to oscillate and a crystal will hopefully get that oscillation to the frequency you want. But if you want it to work in production quantities over temperature and IC mask revisions and such, forget it. Buying a complete oscillator - or engineering a discrete one - is the way to go. Let the digital ICs do just that. Jim Horn, WB9SYN/6 (Been there, done that - won't do it again)Article: 41080
"Kevin Brace" <ihatespam99kevinbraceusenet@ihatespam99hotmail.com> schrieb
im Newsbeitrag news:a79fvc$qo1$1@newsreader.mailgate.org...
> Compared to using a regular CLB FF, using an IOB OE FF makes Tsu
> worse because routing distance will get longer, and will get only worst
> if the device's die gets larger.
> Also, for a path starting from unregistered control signals of PCI bus
> (FRAME#, IRDY#, DEVSEL#, TRDY#, and STOP#) to AD[31:0] or C/BE#[3:0]'s
> OE FFs, I already got 4 levels of 4-input LUT, and so far, I haven't
> been successful reducing the level of LUT.
I got it. But still, try to locate the critical stuff close together so that
the signal dont have to cross the whol chip.
> But the problem is XST overrides my design of using one OE FF for
> AD[31:0], and one OE FF for C/BE[3:0], and duplicates them 32 times and
> 4 times, respectively.
> Attaching "keep" attribute didn't help either.
Did you check the settings in the synthesis options?? In the preferences,
switch to "Advanced" properties, then there is a switch which allows you to
set global generation of IOB FlipFlops. Just set it to Auto or OFF. Then
just add the right attribute to the FF you want inside the IOB.
attribute iob: string;
attribute iob of
{component_name|entity_name|label_name}:
{component|entity|label} is "(true|false|auto)";
Regards
Falk
Article: 41081What is the purpose of having a PCI card? I use Insight Electronics Spartan-II PCI card for my PCI IP core development. http://208.129.228.206/solutions/kits/xilinx/spartan-iipci.html The card cost me only $145, and even with two other option boards and shipping, the whole thing cost me only about $370. Because the board has Spartan-II, you can use the free ISE WebPACK for development, but you won't be able to use LogiCORE PCI with it ($2,000 for a license) because Xilinx for some reason doesn't officially support XST (it's their in-house synthesis tool . . .) to synthesize a user design with LogiCORE PCI, although someone a few months ago claimed that he was able to synthesize his user design + LogiCORE PCI with XST. Alternatively, you should be able to use opencores.org PCI IP core with the same Spartan-II PCI card since that is the card opencores.org PCI IP core project used. Since I was able to design my own PCI IP core from scratch with ISE WebPACK + ModelSim XE-Starter, it is possible for anyone to do so, but it takes some time to design it, and get the timings right (Tsu < 7ns and Tval < 11ns for 33MHz PCI). Kevin Brace (In general, don't respond to me directly, and respond within the newsgroup.) Jimmy Zhang wrote: > > With PCI interface only! > Jimmy Zhang wrote in message > <_lYl8.74605$ZR2.35796@rwcrnsc52.ops.asp.att.net>... > >I am looking for used ones. Does anyone have what I am looking for? > >Where do I go to find a dealer for that, I don't mind buying used ones as > >long as they work. > > > >Article: 41082
Just curious if they have a Linux version of the driver or not? Jimmy Kevin Brace wrote in message ... >What is the purpose of having a PCI card? >I use Insight Electronics Spartan-II PCI card for my PCI IP core >development. > >http://208.129.228.206/solutions/kits/xilinx/spartan-iipci.html > > >The card cost me only $145, and even with two other option boards and >shipping, the whole thing cost me only about $370. >Because the board has Spartan-II, you can use the free ISE WebPACK for >development, but you won't be able to use LogiCORE PCI with it ($2,000 >for a license) because Xilinx for some reason doesn't officially support >XST (it's their in-house synthesis tool . . .) to synthesize a user >design with LogiCORE PCI, although someone a few months ago claimed that >he was able to synthesize his user design + LogiCORE PCI with XST. >Alternatively, you should be able to use opencores.org PCI IP core with >the same Spartan-II PCI card since that is the card opencores.org PCI IP >core project used. >Since I was able to design my own PCI IP core from scratch with ISE >WebPACK + ModelSim XE-Starter, it is possible for anyone to do so, but >it takes some time to design it, and get the timings right (Tsu < 7ns >and Tval < 11ns for 33MHz PCI). > > > >Kevin Brace (In general, don't respond to me directly, and respond >within the newsgroup.) > > > >Jimmy Zhang wrote: >> >> With PCI interface only! >> Jimmy Zhang wrote in message >> <_lYl8.74605$ZR2.35796@rwcrnsc52.ops.asp.att.net>... >> >I am looking for used ones. Does anyone have what I am looking for? >> >Where do I go to find a dealer for that, I don't mind buying used ones as >> >long as they work. >> > >> >Article: 41083
It's not easy but it's not impossible either. I took a ram based C programmable state machine that I developed and was able to update the control store via the select map in real time while the device was running. Just read xapp151. If your really thinking about making your own software type xdl -pips -report v50 SteveArticle: 41084
There's no one answer. How many simultaneously switching outputs do you have? Are you using fast or slow risetime drivers in the 7064S? You can estimate what your worst case current surge would be from the quantity and risetime. From the current surge estimation, you could figure what effective impedance to ground you'd need to avoid a significant power plane "bounce" in voltage. If you need 1 ohm (you probably need lower), a single cap might take care of you. If you use a few caps of a few different sizes, you may cover a wider frequency range without troubles. It's always been a shotgun approach for me in the past - 100nF and 10nF caps, quantity depending on device size. I've come to realize the shotgun approach could leave some ugliness in the stiffness of the power planes at the frequencies that matter for my edge rates. My 7064S shotgun approach might include one or two caps per side of the device, shared evenly between 100nF and 10nF. It's not based on anything but gut feel. Regardless, you'd probably be under-bypassed with a single capacitor even for such a "small" device. Lähteenmäki Jussi wrote: > Hi, > > Im about to use EPM7064S in 44-pin PLCC in my desing and was wondering > what is the correct filter capasitance value between VCC and GND. > Couldn't find it in any datasheets. Perhaps, going for the obvious > 100nF? > > Regards and thank you in advance, > -- > Jussi Lahteenmaki > Tampere University of Technology > FinlandArticle: 41085
Who is "they" in this case? You mean, Insight Electronics? All the reference design's software is for Windows 9x/NT/2000. Another thing I should add is that according to another person who was interested in this board said Insight Electronics discontinued the board. Supposedly, they are going to release a new one at some point. Kevin Brace (In general, don't respond to me directly, and respond within the newsgroup.) Jimmy Zhang wrote: > > Just curious if they have a Linux version of the driver or not? > > JimmyArticle: 41086
The terminology is a bit loose, perhaps. The only way to get the average frequencies to match is to have one clock slave to the other in some fashion. With clean PLLs with tight loops, there's often a fraction of a clock cycle of deviation. The telecom folks don't have the luxury of tight loops and have to design for systems that introduce phase jitter that is many clock cycles in deviation (hence the need for the FIFO) but still requires that the two clocks average to exactly the same frequency - if one is "off" by 0.01%, then you'll end up dropping one out of every 10000 data elements. The clocks need to be phase locked, but can deviate by (significantly) more than one clock period with an appropriately sized FIFO. One trouble that always hit the telecom designs - do I "prefill" the FIFO to exactly one half before starting the drain or do I "adaptively" figure out where the halfway point needs to be before declaring the system stable? Peter Alfke wrote: > John_H wrote: > > > If read and write clocks are both 27.5 MHz - though unrelated - and the > > data widths are the same (your 27.5x4 mention confused me), you'll have a > > 50% chance of working. The two clocks must phase locked (with the FIFO > > absorbing any jitter between the two clocks) or you must design the system > > to occasionally "drop" a data value and design the FIFO to work properly > > under these conditions. > > > > I find this misleading. > The two "27.5 MHz" frequencies need not be phase aligned, but they must have the > same average frequency value. Phase differences and short-term frequency > deviations are absorbed by the FIFO (that's its only purpose!). > If the frequencies are long-term different, then you must either insert or > delete characters occasionally. The telecom people have developed this to a fine > art. > > Peter Alfke, Xilinx Applications.Article: 41087
John_H wrote: > The terminology is a bit loose, perhaps. ... > The clocks need to be phase locked, > but can deviate by (significantly) more than one clock period with an appropriately > sized FIFO. That's a self-contradicting sentence! Peter John, I do not like "loose terminology". The FIFO does NOT require phase lock, not even short-term frequency lock. It fixes all that. But it can cover up for a frequency deviation only for a limited time, then it either misses one character or has to "invent" a character. You may mean the same thing, but that's not what you said (wrote). Peter AlfkeArticle: 41088
--------------234A8691271474D9D5DE2E50 Content-Type: text/plain; charset=iso-8859-1 Content-Transfer-Encoding: quoted-printable Hi, I actually run in to this problem a little while ago. The reason for the huge timing delays is when you are using DLL and has a clock period constraint that has many decimals. I think that there are some rounding errors in the timing tools. So just change your clock period to 41 ns and the problem should go away G=F6ran Kevin Neilson wrote: > All,I keep running into this problem all the time in which I have a > route that misses my constraint by tens of thousands of nanoseconds. > I'm using the Xilinx 4.1 PAR tools. In this case the bad paths are > ones that cross from a domain with a 20ns period to a domain with a > 10ns period. The faster domain is generated from a DLL locked to the > first, so while it is twice the freq, it is synchronous to the first. > I'm taking care to read data in the second domain only on "even" > cycles of the first domain, so the data has 20ns to get from the slow > domain to the fast.The first evidence of a problem comes during > routing: End of iteration 1 > 22869 successful; 0 unrouted; (152088) REAL time: 5 mins 34 > secs You've all cringed at seeing this message before. Then, in the > PAR summary, I see > this:------------------------------------------------------------------= -------------- > > * PERIOD analysis for net "clk_management/f | 10.416ns | 38591.280ns > | 4 > irclk_dcm_clk2x" derived from NET "clk_m | | > | > anagement/CLK_ibufg" PERIOD =3D 41.667 nS | | > | > HIGH 50.000000 % | | > | > > -----------------------------------------------------------------------= --------This > is obviously a problem: my constraint for the fast clock domain is > 10.4ns, and one path requires 38591ns, meaning I need to slow my clock > to the kilohertz range. Here's the detail from > Trace:=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3DTiming > constraint: PERIOD analysis for net "clk_management/firclk_dcm_clk2x" > derived from NET "clk_management/CLK_ibufg" PERIOD =3D 41.667 nS HIGH= > 50.000000 % ; divided by 2.00 and duty cycle corrected to 10.416 nS > HIGH 5.208 nS 29336 items analyzed, 58 timing errors detected. > Minimum period is > 38591.280ns.-----------------------------------------------------------= ---------------------Slack: > -3.704ns (requirement - (data path - negative clock skew)) > Source: dpll/theta[12] Destination: > fir/phase_reclock[5] Requirement: 0.001ns Data Path > Delay: 3.705ns (Levels of Logic =3D 4) Negative Clock Skew: > 0.000ns Source Clock: sclk rising at 216975.695ns > Destination Clock: firclk rising at 216975.696ns Data Path: > dpll/theta[12] to fir/phase_reclock[5] Location Delay > type Delay(ns) Physical > Resource Logical > Resource(s) ------------------------------------------------- > ------------------- SLICE_X57Y32.YQ Tcko > 0.568 > theta[13] > dpll/theta[12] SLICE_X54Y33.F1 net (fanout=3D3) 0.551 > theta[12] SLICE_X54Y33.COUT Topcyf 0.769 > fir/phase_reclock[2] > fir/phase_reclock_qxu[2] > fir/phase_reclock_cry[2] > fir/phase_reclock_cry[3] SLICE_X54Y34.CIN net (fanout=3D1) > 0.000 fir/phase_reclock_cry[3]/O SLICE_X54Y34.Y > Tciny 1.446 > fir/phase_reclock[4] > fir/phase_reclock_cry[4] > fir/phase_reclock_s[5] SLICE_X54Y34.DY net (fanout=3D1) > 0.001 fir/phase_reclock_s[5] SLICE_X54Y34.CLK > Tdyck 0.370 > fir/phase_reclock[4] > fir/phase_reclock[5] > ------------------------------------------------- > --------------------------- > Total 3.705ns (3.153ns logic, > 0.552ns route) > (85.1% logic, 14.9% > route)-----------------------------------------------------------------= --------------- This > is just whack. You can see that the path delay is 3.7ns, which easily > meets the 20ns period of the slow clock (sclk). However, for some > reason it thinks the source clock is sclk rising at 216975ns. Where > did that come from? And how did it get a slack of -3.704ns? Also, > where did the 38591ns period in the PAR summary come from? That's not > even close to 216975. This path really shouldn't be analyzed at all. > The Xilinx answer files state that 4.1i doesn't analyze paths that > cross clock domains. Sometimes when I see this problem, I can "fool" > PAR by putting a FROM-TO in the UCF that explicity states that paths > from the "sclk" domain to the "firclk" domain have 20ns. However, > this isn't working now, and Trace claims that 0 items are analyzed > using that TIMESPEC, even though there are obviously many paths that > fit that description.Has anybody else seen this?-KevinArticle: 41089
Falk, It is typically ~50 ps, but we spec it larger for a worst case, as not taps are created equal. Austin Falk Brunner wrote: > "Austin Lesea" <austin.lesea@xilinx.com> schrieb im Newsbeitrag > news:3C98AF62.C5428F41@xilinx.com... > > > The amazing thing about the DCMs though, that help you out here, is that > the most > > any cycle can be from the last cycle is one tap (~65 ps). So the rest of > the "big > > Iam really curious about the jitter of the tap delay value. Over the last 1 > 1/2 year, I read official numbers from Xilinx, talking about tap delay in > the DLL between 40..65 ps. And the low values where in the days of good, old > Spartan-II. > So, what is the tap delay of the DLL really? > > -- > MfG > FalkArticle: 41090
Out of curiosity, why do you want a single symbol for one of these huge parts? Wouldn't you be better off with multiple symbols, each symbol a separate (or related multiple even) design function? "Chuck" <chuck@sigtek.com> wrote in message news:rtIl8.4212$T_.80903@iad-read.news.verio.net... > Anybody know where I can get orcad symbols for virtex 2 parts? > > Chuck > >Article: 41091
Hi all ... hope you can give me a hint out of this one ! I intend to generate an application (software) that generates the VHDL representation of an ASIC I want to synthesize immediately after on an FPGA. Ideally everything should be handled by this program, including the compilation to the bitstream format. But so far I didn't quite found any compiler library that would allow me to handle this task programmatically. Does any of you know where to find such a library ? (I have no constraint yet on what FPGA to use, so even a library dedicated to a very specific target would do). One more thing. the program is not to be developped in Java, this is a strict constraint, so even though I don't exactly know the range of operations handled by JBits it cannot be used at any stage in my situation. Thanks a million for your help :-) Yves.Article: 41092
Austin Franklin wrote: > > Out of curiosity, why do you want a single symbol for one of these huge > parts? Wouldn't you be better off with multiple symbols, each symbol a > separate (or related multiple even) design function? Or better still, if the board layout tools would accept text symbols and netlists as an option to schematics only. -- Mike TreselerArticle: 41093
I'm attempting to program an XC4010E via JTAG using an XChecker cable and the JTAG programming tool that comes with Foundation 2.1i. The JTAG programmer reports success and the DONE pin on the XC4010 goes high, however none of the pins on the 4010 become active. It looks like the programming doesn't quite complete for some reason. However, if I include the BSCAN component, along with the TDI/TDO/TMS/TCK pads, in my original design then everything works perfectly. Is this expected behavior? The datasheet seems to imply that you don't need to include the BSCAN component unless you want to use JTAG in your design - it doesn't say anything about it being required for JTAG programming. This is kind of annoying because with BSCAN and TDI/TDO/TMS/TCK included in my design I can't use those four I/O pins for anything else, and I can't afford to loose those pins. Any advice would be appreciated! Thanks, Bob ArmstrongArticle: 41094
You can also avoid screwing around with the select map interface by either using SRL16's in place of LUTs in your state machine. As long as the connections remain the same, you can reload the state map by reloading the SRL16's. The SRL16's act the same as LUTs when they are not being written to. The advantage is it makes your "reconfiguration" simulatable with the standard tools flow, and it is one less thing to mess with in the design. Steve Casselman wrote: > It's not easy but it's not impossible either. I took a ram based C > programmable state machine that I developed and was able to update the > control store via the select map in real time while the device was running. > Just read xapp151. If your really thinking about making your own software > type > xdl -pips -report v50 > > SteveArticle: 41095
The quiescent for the xc2s50e is 200mA: http://www.support.xilinx.com/partinfo/ds077_3.pdf pg. 2 -PatrickArticle: 41097
Goran,
No luck with that. I even rounded the period to 40ns so it would be =
divisible by 4 (since I have two DLLs cascaded).
-Kevin
"Goran Bilski" <goran@xilinx.com> wrote in message =
news:3C99089E.57DA27B5@xilinx.com...
Hi,
I actually run in to this problem a little while ago.
The reason for the huge timing delays is when you are using DLL and =
has a clock period constraint that
has many decimals. I think that there are some rounding errors in the =
timing tools.
So just change your clock period to 41 ns and the problem should go =
away
G=F6ran
Article: 41098Why are you driving your timer with a different clock then your processor that is reading it? shengyu_shen@hotmail.com (ssy) wrote in message news:<f4a5f64f.0203191658.cbeb868@posting.google.com>... > Hi everyone > > I am using synplicity 6.2.4 to syn and quartus II 1.1 to P&R, > in my design, there are two clock, one is 25Mhz to drive the cpu, the > other is 33Mhz to drive the timer, this two clock do not have any > relation > > in the timer, the counter can be driven by 25Mhz clock or 33Mhz clock, > so I use a controll bit to select them, then use the result to drive > counter > > so when quartus finish his work, he tell me that my design may not > function, and 1300 path can not be operational becasue their clock > skew larger than logic delay. > > I think the clock mux will make the clock signal go down the clock > net, and become a logic signal, and then drive the FF > > how to deal with this?Article: 41099
> Make sure the 25MHz is assigned to a global clock pin > and that the counter output is resynched to the 33 MHz > clock before it is read. but how to resynched to 33Mhz? and my problem is that: the muxed clock go down the clock tree, and become an logic signal,
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