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Mikeandmax wrote: > Hi Rick- > none taken - I agre with you, sometimes you finish downloading all that stuff > just to find 'no fit' . With most of "our" products - brand A, brand X and > Lattice included - a product brief is downloadable, <200k. What is more useful > is to talk with someone, I hope your conversation with the 'local guy' - Stacy > Deming - helped you avoid some time spent. > > good luck with your project- Yes, Stacy helped me figure out the important issues without having to spend time figuring out a web page and data sheet. That's what FAEs are for. But I don't agree that the A and X web sites offer product overviews. At least they don't have anything to offer me. I get stuff from X all the time that is just circular file material. They talk about longer, lower, wider without telling you any of the stuff that engineers want to know. For example, here is an excerpt from the X web site on "Choosing a Xilinx CPLD That's Right For You!" CoolRunner XPLA3- The CoolRunner XPLA3 product families offer extreme low power making them the leaders in an all new market segment for CPLDs - portable electronics. With standby current in the low micro amps and minimal operational power consumption, these parts are ideal for any application is that is especially power sensitive, for example, battery powered applications. I get nothing from this and know that it will be two or three more clicks before I can get any tecnical info. The real problem is not how many clicks I have to make to get to the technical stuff, it is the lack of organization of the data into a useful form. They then give me separate links to click on to get further info on each family, but I still know nothing about what is different between the families! So which do I click on, A... B... C? If I really want to compare them, the right answer is "ALL OF THE ABOVE". What a waste of time. If they just gave me all of the significant data like speed, power, density, packages, etc... in a single place, I would be done right now! This was not meant to be a rant against Xilinx or any other individual company. This is a complaint about how marketing has taken precedence over the distribution of information to engineers (especially on the web sites) and made our jobs harder rather than easier. Just don't get me started about the Asian company web sites!!! (I know they make semiconductors... they must be in here somewhere...) -- Rick "rickman" Collins rick.collins@XYarius.com Ignore the reply address. To email me use the above address with the XY removed. Arius - A Signal Processing Solutions Company Specializing in DSP and FPGA design URL http://www.arius.com 4 King Ave 301-682-7772 Voice Frederick, MD 21701-3110 301-682-7666 FAXArticle: 41226
acher@in.tum.de (Georg Acher) writes: > In article <m3vgbo6gp1.fsf@scimul.dolphinics.no>, > Petter Gustad <newsmailcomp1@gustad.com> writes: > <coregen troubles> > |> It almost worked. It appears that all dialog boxes have the bottom ok, > |> cancel, etc. buttons missing... You said it, crash everywhere... > > This can be a font problem in the Swing libraries... What JDK/JRE-version are you Most likely. This might also be why I can't run it off the SUN JRE on the SPARC. > running? I have no problems with java version "1.3.0" on a Suse7.2-system. It was jdk1.3.1 under Red-Hat 7.2. However, it worked fine on my PC at home, an old Slackware with the same JRE. Thanks for your hints. Petter -- ________________________________________________________________________ Petter Gustad 8'h2B | (~8'h2B) - Hamlet in Verilog http://gustad.comArticle: 41227
I don't know what your quantities or budget are, but the SpartanXL series might be an option in the smallest size(XCS05XL-????). It does tolerate 5 volts on the I/O pins. In very small quantities it is about $10 US (plus some sort of configuration hardware.) As an alternative, doesn't the Spartan2 support 5v i/o? It is a little cheaper but the configurator is more expensive. Good luck, Theron Hicks rickman wrote: > Mikeandmax wrote: > > Hi Rick- > > none taken - I agre with you, sometimes you finish downloading all that stuff > > just to find 'no fit' . With most of "our" products - brand A, brand X and > > Lattice included - a product brief is downloadable, <200k. What is more useful > > is to talk with someone, I hope your conversation with the 'local guy' - Stacy > > Deming - helped you avoid some time spent. > > > > good luck with your project- > > Yes, Stacy helped me figure out the important issues without having to > spend time figuring out a web page and data sheet. That's what FAEs are > for. > > But I don't agree that the A and X web sites offer product overviews. > At least they don't have anything to offer me. I get stuff from X all > the time that is just circular file material. They talk about longer, > lower, wider without telling you any of the stuff that engineers want to > know. > > For example, here is an excerpt from the X web site on "Choosing a > Xilinx CPLD That's Right For You!" > > CoolRunner XPLA3- The CoolRunner XPLA3 product families > offer extreme low power making them the leaders in an all > new market segment for CPLDs - portable electronics. With > standby current in the low micro amps and minimal > operational power consumption, these parts are ideal for any > application is that is especially power sensitive, for example, > battery powered applications. > > I get nothing from this and know that it will be two or three more > clicks before I can get any tecnical info. The real problem is not how > many clicks I have to make to get to the technical stuff, it is the lack > of organization of the data into a useful form. They then give me > separate links to click on to get further info on each family, but I > still know nothing about what is different between the families! So > which do I click on, A... B... C? If I really want to compare them, > the right answer is "ALL OF THE ABOVE". What a waste of time. If they > just gave me all of the significant data like speed, power, density, > packages, etc... in a single place, I would be done right now! > > This was not meant to be a rant against Xilinx or any other individual > company. This is a complaint about how marketing has taken precedence > over the distribution of information to engineers (especially on the web > sites) and made our jobs harder rather than easier. Just don't get me > started about the Asian company web sites!!! (I know they make > semiconductors... they must be in here somewhere...) > > -- > > Rick "rickman" Collins > > rick.collins@XYarius.com > Ignore the reply address. To email me use the above address with the XY > removed. > > Arius - A Signal Processing Solutions Company > Specializing in DSP and FPGA design URL http://www.arius.com > 4 King Ave 301-682-7772 Voice > Frederick, MD 21701-3110 301-682-7666 FAXArticle: 41228
Stephane, Dunno about chipscope but if you want to wiggle and monitor pins I suggest you look at ianjtag, a project on sourceforge and Intel's JFlash utility used for writing flash. Jon In article <3C9B4C78.B6D2CA06@irisa.fr>, sguyetanREMOVE@irisa.fr (=?iso-8859-1?Q?St=E9phane?= Guyetant) wrote: > Hi, > > I've got a Xilinx JTAG cable (on serial port) and I'd like to debug > with > chipscope-like features under Linux. > Any link on available linux/unix software would be very helpful, > even if I have to buy another JTAG cable. > > Thanks, > StephaneArticle: 41229
On Fri, 22 Mar 2002 12:01:17 -0800, Eric Crabill <eric.crabill@xilinx.com> wrote: > Each data set consists of 16 pieces of data, each piece of data is > 32-bits > (but I'm only sorting on a specific 4-bit field in the data, the rest of > the data just goes along for the ride...) If you're sorting on a such a narrow field (4-bit sounds narrow to me), why not go with a radix sort? The 4-bit field indexes one of 16 FIFOs, where the data value is inserted (16 pieces, so 16 or 32 clocks). The following state then dequeues the FIFOs one at a time and stores the values into memory (or whereever they go) (maybe 48 clocks). KellyArticle: 41230
Sounds like the best approach for the parts he's dealing with. The sort algorithms I looked at suggest the one-step sort would be a bin sort (sorting into bins, not "binary" sort) as opposed to a multistep approach that illustrated the radix sort mechanism (e.g. first sort into 4 bins based on two least significant bits then resort these in order based on the two most significant bits). It seems like one would need different sets of FIFOs needed for each incoming set to run in parallel until the sort is complete - can't quite use one FIFO set to cover a new set ever 10 ns. A more parallel approach might give similar results to the radix without the serial nature: generate a field of 16x16 bits where each input identifies its rank out of 16 as a bit select in a column. The indicies are then ordered scanning the rows in order. It's not exceedingly simple to grab 16 indicies based on 256 bits, but it's conceptually straightforward. Kelly Hall wrote: > On Fri, 22 Mar 2002 12:01:17 -0800, Eric Crabill <eric.crabill@xilinx.com> wrote: > > Each data set consists of 16 pieces of data, each piece of data is > > 32-bits > > (but I'm only sorting on a specific 4-bit field in the data, the rest of > > the data just goes along for the ride...) > > If you're sorting on a such a narrow field (4-bit sounds narrow to me), > why not go with a radix sort? The 4-bit field indexes one of 16 FIFOs, > where the data value is inserted (16 pieces, so 16 or 32 clocks). The > following state then dequeues the FIFOs one at a time and stores the > values into memory (or whereever they go) (maybe 48 clocks). > > KellyArticle: 41231
Yes, I just finished looking at that. There is quite a discrepance between the pricing that Xilinx lists on their web page for HUGELY high volumes and the prices we little people get. I saw $5.50 for an XCS30XL on the Xilinx promo page and >$30 at Avnet for 100. I found that the pricing could work for the XCS05XL or even the XCS10XL, but they don't offer industrial temps in the really small packages. I they have an industrial XCS05XL in the VQ100, but there is not enough IO and I would need to use two of them which still works on price, but not on board space. :( But there is good news... See my other posts at the end of this thread. And Thanks Betsy! Theron Hicks wrote: > > I don't know what your quantities or budget are, but the SpartanXL series might be an > option in the smallest size(XCS05XL-????). It does tolerate 5 volts on the I/O > pins. In very small quantities it is about $10 US (plus some sort of configuration > hardware.) As an alternative, doesn't the Spartan2 support 5v i/o? It is a little > cheaper but the configurator is more expensive. > > Good luck, > Theron Hicks > > rickman wrote: > > > Mikeandmax wrote: > > > Hi Rick- > > > none taken - I agre with you, sometimes you finish downloading all that stuff > > > just to find 'no fit' . With most of "our" products - brand A, brand X and > > > Lattice included - a product brief is downloadable, <200k. What is more useful > > > is to talk with someone, I hope your conversation with the 'local guy' - Stacy > > > Deming - helped you avoid some time spent. > > > > > > good luck with your project- > > > > Yes, Stacy helped me figure out the important issues without having to > > spend time figuring out a web page and data sheet. That's what FAEs are > > for. > > > > But I don't agree that the A and X web sites offer product overviews. > > At least they don't have anything to offer me. I get stuff from X all > > the time that is just circular file material. They talk about longer, > > lower, wider without telling you any of the stuff that engineers want to > > know. > > > > For example, here is an excerpt from the X web site on "Choosing a > > Xilinx CPLD That's Right For You!" > > > > CoolRunner XPLA3- The CoolRunner XPLA3 product families > > offer extreme low power making them the leaders in an all > > new market segment for CPLDs - portable electronics. With > > standby current in the low micro amps and minimal > > operational power consumption, these parts are ideal for any > > application is that is especially power sensitive, for example, > > battery powered applications. > > > > I get nothing from this and know that it will be two or three more > > clicks before I can get any tecnical info. The real problem is not how > > many clicks I have to make to get to the technical stuff, it is the lack > > of organization of the data into a useful form. They then give me > > separate links to click on to get further info on each family, but I > > still know nothing about what is different between the families! So > > which do I click on, A... B... C? If I really want to compare them, > > the right answer is "ALL OF THE ABOVE". What a waste of time. If they > > just gave me all of the significant data like speed, power, density, > > packages, etc... in a single place, I would be done right now! > > > > This was not meant to be a rant against Xilinx or any other individual > > company. This is a complaint about how marketing has taken precedence > > over the distribution of information to engineers (especially on the web > > sites) and made our jobs harder rather than easier. Just don't get me > > started about the Asian company web sites!!! (I know they make > > semiconductors... they must be in here somewhere...) > > > > -- > > > > Rick "rickman" Collins > > > > rick.collins@XYarius.com > > Ignore the reply address. To email me use the above address with the XY > > removed. > > > > Arius - A Signal Processing Solutions Company > > Specializing in DSP and FPGA design URL http://www.arius.com > > 4 King Ave 301-682-7772 Voice > > Frederick, MD 21701-3110 301-682-7666 FAX -- Rick "rickman" Collins rick.collins@XYarius.com Ignore the reply address. To email me use the above address with the XY removed. Arius - A Signal Processing Solutions Company Specializing in DSP and FPGA design URL http://www.arius.com 4 King Ave 301-682-7772 Voice Frederick, MD 21701-3110 301-682-7666 FAXArticle: 41232
Austin Lesea wrote: > > Rick, > > I have asked my friends in CPLD-land here at Xilinx to contact you. They rely > on Peter or myself to alert them to CPLD issues on this newsgroup. > > Let me know if they don't! > > I would answer if I could, > > Austin Well, Austin, your friends did call and I have been saved! Betsy T, the coolrunner product manager called and is sending me three chips in the industrial temp as engineering samples :) The story is that the XCR3384XL was planned to go in the CS280 alongside the XCR3256XL part. But the die is just too big to fit. So they are putting both the parts in the FT256 package, but of course the XCR3256XL will be last since it is already out in the smaller CS280 package. There were even some other issues having to do with moving things from the Philips facility to the Xilinx plants, but that was really complicated. The bottom line is that I will be able to get my prototypes built at the end of April, assuming that I keep up my end of the development schedule. Now if I can just get someone at Xilinx to support partial reconfiguration on the Spartan II family I will become rich and famous and live a full and productive life! Thanks again, Betsy! -- Rick "rickman" Collins rick.collins@XYarius.com Ignore the reply address. To email me use the above address with the XY removed. Arius - A Signal Processing Solutions Company Specializing in DSP and FPGA design URL http://www.arius.com 4 King Ave 301-682-7772 Voice Frederick, MD 21701-3110 301-682-7666 FAXArticle: 41233
Rick, Ask, and we shall at least try. I am happy it worked out. Austin rickman wrote: > Austin Lesea wrote: > > > > Rick, > > > > I have asked my friends in CPLD-land here at Xilinx to contact you. They rely > > on Peter or myself to alert them to CPLD issues on this newsgroup. > > > > Let me know if they don't! > > > > I would answer if I could, > > > > Austin > > Well, Austin, your friends did call and I have been saved! Betsy T, the > coolrunner product manager called and is sending me three chips in the > industrial temp as engineering samples :) > > The story is that the XCR3384XL was planned to go in the CS280 alongside > the XCR3256XL part. But the die is just too big to fit. So they are > putting both the parts in the FT256 package, but of course the XCR3256XL > will be last since it is already out in the smaller CS280 package. > There were even some other issues having to do with moving things from > the Philips facility to the Xilinx plants, but that was really > complicated. > > The bottom line is that I will be able to get my prototypes built at the > end of April, assuming that I keep up my end of the development > schedule. > > Now if I can just get someone at Xilinx to support partial > reconfiguration on the Spartan II family I will become rich and famous > and live a full and productive life! > > Thanks again, Betsy! > > -- > > Rick "rickman" Collins > > rick.collins@XYarius.com > Ignore the reply address. To email me use the above address with the XY > removed. > > Arius - A Signal Processing Solutions Company > Specializing in DSP and FPGA design URL http://www.arius.com > 4 King Ave 301-682-7772 Voice > Frederick, MD 21701-3110 301-682-7666 FAXArticle: 41234
So far they have only told us what is in the hat. Let's wait to see what they really pull out. Recent history has once again demonstrated that the performance numbers presented in a product announcement can't always be matched by the silicon when it finally comes along. Let's hope that the numbers in the announcement pan out, but for now a healthy dose of skepticism wouldn't hurt anyone. Mikeandmax wrote: > Ray pointed out- > >Not yet, so far they are only available on marketing slides. > > > >Peter Lang wrote: > > > >> > >> Anybody using already the Stratix devices? > >> Any Comments? > > but Ray, they are really high performance slides! > > Mike ThomasArticle: 41235
I found a new product that provides a very simple boundary scan interface for very simple debugging of BGAs and other hard to probe parts. You can see information on it at: http://www.insight-electronics.com/uscan/ I find this page to be PITA along with the entire Memec suite of web pages. or http://www.universalscan.com/ This is the company that makes the interface and software. It seems to allow you to set outputs to a 1 or a 0 and to look at inputs in pseudo real time. I was told that it updates at about a 10 Hz rate. The more I thought about it, the more I realized that this might be useful for finding a fault on a board with BGAs or even fine pitch devices. It is $700, so it is not exactly a gimme in terms of being cheap enough to toss if it doesn't do what you want. And they want another $700 for a second probe even though you don't need a second eval board to go with it. Any comments? Anyone using this device? Anyone using boundary scan??? I am finding that boundary scan has been pushed off to the land of million piece runs due to the high initial investment. Maybe my next product will be JTAG tools!!! -- Rick "rickman" Collins rick.collins@XYarius.com Ignore the reply address. To email me use the above address with the XY removed. Arius - A Signal Processing Solutions Company Specializing in DSP and FPGA design URL http://www.arius.com 4 King Ave 301-682-7772 Voice Frederick, MD 21701-3110 301-682-7666 FAXArticle: 41236
rickman wrote: > > Jim Granville wrote: > > > > There is no exact match, if you need all the pins and registers. > > The Atmel ATF1508ASVL has 128MC, but can pack more into a macrocell. > > It does have low static Icc. > > Newest Lattice MAC devices are 1.8/2.5V so 5V io is out... > > -jg > > Thanks for the advice. But I need 200+ macrocells and will need 140+ > IOs. I also HAVE to have the 5 volt tolerance. If it wern't for that, > I could leave this part off the board and use a couple of 16 bit buffer > chips for the inter-processor interfaces. A PC/104 interface requires > some 6 or 7 - 16 bit buffer chips which are way far larger than the > FT256 or CS280 packages. > > I considered an FPGA, but all the Xilinx devices that have 5 volt > tolerance are not very cheap and/or won't run off of 3.3 volts. :( Seems costly use of programmable logic. I have not checked the voltage flow details, but how about something like http://www.fairchildsemi.com/pf/FS/FST34X245.html ( a QSOP80 32 bit BUS switch ) alongside a smaller/cheaper CPLD ? -jgArticle: 41237
rickman wrote: Betsy T, the coolrunner product manager called and is sending me three chips in the industrial temp as engineering samples :) > The bottom line is that I will be able to get my prototypes built at the > end of April, assuming that I keep up my end of the development > schedule. > > Now if I can just get someone at Xilinx to support partial > reconfiguration on the Spartan II family I will become rich and famous > and live a full and productive life! Glad to hear that we could help. Now, what do you need for partial reconfig ? I am involved in a Virtex-II design that totally relies on partial reconfiguration How do you want to go about it ? I suppose you understand the basics: Reconfigure one complete frame at a time. Neither more nor less... As you saw, we will do (almost) anything to make you "rich and famous"... :-) Peter AlfkeArticle: 41238
They have to learn how to spell it first :-)
rickman wrote:
> Now if I can just get someone at Xilinx to support partial
> reconfiguration on the Spartan II family I will become rich and famous
> and live a full and productive life!
>
--
--Ray Andraka, P.E.
President, the Andraka Consulting Group, Inc.
401/884-7930 Fax 401/884-7950
email ray@andraka.com
http://www.andraka.com
"They that give up essential liberty to obtain a little
temporary safety deserve neither liberty nor safety."
-Benjamin Franklin, 1759
Article: 41239I'm not sure how to sort the values, but I'd manipulating only the 4-bit fields and sending the rest of the data through SRL delay lines while you're sorthing the fields. That will save some gates. "Eric Crabill" <eric.crabill@xilinx.com> wrote in message news:3C9B8D8D.D9DA1A2D@xilinx.com... > > Hi, > > Each data set consists of 16 pieces of data, each piece of data is > 32-bits > (but I'm only sorting on a specific 4-bit field in the data, the rest of > the data just goes along for the ride...) > > When I initially searched the web, I found all sorts of exotic methods, > I'm just looking for something simple to implement, and fast (~100 MHz), > and don't care too much about the latency or size of the resulting > design. > > Thanks! > Eric > > John_H wrote: > > > > Sorts aren't easy. > > > > Do a google search for sorting algorithms and you'll find all sorts of > > sorts out there mostly optimized for computing. The parallel algorithms > > may be harder to find - I haven't gotten a good reference yet. > > > > What's the design data set size and clock frequency? For 16 data sets > > in and 16 data sets out, that's a bunch of pins! Then do you just want > > the data output or the indicies to know what the channel order was? > > It's a mess in the general sense. > > > > A quick stab for me would be an insertion sort (easy to understand from > > a quick google search) if your clock rate is too fast for multiplexing > > the comparisons. The insertion sort would need about 14 SRL sets, > > (16*15)/2=120 comparators, 30 20-1 and 105 3-1 registered multiplexers. > > Uuuuuhgly. But it may be better than the bubble sort's 113 comparators > > (est) and 113 2-1 swap registers (complementary 2-1 multiplex registers) > > with 14 register sets mixed in the middle. > > > > Have fun with this! > > > > Eric Crabill wrote: > > > > > Hi, > > > > > > I am looking to build a circuit for sorting small data sets, > > > and am hoping someone here might have some pointers for where > > > I should start looking for algorithms to do it. > > > > > > My desire is to build a circuit to do the following: > > > > > > Every cycle, 16 pieces of data are provided as input. > > > Some number of cycles later, the data set is provided > > > at the output, sorted... > > > > > > The latency isn't a big issue, as long as it is constant, > > > and I can provide a new data set to the circuit every cycle. > > > > > > Thanks, > > > EricArticle: 41240
Greetings all, I wonder if there would be other good sites like Questlink or the former findparts.com out there? (Whatever happened to findparts.com electronic components search engine?) Can anyone recommend one? I need to check the availability and/or datasheets accross multiple parts vendors. Thanks, YuryArticle: 41241
You might consider checking Personal JTAG at: http://www.rsn-tech.co.uk/pjtag The interface can be done via the parallel port. Can't get less expensive than that! If you want more information on JTAG in general, I'd recommend the Web sites at Corelis and JTAG Technology - lots of articles and application notes to download. The full-blown boundary scan hardware & software packages can go deep into 5 digit prices, but you can get started with just an investment of time. Have fun! Jim HornArticle: 41242
Ray Andraka <ray@andraka.com> wrote in message news:<3C9BC037.7597BABA@andraka.com>... > So far they have only told us what is in the hat. Let's wait to > see what they really pull out. Recent history has once again > demonstrated that the performance numbers presented in a product > announcement can't always be matched by the silicon when it > finally comes along. Let's hope that the numbers in the > announcement pan out, but for now a healthy dose of skepticism > wouldn't hurt anyone. > > Mikeandmax wrote: > > > Ray pointed out- > > >Not yet, so far they are only available on marketing slides. > > > > > >Peter Lang wrote: > > > > > >> > > >> Anybody using already the Stratix devices? > > >> Any Comments? > > > > but Ray, they are really high performance slides! > > > > Mike Thomas Well, it's in the Quartus software. Also, Synplicity and Mentor already have support for it... that's more than powerpoint. There's a Stratix tutorial in the software too. And a datasheet. I think you should be able to get a reasonably accurate view of the device by using the software and the documentation.Article: 41243
I am the new age guy, thus when I first encounter these tools, they are pretty mature and do things correctly, I think they are so for all my small designs. Probably later for larger designs these do occur. -- Best Regards, ----------------------------------------------------------------- Xu Qijun Engineer OKI Techno Centre (S) Pte Ltd Tel: 770-7049 Fax: 779-1621 Email: qijun@okigrp.com.sg "Spam Hater" <spam_hater_7@email.com> wrote in message news:3c9b5116.4362136@64.164.98.7... > > Now you have some experience. > > I have found errors in chips that gate-level simulation did not catch. > > I have found errors in gate-level simulation that the simulator did > not catch. > > That's why all these tools exist! > > > > On Fri, 22 Mar 2002 08:39:51 +0800, "Kelvin Hsu" <qijun@okigrp.com.sg> > wrote: > > >huh... > >well...my experience was that everytime RTL and gatelevel simulation match, > >thus > >later i overlook gate level simulation and skipped them anyway. > > >Article: 41244
Timing numbers in the software don't mean squat until the silicon is characterized and the
measured parameters are back-annotated into the speed files used to generate the timing
reports in software. Of course the tools are in place, you need them in order to be able
to have sockets to put the parts in when the silicon arrives. My point is that the
reality etched in the silicon often does not align with the expectations set by marketing
and bolstered by simulations before the real thing is available. Deep submicron design is
not trivial, and design mistakes get made that can either disable or significantly impair
features. Recently introduced FPGA families are replete with examples of functions that
did not work correctly or that did not come even close to the performance numbers
trumpeted by the marketing department before the device was available.
Girl wrote:
> Ray Andraka <ray@andraka.com> wrote in message news:<3C9BC037.7597BABA@andraka.com>...
> > So far they have only told us what is in the hat. Let's wait to
> > see what they really pull out. Recent history has once again
> > demonstrated that the performance numbers presented in a product
> > announcement can't always be matched by the silicon when it
> > finally comes along. Let's hope that the numbers in the
> > announcement pan out, but for now a healthy dose of skepticism
> > wouldn't hurt anyone.
>
>
> Well, it's in the Quartus software. Also, Synplicity and Mentor
> already have support for it... that's more than powerpoint. There's a
> Stratix tutorial in the software too. And a datasheet. I think you
> should be able to get a reasonably accurate view of the device by
> using the software and the documentation.
--
--Ray Andraka, P.E.
President, the Andraka Consulting Group, Inc.
401/884-7930 Fax 401/884-7950
email ray@andraka.com
http://www.andraka.com
"They that give up essential liberty to obtain a little
temporary safety deserve neither liberty nor safety."
-Benjamin Franklin, 1759
Article: 41245Peter Alfke wrote: > > rickman wrote: > Betsy T, the coolrunner product manager called and is sending me three chips in the > industrial temp as engineering samples :) > > > The bottom line is that I will be able to get my prototypes built at the > > end of April, assuming that I keep up my end of the development > > schedule. > > > > Now if I can just get someone at Xilinx to support partial > > reconfiguration on the Spartan II family I will become rich and famous > > and live a full and productive life! > > Glad to hear that we could help. > Now, what do you need for partial reconfig ? > I am involved in a Virtex-II design that totally relies on partial reconfiguration > How do you want to go about it ? > I suppose you understand the basics: > Reconfigure one complete frame at a time. Neither more nor less... > > As you saw, we will do (almost) anything to make you "rich and famous"... :-) > > Peter Alfke My first step is to get a board designed and out the door. I can do a single FPGA design for my initial AIOmodule and worry about the partial reconfig later. Unless there are things I need to do in my pinout so that I don't make life difficult later? What exactly is a Frame? Does this correspond to a section of hardware? I expect that I should make my pinout match the Frame boundaries. On the last board we supported multiple AIOmodule interfaces by having separate FPGAs for each interface. I want to do the same thing, but I only have one FPGA. I don't need to download while any part of the FPGA is running. I am looking to modularize the download so that I can mix and match pieces for the download to match the hardware that is installed. If I try to have separate downloads for every hardware combination, there will be hundreds or even thousands of combinations that will each have to be designed and tested. If I use separate modules for each interface, they can be installed at boot time as the board is brought up and I only have to do 4 P&R for each module type (one P&R for each AIOmodule position. I have not done much research on the partial reconfig. Once I read that it currently is only being done for the Virtex or VII parts ( I can't remember exactly which, but it did not include Spartan of any kind). But now I can't find any mention of it on the Xilinx web pages. Did I imagine this??? -- Rick "rickman" Collins rick.collins@XYarius.com Ignore the reply address. To email me use the above address with the XY removed. Arius - A Signal Processing Solutions Company Specializing in DSP and FPGA design URL http://www.arius.com 4 King Ave 301-682-7772 Voice Frederick, MD 21701-3110 301-682-7666 FAXArticle: 41246
Jim Granville wrote: > > rickman wrote: > > > > Jim Granville wrote: > > > > > > There is no exact match, if you need all the pins and registers. > > > The Atmel ATF1508ASVL has 128MC, but can pack more into a macrocell. > > > It does have low static Icc. > > > Newest Lattice MAC devices are 1.8/2.5V so 5V io is out... > > > -jg > > > > Thanks for the advice. But I need 200+ macrocells and will need 140+ > > IOs. I also HAVE to have the 5 volt tolerance. If it wern't for that, > > I could leave this part off the board and use a couple of 16 bit buffer > > chips for the inter-processor interfaces. A PC/104 interface requires > > some 6 or 7 - 16 bit buffer chips which are way far larger than the > > FT256 or CS280 packages. > > > > I considered an FPGA, but all the Xilinx devices that have 5 volt > > tolerance are not very cheap and/or won't run off of 3.3 volts. :( > > Seems costly use of programmable logic. I have not checked the > voltage flow details, but how about something like > http://www.fairchildsemi.com/pf/FS/FST34X245.html > ( a QSOP80 32 bit BUS switch ) > alongside a smaller/cheaper CPLD ? > > -jg I don't see how this could help. I need about 90 IOs for the PC/104 interface. I can mux this through a single part or I can use a lot of separate buffers that all have to duplicate the low voltage connection which will use more pins and board space. I would love to save a few bucks on the CPLD, but there is no space on the board. This part acutally has enough extra pins to let me eliminate some buffers I was going to add to isolate the always powered section of the board from the power switched section of the board. The commercial temp version of the XCR3256 is only $14. I don't see how I can save much more on that by adding large buffer chips. -- Rick "rickman" Collins rick.collins@XYarius.com Ignore the reply address. To email me use the above address with the XY removed. Arius - A Signal Processing Solutions Company Specializing in DSP and FPGA design URL http://www.arius.com 4 King Ave 301-682-7772 Voice Frederick, MD 21701-3110 301-682-7666 FAXArticle: 41247
You can try partminer.com. You will need to register which is not painful. It searches some 20 or so sites fairly well. I find that sometimes it will not return a hit that I can get if I go to distis direct. It is also a bit slow and it will time out and require you to log in again after 20 mins or so of inactivity. Arrow is not one of the sites searched, likely because Arrows wants you to log in so they can track your interests. But Insight also requires you to log in and they are searched by partminer. Yury wrote: > > Greetings all, > I wonder if there would be other good sites like Questlink or > the former findparts.com out there? > > (Whatever happened to findparts.com electronic components search > engine?) > > Can anyone recommend one? I need to check the availability and/or > datasheets accross multiple parts vendors. > > Thanks, > Yury -- Rick "rickman" Collins rick.collins@XYarius.com Ignore the reply address. To email me use the above address with the XY removed. Arius - A Signal Processing Solutions Company Specializing in DSP and FPGA design URL http://www.arius.com 4 King Ave 301-682-7772 Voice Frederick, MD 21701-3110 301-682-7666 FAXArticle: 41248
Hello, I am working on an asynchronous fifo (Xiliinx coregen 3.1) which uses separate clocks(both 100MHz) for read/write and getting read error or write error flag asserted when I simulate with various different phases between two clocks even though read enable ot write enable signal has enough setup time.. Any advice?Article: 41249
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Goran,
You're right... I thought this didn't work because I changed the period =
in the UCF to an integer and saw no difference but forgot that I had a =
period constraint in the NCF too so I just deleted the NCF.
Thanks a lot... you save me a lot of time.
But since you're from Xilinx maybe I can complain a bit... how come I =
have version 4.2 and this problem still persists? Am I the only person =
that uses noninteger periods?
-Kevin
"Goran Bilski" <goran@xilinx.com> wrote in message =
news:3C99089E.57DA27B5@xilinx.com...
Hi,
I actually run in to this problem a little while ago.
The reason for the huge timing delays is when you are using DLL and =
has a clock period constraint that
has many decimals. I think that there are some rounding errors in the =
timing tools.
So just change your clock period to 41 ns and the problem should go =
away
G=F6ran
Kevin Neilson wrote:
All,I keep running into this problem all the time in which I have a =
route that misses my constraint by tens of thousands of nanoseconds. =
I'm using the Xilinx 4.1 PAR tools. In this case the bad paths are ones =
that cross from a domain with a 20ns period to a domain with a 10ns =
period. The faster domain is generated from a DLL locked to the first, =
so while it is twice the freq, it is synchronous to the first. I'm =
taking care to read data in the second domain only on "even" cycles of =
the first domain, so the data has 20ns to get from the slow domain to =
the fast.The first evidence of a problem comes during routing: End of =
iteration 1
22869 successful; 0 unrouted; (152088) REAL time: 5 mins 34 secs =
You've all cringed at seeing this message before. Then, in the PAR =
summary, I see =
this:--------------------------------------------------------------------=
------------
* PERIOD analysis for net "clk_management/f | 10.416ns | =
38591.280ns | 4
irclk_dcm_clk2x" derived from NET "clk_m | | =
|
anagement/CLK_ibufg" PERIOD =3D 41.667 nS | | =
|
HIGH 50.000000 % | | =
|
=
-------------------------------------------------------------------------=
-------This is obviously a problem: my constraint for the fast clock =
domain is 10.4ns, and one path requires 38591ns, meaning I need to slow =
my clock to the kilohertz range. Here's the detail from =
Trace:=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3DTiming constraint: PERIOD analysis for net =
"clk_management/firclk_dcm_clk2x" derived from NET =
"clk_management/CLK_ibufg" PERIOD =3D 41.667 nS HIGH 50.000000 % ; =
divided by 2.00 and duty cycle corrected to 10.416 nS HIGH 5.208 nS =
29336 items analyzed, 58 timing errors detected. Minimum period is =
38591.280ns.-------------------------------------------------------------=
-------------------Slack: -3.704ns (requirement - (data =
path - negative clock skew)) Source: dpll/theta[12] =
Destination: fir/phase_reclock[5] Requirement: =
0.001ns Data Path Delay: 3.705ns (Levels of Logic =3D 4) Negative =
Clock Skew: 0.000ns Source Clock: sclk rising at 216975.695ns =
Destination Clock: firclk rising at 216975.696ns Data Path: =
dpll/theta[12] to fir/phase_reclock[5] Location Delay =
type Delay(ns) Physical Resource =
Logical Resource(s) =
------------------------------------------------- ------------------- =
SLICE_X57Y32.YQ Tcko 0.568 theta[13] =
dpll/theta[12] =
SLICE_X54Y33.F1 net (fanout=3D3) 0.551 theta[12] =
SLICE_X54Y33.COUT Topcyf 0.769 fir/phase_reclock[2] =
=
fir/phase_reclock_qxu[2] =
fir/phase_reclock_cry[2] =
fir/phase_reclock_cry[3] SLICE_X54Y34.CIN net =
(fanout=3D1) 0.000 fir/phase_reclock_cry[3]/O SLICE_X54Y34.Y =
Tciny 1.446 fir/phase_reclock[4] =
fir/phase_reclock_cry[4] =
fir/phase_reclock_s[5] =
SLICE_X54Y34.DY net (fanout=3D1) 0.001 =
fir/phase_reclock_s[5] SLICE_X54Y34.CLK Tdyck =
0.370 fir/phase_reclock[4] =
fir/phase_reclock[5] =
------------------------------------------------- =
--------------------------- Total =
3.705ns (3.153ns logic, 0.552ns route) =
(85.1% logic, 14.9% =
route)-------------------------------------------------------------------=
------------- This is just whack. You can see that the path delay is =
3.7ns, which easily meets the 20ns period of the slow clock (sclk). =
However, for some reason it thinks the source clock is sclk rising at =
216975ns. Where did that come from? And how did it get a slack of =
-3.704ns? Also, where did the 38591ns period in the PAR summary come =
from? That's not even close to 216975. This path really shouldn't be =
analyzed at all. The Xilinx answer files state that 4.1i doesn't =
analyze paths that cross clock domains. Sometimes when I see this =
problem, I can "fool" PAR by putting a FROM-TO in the UCF that explicity =
states that paths from the "sclk" domain to the "firclk" domain have =
20ns. However, this isn't working now, and Trace claims that 0 items =
are analyzed using that TIMESPEC, even though there are obviously many =
paths that fit that description.Has anybody else seen this?-Kevin
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