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> Well, everything is in the title, what are the main differences between the > Virtex and Virtex II families of FPGA? > > regards, Cyrille Cyrille, I think the best way for you to find this out is to visit http://www.xilinx com and look around. If you are just looking around in general, you also might want to take a look at SpartanII devices, and the VirtexII-Pro (which includes an embedded PowerPC!) Here is an excerpt from Xilinx's FAQ (http://www.xilinx.com/products/virtex2/v2qa.pdf) to get you started... Q: What are the major innovations of Virtex-II family compared to previous Virtex families such as Virtex and Virtex-E? A: The Virtex-II family builds upon the success of the Virtex and Virtex-E families. The Virtex-II family includes industry leading features such as Digital Clock Managers (DCMs) and Select I/O-Ultra. The Virtex-II family is the first programmable logic device to include Xtreme Multipliers (18x18 hard multiplier blocks) and XCITE Technology (digitally controlled impedance). The Virtex-II family features a redesigned configurable logic block (CLB) that has twice the number of slices as the Virtex and Virtex-E families. The Virtex-II family offers increased system performance, a benefit of both the advanced 0.15-micron process and the Active Interconnect routing architecture. The Virtex-II family offers twice the ratio of embedded memory-to-logic as the Virtex and Virtex-E families. Virtex and Virtex-E designs can be directly re-synthesized, compiled, and targeted to the Virtex-II family. j.Article: 42001
Hi, If you are part of a university lab, you should fill out a donation request with the Xilinx University Program (XUP). I believe the Xilinx PCI Interface is something that they can donate... If you are not a faculty member, find one that is associated with your project and ask them to help. Eric Jason Zimmernann wrote: > > Just wanted to clarify a few things... > I work for a university lab, and this is a research project, not a > commercial product. Consequently, two main issues are driving my > decision. First, I must use the hardware that is available to me. > Which in this case contains a Xilinx part as the PCI interface. Other > people are working on other aspects of the project (networking and > security), and this is the platform we must all coexist on. Second, I > must really justify the cost if I don't use something that is freely > available. I am *hoping* that the opencores code can be used as > somewhat of a "black box", but with the Wishbone stuff replaced with a > different backend. > > Kevin, I appreciate the honesty, and also the fast reply. After our > experience (admittedly a long time ago) with another Open core, I > hesitate to use something off of that site. Getting the code to > synthesize was hard enough being that it was "someone else's code", > but on top of that we couldn't get it to work well enough for our > purposes so we wrote our own. I do not like to generalize about a > "movement", as it were, from one experience, and it really looks > attractive to have the PCI master logic already done--but then again, > once burned... > > j. > > p.s.: fyi, we may be moving to a VirtexII-based board in the future, > and i think i read somewhere that they want $15,000 for the newer PCI > core...which is a lot compared against my stipend... :)Article: 42002
chris wrote: [snip] > the last option would be to just buy/rent one of those ASIC > prototyping tools. these will be expensive though, but if your time to [snip] Are you referring to something like IKOS, or some other system. I've heard very good things about IKOS. I think you can rent the entry level box for $150K for 6 months. My problem is that the board needs to be portable for sales calls. It is not only for design debug/verification, but also for live demos. The emulation systems I've seen won't meet that constraint. Thanks, GilArticle: 42003
Thanks for your inputs. In my application I don't use gated clocks. I am interested in an FPGA with integrated ARM, but also need to consider that against the debug effort. On the proto board it may be nice to have access to the ARM bus for debug. If I were going to production with the FPGA I would be more in favor of the integrated solution. In my case, the discrete ARM chip has some advantages. Thanks, Gil Peter Ormsby wrote: > Gil, > > It might be worth your while to take a look at Altera's Excalibur ARM FPGA. > > It's a device that put an ARM 922T processor on the same die as a 100K, > 400K, or 1M marketing gate FPGA array (if you have good idea of the number > of registers in your design, it's better to use that to determine size > requirements rather than ASIC gates). Inside the Excalibur part, the ARM > will run at 200 MHz and is attached (via AMBA AHB bus) to 256K Bytes SRAM, > 128K Bytes dual-port SRAM, an SDRAM controller, a serial port, and several > other peripherals. The device is available today and Altera sells a > development board with the 1M gate version of the part on it. The > development board also has PMC connectors on it for expansion daughter > cards. You can get more details on Altera's web site. > > In case you're not familiar with the clocking differences between an FPGA > and an ASIC, I should point out that the much-used practice of gating clocks > in ASICs is generally a big no-no in FPGAs. Synplicty's Certify is a tool > which can convert gated-clocks in your design to the more FPGA-friendly use > of clock enables if you don't want to do it manually. There's sort of a > trade-off between keeping your design as close to your ASIC as possible > (gated clocks) and getting the most speed out of the FPGA (clock enables). > > -Pete- > > Gil Herbeck <gil@radix20.com> wrote in message > news:3CB61C7B.700@radix20.com... > >>I need to prototype an ASIC design and am looking for >>advice on type of FPGA and on FPGA board as well. >> >>The board needs to have an ARM9, external memory, an >>interface to a PC (serial is ok), the FPGA (or ASIC), >>and a header to plug in a daughter card with some pins >>routed to the FPGA. >> >>The ASIC will have between 100K and 500K ASIC Logic >>Gates. It will run at about 150 MHz. It needs about >>200 KB of internal RAM. And it will have a lot of >>multipliers. There will probably be some pipelining >>in the ASIC to meet speed - and probably deeper pipes >>in the FPGA. We want to match the FPGA to the ASIC >>as closely as possible. >> >>I think the key factors in FPGA selection are: >>- Capacity. We want to fit in one FPGA. >>- Performance. We want to run at speed. >>- "ASIC-like" synthesis library (see below)? >>- Availability of board described above. >> >>"ASIC-like" synthesis library... The datapath >>content on the ASIC may force us to use one of the >>datapath synthesis tools. These tools don't support >>FPGA architectures directly. I've heard that since >>the Actel architecture is "fine-grain" that it works >>best for these types of designs. >> >>Any advice will be much appreciated. >> >>Thanks, >>Gil >> >> > >Article: 42004
We do a functional simulation on the design source, and if there are either questions
about the synthesis not answerable by looking at the RTL analyst, or if it is for a
design that we will not be participating in the integration, or for macros, we will
simulate the mapped netlist out of synplify. That mapped netlist is a netlist using
only <insert any vendor beginning with "A" or "X"> primitives. Generally speaking, the
Xilinx mapper won't touch this netlist, the notable exceptions being for trimming unused
logic and duplicating tristate registers in IOBs. Both are functional simulations. The
mapped netlist 1) verifies the synthesized design works as intended and 2) serves as a
universally portable reasonably hard to decipher delivery mechanism for accurate
simulation models for IP. Unless we are having problems this is as far as we go in
simulation (ie, we don't typically use any of the simulation outputs from the Xilinx
tools).
If you are attempting to simulate to verify timing, it will generally require a
different set of vectors than that required to functionally check the design to be able
to qualitatively say that the design passes timing. This is especially true in
arithmetic intensive designs because arithmetic multiplies the number of possible signal
paths by a considerable factor. In complex designs, it may well take several times
longer than it took to do the design to properly assemble a comprehensive set of timing
simulation vectors, or may not even be possible.
We use a combination of RLOCs in our hierarchical code, the graphical floorplanner and
the UCF file. Stuff that is either instantiated several times in the design or is
reused in more than one design is usually RLOC'd in the source, which means
instantiating primitives rather than writing RTL code. This gives us bigger blocks to
work with in the graphical floorplanner, which in turn decreases the amount of time
needed to floorplan a design. We do get a fair amount of reuse out of the library of
modules this way, in fact our reuse numbers are quite a bit higher than what I hear in
the industry.
Unfortunately, I can't really recommend a good tutorial on how to do floorplanning. The
tools manuals tell you the mechanics of using the tools but are pretty sparse on advise
as to how one proceeds. Unfortunately floorplanning seems to be more of an art: some
people seem to have the knock, others never get it.
Theron Hicks wrote:
> Ray,
> Please enlighten me. In 4.1 the simulation options are
>
> 1. Simulate Behavioral VHDL Model
> 2. Simulate Post-Translate VHDL Model
> 3. Simulate Post-Map VHDL Model
> 4. Simulate Post-Place & Route VHDL Model
>
> Can you clarify what each of these really accomplishes?
>
> #1, I assume is simulation of the code as written and assumes delta delays
>
> I am uncertain as to precisely what #2 and #3 do.
>
> #4 I assume is the actually delays including routing, etc.
>
> If I understand correctly you use #3 as your last level of simulation.
>
> Also, you make a comment that seems to imply that the different levels of simulation
> require different test vectors. (I would have thought that each would use the same
> test vectors.) Is that because of the real world of chip delays vs. ideal delays?
>
> Another comment, I have seen some realy screwed up placements in the floorplanner.
> I assume that you must be floorplanning your designs quite carefully. How do you do
> that? (floorplanner vs. UCF vs. ??) If you are using something other than
> floorplanner, can you recommend a tutorial, etc.?
>
> Perhaps I should be just setting things up very carefully with the timing
> constraints. I am having trouble figuring how to set timing constraints for
> critical internal signals.--
--Ray Andraka, P.E.
President, the Andraka Consulting Group, Inc.
401/884-7930 Fax 401/884-7950
email ray@andraka.com
http://www.andraka.com
"They that give up essential liberty to obtain a little
temporary safety deserve neither liberty nor safety."
-Benjamin Franklin, 1759
Article: 42005Hello everybody, I am wondering what really the "Creat RPM" option in Xilinx Core Generator is for. It seems it enforces the placement tool to keep the relative location attributes of the LUTs and Slices. if so, then what is its real advantage? The problem I am having with RPMd multiplier core is that there are some unused slices in the RPMd core and it seems these resources are not being used even by other parts of the circuit. So, when I place and Route my design ( which contains hundreds of these multiplier cores) on Virtex 2000E the xilinx output file reports that almost 90% of the slices are being used but as the report says still only half of total LUTs are used. So, I think unchecking RPM option will free those unused slices but not sure what would be the effect on the timing of the circuit... any idea or guide for more efficient use of the logic? cheers, AhmadArticle: 42006
Peter Ormsby wrote:
>
> Kevin,
>
> This probably should be an off-line conversation, but since it appears that
> you want to go public with your personal issues that you seem to have with
> me, I guess I'll comply...
>
> Let's start with this:
>
> Kevin Brace <kevinbraceusenet@hotmail.com> wrote in message
> news:cc7b0b5f.0204021251.687e81d9@posting.google.com...
> > Peter, I find the things you mentioned somewhat unfair.
> > In Quartus II 2.0 Web Edition (the free version like the ISE WebPACK),
> > LogicLock is disabled. (and bunch of other things like Tcl scripting
> > are also disabled.)
> > Since the original poster is talking about ISE WebPACK here, I will
> > say that you shouldn't mention the features available only for the
> > paid version.
>
> The original poster had a problem. He did not specify that he was only
> interested in "free" solutions, only that he was looking for answers. I
> offered him one. I'm sorry that you didn't think it was a viable solution,
> but then again, you weren't the one looking for floorplanning help, so I
> don't see how you should be judging whether I should have mentioned it or
> not.
>
Well, here is how I will look at it.
The original poster was using ISE WebPACK, so likely this person cannot
afford the paid version.
I believe most people including myself who use these free tools use
it mainly for hobby projects because not too many people have the luxury
of paying a couple thousand dollars for the paid version.
So, if you tell him that Quartus II 2.0 supports LogicLock, he might
assume that QII 2,0 Web Edition which is free supports LogicLock.
Actually it doesn't (I didn't know that until I tried to see if
LogicLock was supported.), and he might feel cheated.
However, if you said, "If you are willing to subscribe to Altera
software subscription program which costs $2,000, you can use LogicLock
which let you . . ., and QII 2.0 WE doesn't support it. " in your reply,
then I probably would not have felt like you were being unfair.
You are right to some extent that to solve a particular issue, sometimes
money is not an issue, but I got the impression that this person wasn't
willing to spend $2,000 for software subscription, therefore I felt like
your solution was not realistic.
However, if LogicLock wasn't disabled in QII 2.0 WE, then I wouldn't
have had any problem with your solution to the problem.
> > I already did some manual floorplanning in QII 2.0 WE, and some
> > features like automatically displaying the routing delay on the screen
> > is nice, but it has its own problems like it lets me assign multiple
> > FFs to a single LE which shouldn't happen in the first place because
> > one LE has only one FF.
>
> The floorplanner doesn't let you assign anything to a specific LE. Since
> every LE in a LAB has essentially the same connection to the rest of the
> FPGA fabric,
Well, somehow I was able to assign as much as 4 FFs to a single
LE.
Yes, I do understand that's a no-no, but then why doesn't the
floorplanner prevent that from happening in the first place?
Is that supposed to be a bug or part of the feature?
I feel like it should be considered a bug or at least a mistake.
> it doesn't make a lot of sense to assign to that level of
> detail.
Most power users of this newsgroup seem like they haven't used
Altera's tools/devices lately because of poor low-level backend tool
support from Altera.
Altera attitude seems like users don't have to get too much in detail,
and let the tool handle it, but shouldn't Altera listen to those power
users?
> If you'll go back and take another look at it, you'll notice that
> all LE assignements get promoted to a LAB assignment. If you read the
> messages, it will tell you the same thing.
>
Yes, after some trials, I realized that I should just throw in
relevant FFs or LUTs into a LAB, and let the Fitter figure it out the
best location within it rather than assigning a FF or a LUT to a certain
LE within a LAB.
When I did so, the fitter somehow seems to complain that it can pack all
the specified FFs and LUTs within a LAB.
I really didn't understand why it was a problem. (I only assigned as
many as 4 FFs to a LAB.)
> As far as the rest of your tirade (both in this thread and the Queensbury
> Rules thread), let's make this all clear:
>
> I recieve absolutely no financial gain by reading or posting to this
> newsgroup. There is no one at Altera that told me to, or probably even
> knows that I post here, unless they've seen the postings here like you. My
> postings are done on my own time with my own computer equipment and they
> represent nothing more than my own opinion. As far as my employer goes,
> there is nothing in my job description or any of my performance review
> categories that has anything to do with this newsgroup. In summary: I don't
> get paid anything (directly or indirectly) to post here. However, in
> interest of full disclosure, I do own some Altera stock (and the stock of
> another programmable logic vendor too).
>
When I got a reply about my criticism of QII 2.0's fast fit
option from you, I felt like, "Why is this guy getting offended by my
this posting and my past postings about Altera's free tools?"
Sometime after that, I started to suspect that you are probably worked
at Altera.
I don't totally buy your explanation that your opinion isn't
influenced by your employer.
Anyone who owns technology related stocks probably remember how stock
analysts used to hype certain stocks.
While those stock analysts were hyping stocks on television, most often
their employers had an investment banking relationship with the company
the analyst was hyping.
Now it is well known now that these analysts were under intense pressure
to hype the stock, and almost never issued a "sell" rating on a stock
(Okay, a "hold" rating was a sell I suppose.) because these firms don't
make much money from analyzing stocks; They make their money from
investment banking services.
I believe only after a lot of ordinary investors got burned that these
financial news services started to disclose whether or not the firm the
analyst belongs to has investment banking relationship fearing possible
lawsuits by trial lawyers. (trial lawyers = hungry sharks)
If I bring the issue back to FPGAs, when you criticized me for being a
troll regarding QII 2.0's fast fit option, you didn't disclose that you
belong to Altera.
After I got the impression that you were an Altera employee that I
understood why you couldn't tolerate criticism of your company by me.
Well, your paycheck comes from there even though you deny that
it influences your opinions.
In theory, although I don't believe it matters considering that Altera
still has lots of design wins, if some people who saw my postings
decided to switch from Altera to Xilinx, your company will make less
money.
Technically, your employment might be threatened by that, although I
don't even believe that myself.
You also claim that you don't get paid to post here, and it is
not part of your job performance review, but I am sure if praise Xilinx
at this newsgroup while being an Altera employee, I am sure your boss or
employer won't be happy if they happened to see that. (It is very easy
to read past posting thanks to Google Groups. All you have to do is to
enter someone's name to retrieve past postings.)
> I am much more familiar with the Altera tools and devices that those from
> any other vendor. I won't even pretend to know half as much about Xilinx
> devices/tools or even FPGA design in general as some of the brighter posters
> in this group do. However, if someone has a problem that I think would be
> aided by some feature in an Altera device or tool, I'm probably going to
> post something. This is mostly because there doesn't seem to be an
> over-abundance of Altera product knowledge here (although lately there sure
> seem to be a lot of marketing-type cheerleading that I'd appologize for if I
> was somehow responsible).
>
I think you should, in general, disclose your affiliation if you
are going to recommend or hype products, although you are not the only
one who does that. (I saw a Quicklogic FAE 'shamelessly' hyping his
employer's anti-fuse FPGAs recently.)
No, I don't have anyway to force that, but people who are getting the
advise will rather know the poster's affiliation I think.
Although I do understand that some people won't want to use their work
E-mail to post here, and rather use a personal E-mail considering the
spam you will get by posting here.
> OK, that's enough here. If you want to take continue this, I would suggest
> that you send me an email. I would be happy to continue this discussion
> without adding any more useless postings to this otherwise generally
> informational newsgroup.
>
> -Pete-
I don't believe this discussion was totally useless.
I believe I should have the right to criticize any vendor if I feel like
there is a problem.
I should also have the right to make fun of vendors who hype small
additions to their software, and in this case, I believed Altera was
hyping QII 2.0's Fast Fit option even though similar option existed on
Xilinx tools for years.
I also believe it also raised questions of conflict of interest and
disclosure.
Should an employee who belongs to a PLD vendor recommend products,
especially if that person is recommending the employer's products,
without disclosing where the paycheck is coming from? (Or whether or not
that person own the company stock.)
Actually, I am fine with you hyping Altera's products if that is all you
know, and that's all you feel like, but at least, I think you should
disclose where you work at, so that people who read your postings see
why you are coming up with whatever answers you posted here.
Most Xilinx employees who post their postings here do that.
Kevin Brace (In general, don't respond to me directly, and respond
within the newsgroup.)
Article: 42007
Peter Ormsby wrote:
>
>
> Kevin,
>
> Here's one of the places where I found the definition of a usenet "Troll":
>
> http://www.dickalba.demon.co.uk/usenet/glossary.htm
>
I copied off the text from the URL you provided.
___________________________________________________________________
Troll:
Trolling is posting a message in a newsgroup with the deliberate
intent of starting heated discussion.
There are people who imagine that trolling is always a Bad Thing.
Bad trolling is definitely a bad thing but I have seen many intelligent
and entertaining trolls.
When it is done properly it can be compared to gently winding people up
or stirring things for fun, as you would find people doing every night
in your local bar.
Where trolling becomes bad is when it is done by a stranger to the group
who has no real interest in the group's topic and is there purely to
hurt or disrupt the normal flow of discussion.
A troll feeds on responses, taking any serious attempts at debate and
turning them round to feed the fire - this is one of the ways in which a
real troll can be identified.
When it becomes clear that one of these is at work, the correct response
is to post a short message exposing them as such and thereafter, ignore
the thread.
Of course, if the troll is entertaining and harmless, you can have some
fun by joining in.
___________________________________________________________________
> Most of the posts to this newsgroup are either people with questions or
> people with answers to those questions. Sometimes the questions are really
> specific to a design and sometimes they're more like "What do you think of
> this concept?". Responses usually raise more questions or provide
> (hopefully) helpful answers. In any case, posts here usually either
> solicit feedback or provide it. This is good.
>
I feel like you are limiting the scope of the newsgroup here.
Can't there be constructive criticism of a vendor if there is something
wrong?
I believe my posting was relevant to this newsgroup because I was
criticizing Altera's free tools, and you sound like you didn't
appreciate my criticism.
You don't have to agree with my postings, but as long as it is about
programmable devices or vendors, shouldn't I also be allowed to make fun
or criticize a vendor who hypes a fairly minor new feature that existed
on the rival vendor's software for years?
> The post which caused me to feel like you were behaving like a Troll was
> this:
>
> Kevin Brace <ihatespam99kevinbraceusenet@ihatespam99hotmail.com> wrote in
> message news:a63bum$p8s$1@newsreader.mailgate.org...
> > I have been using QII 2.0 Web Edition for a few days, and one of
> > the new features of QII 2.0 is fast fit option which reduces compile
> > (P&R) time.
> >
> >
> http://www.altera.com/corporate/news_room/releases/products/nr-stx_quartus.h
> tml
> >
> > Didn't kind of feature to reduce the P&R effort level already existed in
> > Xilinx tools for years?
> > In Xilinx tools (like ISE WebPACK 4.1 I primarily use), the user can
> > choose between five P&R effort levels with an optional Extra Effort
> > level available.
> > So, what is the big deal about it, Altera?
> > I guess I am now critical of Altera because of my bad experiences with
> > QII 2.0 WE + LeonardoSpectrum-Altera 2002 Level 1 NativeLink issue when
> > FLEX10KE or ACEX1K is the target device.
>
> This was not in response to any query about the Fast Fit option, nor is
> there any serious solicitation for feedback from the rest of the
> comp.arch.fpga community. It seemed to me that your post was submitted to
> "stir the pot" and see what sort of trouble you could stir up. In other
> words, it was a Troll post (unless I'm really missing the boat on the Troll
> definition).
The 'good Troll' definition allows posting of a nature that
'stir the pot'.
Since my posting was not off topic to this newsgroup, I don't see a
problem with my posting.
However, if you don't like it, that's too bad.
> Now, granted, I should probably have provided a pointer to one
> of the usenet glossary pages to be a bit more clear what I was talking
> about, but you have to admit that the Troll reference wasn't totally
> unjustified.
>
> -Pete-
Reading the URL you provided, the word 'Troll' doesn't always
have a negative meaning I think.
The definition of a bad Troll seems to be that if some idiot who posts a
totally off topic posting to this newsgroup, tries to start a discussion
here, and doesn't listen to people that it is off topic, that's a Troll.
I don't believe I am a stranger to this newsgroup, and neither do I
believe that my posting was off topic.
The purpose of my posting about QII's Fast Fit option was to make fun of
marketers who hype a new minor feature that existed on the competitor's
products for years.
I think both Xilinx and Altera's marketers equally deserves punishment
for their marketing hype of their products, but I guess I felt like
poking fun at Altera when I wrote it.
Since I do work on a IP core myself, I sure can criticize and make fun
of Xilinx's 'proprietary' Smart-IP Technology (TM) if I wanted to since
all they are talking here are segmented routing (all Xilinx FPGAs are
like that already.), manually floorplanned netlist (I can do that much
myself using Xilinx Floorplanner.), and the use of guided routing when
it is necessary. (For 66MHz PCI.)
Basically, all those features are available to regular users if they
wanted to use it, so things don't seem that 'proprietary' after all.
I see very clearly why you called me a Troll.
Even though you claim your employer doesn't force you to say certain
things, I am sure you won't speak against your company at this newsgroup
fearing job retaliation.
Plus, I will say it again, but doesn't getting your paycheck from Altera
influence your opinions?
Sure, you can deny that, but then why are politicians influenced by
large campaign donors?
Yes, when confronted about the money and politics, almost all
politicians deny that there is any link, but look at their voting
records and money trails.
Kevin Brace (In general, don't respond to me directly, and respond
within the newsgroup.)
Article: 42008Take a look at http://www.digilentinc.com/Products/products.html Anna Tom Loredo wrote: > Hi- > > I'm experienced with 8-bit microcontrollers, but a complete > newbie to FPGAs. I'm considering them for an upcoming > project, and a factor in my choice is availability of > an affordable evaluation/development board with a *serial* > interface. So far I've been looking at parts from Xilinx > and Atmel, but the eval boards I've come across all use > the parallel port on the PC. I only have a serial or USB > port, so these are not suitable. Any leads/suggesions > are appreciated. > > Thanks! > Tom Loredo -- ***************************** Anna M. Acevedo Xilinx University Program 2100 Logic Drive San Jose, CA 95124 PH: (408) 879-5338 FAX: (408) 879-4780 Email: anna.acevedo@xilinx.com http://www.xilinx.com/programs/univ.htm *****************************Article: 42009
Jason Zimmernann wrote:
>
> Just wanted to clarify a few things...
> I work for a university lab, and this is a research project, not a
> commercial product. Consequently, two main issues are driving my
> decision. First, I must use the hardware that is available to me.
> Which in this case contains a Xilinx part as the PCI interface.
Which Xilinx FPGA are you using?
> Other
> people are working on other aspects of the project (networking and
> security), and this is the platform we must all coexist on. Second, I
> must really justify the cost if I don't use something that is freely
> available. I am *hoping* that the opencores code can be used as
> somewhat of a "black box", but with the Wishbone stuff replaced with a
> different backend.
>
If everything fails, send me an E-mail.
I will see what I can do for you.
> Kevin, I appreciate the honesty, and also the fast reply. After our
> experience (admittedly a long time ago) with another Open core, I
> hesitate to use something off of that site. Getting the code to
> synthesize was hard enough being that it was "someone else's code",
> but on top of that we couldn't get it to work well enough for our
> purposes so we wrote our own. I do not like to generalize about a
> "movement", as it were, from one experience, and it really looks
> attractive to have the PCI master logic already done--but then again,
> once burned...
>
> j.
>
No, I won't say that the ideal of the Opencores.org is bad, but
the problem is, the people who work on projects seem to post their work
there without adequately testing it.
Perhaps for a small project (I will consider a PCI IP core a small
project.) they might want to have a policy not to allow code to be
available until all known bugs are fixed.
Also, since the design will be open source, the authors will have to
keep the design easy to understand if someone wants to modify or fix
bugs themselves, but the authors of Opencores.org PCI IP core didn't
seem to care about it.
> p.s.: fyi, we may be moving to a VirtexII-based board in the future,
> and i think i read somewhere that they want $15,000 for the newer PCI
> core...which is a lot compared against my stipend... :)
I heard somewhere that a LogiCORE PCI license for educational
institutions costs $500.
You might be talking about Xilinx's PCI-X IP core.
Kevin Brace (In general, don't respond to me directly, and respond
within the newsgroup.)
Article: 42010Hi- I'm experienced with 8-bit microcontrollers, but a complete newbie to FPGAs. I'm considering them for an upcoming project, and a factor in my choice is availability of an affordable evaluation/development board with a *serial* interface. So far I've been looking at parts from Xilinx and Atmel, but the eval boards I've come across all use the parallel port on the PC. I only have a serial or USB port, so these are not suitable. Any leads/suggesions are appreciated. Thanks! Tom LoredoArticle: 42011
But the card I mentioned doesn't need an external power suply. What I now plan to do, to circumvent the bus speed issue, is to give the FPGA a very large task. In the game of go, what is necessary to compute is a search tree of possible moves. When I split a board position up into its smallest units, I'll end up with around 10 grids of each max. 19 x 19. When I succeed in designing a hardware move generator, 'chain-safety recognizer' and 'chain-freedom counter', all bandwidt issues are gone, as I merely need to send a few hundred bytes per grid, and I get a boolean back! But it is of the utmost importance that the final design is a Virtex-E speed grade 8, for I intend to make a brute- force move generator with a much higher branching factor than that of chess. I need to have millions of positions examined per chain, as I can't include any 'artificial intelligence' that decides about skipping moves. For a newbie like me, designing the stuff I just talked about will prove to be a major nightmare anyway. I am now doing some preliminary study on how to do it, and whether it's feasible at all... I have no idea how many gates I'd need, for example. Might be very few, might be millions... Thanks for all the advice (I need it) Frank "Andreas Ehliar" <ehliar@lysator.liu.se> wrote in message news:a956cl$8ng$1@news.island.liu.se... > In article <a94m6t$j6$1@newsreader.mailgate.org>, Kevin Brace wrote: > > Is that what you really want? > > I heard that that PCI board can handle only 1MB/s to 2MB/s (Something > > close to an ISA bus card.) because supposedly it cannot handle burst > > transfers. > > I've read some of the documentation for this card and the PCI-bridge seems > to be designed with a small 8-bit CPU in mind. The interface to the bridge > is only one byte, so the card will silently ignore reads/writes to the > remaining 3 bytes. > > The datasheet for the PITA-2 bridge is available here: > http://www.infineon.com/cgi/ecrm.dll/ecrm/scripts/prod_ov.jsp?oid=16802 > > Anyway, the bridge is probably very interesting if it is used in > conjunction with a small microcontroller. Not so interesting for > most FPGA solutions. > > /AndreasArticle: 42012
Bob, The two things that control the speed of an ILA core most are the trigger width and match unit type. Small trigger widths are key to have speedy cores. In a very simple design, I'm able to get a core with an 8-bit wide trigger bus and extended matching to meet a 7ns period constraint (142 MHz) for Virtex-II. Use a -6 part and basic matching, and you can get it running at speeds in excess of 200 MHz. If you can't get a particular core to run at the speed you want, consider breaking up the core into two, each with smaller trigger widths. It's important to note that my design was not conjested at all in terms of routing or placement, and that can certainly have an effect. As Mr. Murray said, floorplanning and pipelining are always good practices when trying to meet a tough timing constraint. Hope this helps, Mike Bob Perlman <bobsrefusebin@hotmail.com> wrote in message news:<6i5abugbfjjtaevmq9eo93d48dpf6gdlk1@4ax.com>... > Hi - > > We're currently using ChipScope in the lab, to debug some Virtex II > parts. The functionality is impressive, but the speed is somewhat > lacking. When we try to use ChipScope logic in parts running at 125 > MHz, we can't meet timing. Simplifying the trigger conditions helps > somewhat, but not enough. > > Does anyone who's worked with ChipScope have some tips for speeding it > up? Other than not looking at the timing reports, that is... > > Thanks, > Bob PerlmanArticle: 42013
DDR does not have full page mode. On Fri, 12 Apr 2002 08:39:37 -0700, "name" <e@m.ail> wrote: >Set the memory to full page mode and abort the operation after one cycle. >Article: 42014
Hi Ahmad, I think you have the right idea. It is that the cores will run faster if their critical path delays are optimised by a designer and fixed. If you don't need the absolute maximum performance then try turning off RPM and see what that does for you space wise. I think there is a switch in the placement tool that lets you ignore RPM placements which would save you recreating the core. Can't say where it is as I am not at the machine right now. I don't know the performance hit you will take on speed, try it & see. I do know that it's very difficult to get the tool to use all the luts. -- dmacArticle: 42015
"Jim Raynor" <chris@ultrasonix.com> writes: > hi, > > Does anyone know where to get a complete price list for all the Xilinx's > FPGAs (Virtex 2, Virtex E, Spartan 2 E, etc)? The price list doesn't have > to be accurate 'cause I just want to get an idea which FPGAs I am going to > use in the new design in term of processing power and $$$. Try http://findchips.com/ This will search through several of the distributor sites for you. Petter -- ________________________________________________________________________ Petter Gustad 8'h2B | (~8'h2B) - Hamlet in Verilog http://gustad.comArticle: 42016
I tried it, and found it fast and intuitive, but unforyunately almost worthless since it does not cover the major distributors. Nice try, but no cigar. Peter Alfke, Xilinx Applications ========================== Petter Gustad wrote: > Try > > http://findchips.com/ > > This will search through several of the distributor sites for you. >Article: 42017
OK, call me brain damaged, but searching the Xilinx web site isn't
helping me yet.
I want to do some post placement, pre-routing manipulation of the
design (well, actually, build TOOLS to do...). Is there a way to
extract/manipulate the .ngd file, including placement information? Or
is the format published somewhere?
ngd2{edif,vhdl,vlg} seems to just produce a simulation netlist,
annotated with delays. I want something I can go back & forth with.
Thanks.
--
Nicholas C. Weaver nweaver@cs.berkeley.edu
Article: 42018Kevin, Cool. I'm glad that you took my calling you a Troll in the correct light. I responded here because it was never my intention to make you feel as if you were being "personally attacked" and I wanted to dispute your claim that there a lot of mean-spirited discussion going on here. My selection of that particular definition of Troll was specifically because it was not all negative. That being said, the original discussion of the "Fast Fit" feature apparently needs some closure. You must not assume that every marketing claim by Altera (or Xilinx, for that matter), is aimed at users of the competitors tools. Users of Quartus 2000.09 were probably pretty excited about the ability of Quartus II to accelerate the P&R process by compromising the ultimate speed of the results. In the same light, I don't begrudge Xilinx for their marketing of MicroBlaze (or even Block RAMS for that matter) just because these were feaures that were available in Altera tools/devices previously. Both Altera and Xilinx have taken ideas from each other and used them to make their own products better. This is good for all the engineers out there as they will have better devices today than they had five years ago - no matter which vendor's devices they decide to use. -Pete-Article: 42019
Xdl (Xilinx Design Language).. If you remember the tool I showed at FCCM
last year it was all based on xdl. Just type xdl at a command prompt. You
can do ncd2xdl and xdl2ncd When I parse it in I can get all the loads on a
signal lots of other information.
Steve
"Nicholas Weaver" <nweaver@CSUA.Berkeley.EDU> wrote in message
news:a97n03$11bv$1@agate.berkeley.edu...
> OK, call me brain damaged, but searching the Xilinx web site isn't
> helping me yet.
>
> I want to do some post placement, pre-routing manipulation of the
> design (well, actually, build TOOLS to do...). Is there a way to
> extract/manipulate the .ngd file, including placement information? Or
> is the format published somewhere?
>
> ngd2{edif,vhdl,vlg} seems to just produce a simulation netlist,
> annotated with delays. I want something I can go back & forth with.
>
> Thanks.
>
> --
> Nicholas C. Weaver nweaver@cs.berkeley.edu
Article: 42020"Frank de Groot" <franciad@online.no> wrote in message news:<gTGt8.4415$dm4.94093@news2.ulv.nextra.no>... > But the card I mentioned doesn't need an external power suply. > > What I now plan to do, to circumvent the bus speed issue, is to give the > FPGA a very large task. > In the game of go, what is necessary to compute is a search tree of possible > moves. > When I split a board position up into its smallest units, I'll end up with > around 10 grids of each max. 19 x 19. > > When I succeed in designing a hardware move generator, 'chain-safety > recognizer' and 'chain-freedom counter', > all bandwidt issues are gone, as I merely need to send a few hundred bytes > per grid, and I get a boolean back! > > But it is of the utmost importance that the final design is a Virtex-E speed > grade 8, for I intend to make a brute- > force move generator with a much higher branching factor than that of chess. > I need to have millions of positions examined > per chain, as I can't include any 'artificial intelligence' that decides > about skipping moves. > > For a newbie like me, designing the stuff I just talked about will prove to > be a major nightmare anyway. > I am now doing some preliminary study on how to do it, and whether it's > feasible at all... > I have no idea how many gates I'd need, for example. Might be very few, > might be millions... > > Thanks for all the advice (I need it) > > Frank > Interesting project. My advice would be to finish a lot of your design and synthesize it before you purchase a card. You can try to target different FPGAs and see what size that you'll need. I've heard of supposedly experienced hardware engineers fabbing PCBs before finishing their HDL coding, and then finding out that their boards were basically useless because they overestimated what they could fit in the FPGAs. Since you're a "newbie" then you should be particularly careful about this sort of thing. I would think that a Go move generator plus some evaluation would be fairly large, but it's just a guess. Marc Boulé designed a chess move generator much like that used in Belle with a few enchancements based on what Hsu added in Deep Blue and if I recall correctly it took him about half of an XCV800. You can read about it on his web page: <http://www.macs.ece.mcgill.ca/~mboul/> After he finishes his thesis then he will publish his source code - which will of course not be at all relevent to Go, but you might find it interesting regardless. Regards, KeithArticle: 42021
the AMBA bus in not external to any ARM chip. just an FYI. maybe you should look into the Excalibur along with the Altera internal logic analyzer. that might be an option, but you should definitely confirm availability, lead time, price, size, etc... also, it is a very new part, so you might want to look into errata. if you find it doesn't suit your needs, i would go with virtex-2. i have had a lot of success with that chip. the main thing is size, though. find out how many ASIC gates really map to whatever FPGA you buy. also, give yourself as much headroom as you can. chrisArticle: 42022
Oh yeah. Sorry. If you need a lot of multipliers, for FIRs or mixers or such, you might want to go to a VirtexII. Multipliers in a non-V2 are pretty large. "Ray Andraka" <ray@andraka.com> wrote in message news:3CB629D4.3F66D08C@andraka.com... > Nope, > > If you were working with a virtexII or virtexII-pro then you can instantiate > the mult18x18s. VirtexE does not have the dedicated multipliers. You need to > either roll your own or use the Xilinx coregen to create a multiplier macro > which you can then put in your design. The multipliers in virtexE are created > from the general purpose logic in the fabric, not from special multipliers. > > That said, there is an added AND gate in the carry logic that is useful for > reducing the logic required to make a 2xN partial product multiplier, which is > then used to create a larger multipler as shown on my website. > > Kevin Neilson wrote: > > > Instantiate MULT18X18S. Some synthesizers might be able to just infer them > > (with '*') but I've been instantiating them. > > > > Make sure you have the most current data sheet for multiplier timing. > > (They've been getting progressively slower.) > > > > "Max Edmand" <maxedman3503@yahoo.com> wrote in message > > news:3a30996f.0204101958.2df0945c@posting.google.com... > > > Could someone please give a hint how to instantiate built in > > > multipliers that Xilinx claims are available in Virtex 2000E? > > > > > > I need to exploit them in my VHDL design. should I use something > > > like primitives or components from Xilinx Library? but they seem > > > to be lower level functions like multiplexers, registers, > > > comparators,... > > > > > > Thanks, > > > Max Edmand > > -- > --Ray Andraka, P.E. > President, the Andraka Consulting Group, Inc. > 401/884-7930 Fax 401/884-7950 > email ray@andraka.com > http://www.andraka.com > > "They that give up essential liberty to obtain a little > temporary safety deserve neither liberty nor safety." > -Benjamin Franklin, 1759 > >Article: 42023
Xilinx's XAPP 502 points you to Xilinx's web site where you can download Verilog and C code for interfacing a MicroP to a CPLD to program an FPGA. The Verilog code is what is compiled into the CPLD. My question - has anyone ported the Verilog code to VHDL, and if so, where can I get a hold of it? Thanks! To reply by email, remove the period and everything after it up to the @ sign.Article: 42024
Not necessarily. Only full parallel multipliers are large. If you have
several clocks per sample to do the multiplication you can use a scaling
accumulator. FIR filters can be made considerably smaller by using
distributed arithmetic, and depending on the size of the filter and the clock
rate vs sample rate you could get fairly sizable filter into an FPGA. For
more info on multiplication see the multipliers page on my website. There is
also a tutorial page on distributed arithmetic. Finally, take a look at the
paper titled FPGAs make a radar on chip a reality for an example of some
pretty large filters implemented using DA. In that case there are a pair of
256 tap complex (complex input, complex coefficient) non-symmetric FIR filters
implemented in a V1000-4, and they run at a 5MHz sample rate.
Kevin Neilson wrote:
> Oh yeah. Sorry. If you need a lot of multipliers, for FIRs or mixers or
> such, you might want to go to a VirtexII. Multipliers in a non-V2 are
> pretty large.
>
--
--Ray Andraka, P.E.
President, the Andraka Consulting Group, Inc.
401/884-7930 Fax 401/884-7950
email ray@andraka.com
http://www.andraka.com
"They that give up essential liberty to obtain a little
temporary safety deserve neither liberty nor safety."
-Benjamin Franklin, 1759
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