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Jack Nimble wrote: > > I am currently looking at two solutions to a frequency generation > problem. > > Either I can use a PIC microprocessor or a CPLD (Xilinx XCR3256XL). If a uC can meet the targets, the it tends to self-select. Normally, a PLD is used either alone, or to Augment a uC, when the uC alone is not sufficent. Look also at a uC plus smaller PLD combination. > The PIC includes a crystal oscillator on chip. What I am wondering is, > can I use some gates from the CPLD to create an embedded crystal > oscillator rather than having to include an external design based > around a couple of inverters in a discrete logic chip. > > Has anyone done this already? Short answer: It is doable, but risky. There are two main Logic osc topologies, a) 2 teminal Parallel, ( as in PIC osc ) where the xtal sits across a single unbuffered inverter, which internally drives a schmitt. If a buffered inverter is used, it tends to be unstable. Hysteresis can also create another 'natural frequency' to watch out for. b) 4 terminal series, where two inverters are biased into nominal linear region, and a xtal in series completes the loop. This circuit will ALWAYS oscillate, the hope is that the xtal locks it. Common in old TTL designs. Smallest area solution is TinyLogic HCU04 gates, budget for more than one, as the finite slew of a Sine wave can cause problems in the fast CPLDs. -jg -- ======= 80x51 Tools & IP Specialists ========= = http://www.DesignTools.co.nzArticle: 41726
Sounds like it isn't the synthesizer but more an overzelious P&R tool trying to save setup time. I think that there is a global option under one of the menus thats tells it not to use the IOB flops. Regards "Don Teeter" <spam.not.allowed@intel.com> wrote in message news:<a8fc8i$iqb@news.or.intel.com>... > My VHDL design uses 'generate' to instantiate a bunch of FDPE primitives > (XC4000). These are flip-flops with preset. But one always gets > synthesized as an IDFX type, which is an input flip-flop without preset. > This changes the circuit function. Why does it do this? How can I prevent > it? > > Thanks,Article: 41727
I've built a small prototypeboard for experimenting with this Altera PLD. Basically, all pins are routed to some expansions connectors. But I really don't know what happened, because first I managed to download a simple design into the chip. It was just an input connected through a T-flipflop to an outout. Then I hooked up a led to the output (through a 1k resistor), and had a 1kHz clock connected to the input. Everything worked, wow I though. But then I touched the chip and noticed it was very hot. The led still toggled as it was supposed to, but the programmer got no contact. I've dubble-checked all connections and there are no shorts or missroutings. I've heard of the so called latch-up effect on the inputs when they're not connected but can that really have made the chip get hot and crack?Article: 41728
Will (wv9557@yahoo.com) wrote:
: Can someone explain the following OPS:
: din_zx
: din_zxp
: split
: split_y
: in the file "microcode.csv" on the Free6502 page
: Or better yet, if you know of a document that describes all the ops, please
: tell me.
: Thank you
: Will
This is freeware man, We don't need no stinkin documents.
The "ops" are all about creating the next address needed
by the instruction by routing the proper values to an
Adder that will create the next address.
for example:
(ADDR_OP_MC_DIN_ZX ):
begin
addr_add_1 = {8'b00000000 , data_in};
addr_add_2 = x_reg;
eight_bit_flag = 1'b1;
end
In this case a offset value is currently being read in on
the data_in buss. This value is added to the X index to form
the next address.
(ADDR_OP_MC_DIN_ZXP ):
begin
addr_add_1 = {8'b00000000 , data_in};
addr_add_2 = x_reg;
addr_add_cin = 1'b1;
eight_bit_flag = 1'b1;
end
Same thing as before buy add 1 to the result.
(ADDR_OP_MC_SPLIT ):
begin
addr_add_1 = {data_in , dint1};
end
In this case the instruction is reading a 16 bit address. The
low byte was read in the last cycle and is stored in dint1. The
hi byte is currently on the data_in buss.
(ADDR_OP_MC_SPLIT_Y ):
begin
addr_add_1 = {data_in , dint1};
addr_add_2 = y_reg;
end
Same as before but add the Y index to the result.
The free-ip design is a standard microcode design that is easy
to code and experiment with. If you really wanted to make it
a real product then you would probably replace the microcode rom
with dedicated logic.
John Eaton
Article: 41729
I don't mean to take business away from Quicklogic, but why not use a
CPLD to do what you are trying to do?
Most CPLDs are flash memory-based (EEPROM-based), which means you can
reprogram it as many times as you want (Typically, you can reprogram it
more than 100 times. Check various CPLD datasheets to see how many times
you can do that.).
All Quicklogic FPGAs are anti-fuse FPGAs, in which you can only program
the chip once.
That is an advantage for keeping the design secret after shipment, but
during prototyping, it can be costly.
I believe Quicklogic has a program called WebASIC where you can order up
to 10 samples per project already programmed for free.
However, once you solder in the chip onto the board and noticed
something going wrong, then you will have to remove the chip somehow, or
get another board, and solder in another part.
That can be costly and time consuming.
If you used a CPLD here, since most CPLDs support ISP (In-System
Programming), you can reprogram the CPLD by attaching a jumper cable
without having to pull out the chip.
There is another type of FPGA called an SRAM-based FPGA (as opposed to
an anti-fuse FPGA), but I won't get into that here.
If you are a beginner of designing digital circuit using
CPLD/FPGA, I recommending downloading free design tools from various
FPGA/CPLD vendors.
I believe Xilinx's free tool called ISE WebPACK is the best in the
industry considering that it is the only vendor that lets you use a
crippled version of ModelSim for free. (Other vendors charge at least
$1,000 for the full version from them that's not crippled.)
When I say crippled, it starts to run slowly if the design is larger
than certain size, but for your application, I am sure you will be able
to live with that.
Some people won't like it, but I will recommend that you learn an HDL
like Verilog or VHDL to do the design, rather than using schematics.
(Yes, some people will criticize me for saying that.)
I think Verilog in general is easier to learn than VHDL, so I will
recommending using Verilog.
VHDL seems to force you to type in more stuff to do the same thing
Verilog can do in few number of lines, but Verilog's type check is
weaker compared to VHDL.
Regarding the Verilog code the guy who is likely a Quicklogic FAE wrote,
that code can be synthesized by any synthesis tool that supports
Verilog, and most CPLDs should be able to fit that in.
Several vendors sell prototyping boards with CPLDs, and they typically
cost about $100.
Programming cables shouldn't cost any more than $100.
One more thing to note, when you see a poster who only seems to
promote one vendor's device, there is a pretty good chance that person's
paycheck comes from that vendor.
Although I recommended using Xilinx's devices/tools here, that is
because I have been using their free tools for about a year, and it
seems to be the most stable and generous among the choice I got.
I don't work for Xilinx or its distributors, and I don't have any
financial incentive promoting it.
I just think there stuff are the best at the moment.
Kevin Brace (In general, don't respond to me directly, and respond
within the newsgroup.)
Patrick Robin wrote:
>
> Hi,
>
> I am new to this field. I am a senior software engineer with some
> college experience in basic digital design from 12 years ago.
>
> I also have experience programming AVR Atmel uC.
>
> I am contemplating moving one of my uC design to part hardware, part
> software to increase speed. It consists in a frequency and pulse width
> adjustable square wave generator.
>
> I would apreciate your opinion on how difficult and costly ($) would it
> be for someone like me to design a hardware (chip) with:
>
> -a 32 bit accumulator
> -a 32 bit comparator
> -one 32 bit register (A) to store the number to be added by the
> accumulator
> -one 32 bit register (B) to store the number to compare against the
> accumulator sum (C)
> -one digtal output =1 if C>B 0 otherwise or vice versa
>
> The accumulator should run at least at 25MHZ, preferably 50MHZ
>
> I could probably do this with individual components but I want to
> minimize part count. Please let me know of the best way to approach
> this. I don't want to invest in costly ($1000) programmators if
> possible.
>
> Of course if you already know of such a chip I would like to know also
> :)
>
> Thanks for your time.
>
> Patrick
Article: 41730A few items need to be considered here. If you would attempt to implement this design in a CPLD even though they are flash based and offer the benefits of ISP they can be weak at implementing wide counters or accumulators due to product term limitations within the Macro Cells. Another issue is utilization, the design that you have described requires 97 DFF's. CPLD's tend to have trouble maintaining pin locking when a design becomes over 70 % utilized. What good is ISP if you can't maintain your pin out through design cycles? The design would require around a 200 MacroCell CPLD for a safe margin. Large CPLD's tend to get rather expensive > $20.00 . Antifuse devices can actually maintain 100% pin locking and 100% utilization due to an abundance of internal routing resources. The advantage of a OTP device with a design like this is that you have already proven the functionality in software so there is little risk that any changes will be required. It is easy to equip prototype boards with sockets while you are verifying the design if you encounter problems. With an SRAM based FPGA there is a need to provide a serial boot rom that initializes the FPGA at power up. This is an additional device that you will have to provide and maintain yourself and will require the purchase of a programmer to support it. Another issue is that in the event of a power glitch the SRAM based FPGA needs to go through an initialization sequence which could be detrimental to a critical application. Another disadvantage with an SRAM based device is that unlike antifuse devices, they tend to be rather power hungry. With a QuickLogic solution the device is alive at power up, and will consume a fraction of the power of an SRAM device. The production devices will also be provided to you pre-programmed. Think of it like a quick turn custom ASIC for around $10.00. As far as free tools go, beware, you get what you pay for. The free tools from Xilinx will not support Verilog or VHDL designs. "Kevin Brace" <ihatespam99kevinbraceusenet@ihatespam99hotmail.com> wrote in message news:a8lf3u$tft$1@newsreader.mailgate.org... > I don't mean to take business away from Quicklogic, but why not use a > CPLD to do what you are trying to do? > Most CPLDs are flash memory-based (EEPROM-based), which means you can > reprogram it as many times as you want (Typically, you can reprogram it > more than 100 times. Check various CPLD datasheets to see how many times > you can do that.). > All Quicklogic FPGAs are anti-fuse FPGAs, in which you can only program > the chip once. > That is an advantage for keeping the design secret after shipment, but > during prototyping, it can be costly. > I believe Quicklogic has a program called WebASIC where you can order up > to 10 samples per project already programmed for free. > However, once you solder in the chip onto the board and noticed > something going wrong, then you will have to remove the chip somehow, or > get another board, and solder in another part. > That can be costly and time consuming. > If you used a CPLD here, since most CPLDs support ISP (In-System > Programming), you can reprogram the CPLD by attaching a jumper cable > without having to pull out the chip. > There is another type of FPGA called an SRAM-based FPGA (as opposed to > an anti-fuse FPGA), but I won't get into that here. > If you are a beginner of designing digital circuit using > CPLD/FPGA, I recommending downloading free design tools from various > FPGA/CPLD vendors. > I believe Xilinx's free tool called ISE WebPACK is the best in the > industry considering that it is the only vendor that lets you use a > crippled version of ModelSim for free. (Other vendors charge at least > $1,000 for the full version from them that's not crippled.) > When I say crippled, it starts to run slowly if the design is larger > than certain size, but for your application, I am sure you will be able > to live with that. > Some people won't like it, but I will recommend that you learn an HDL > like Verilog or VHDL to do the design, rather than using schematics. > (Yes, some people will criticize me for saying that.) > I think Verilog in general is easier to learn than VHDL, so I will > recommending using Verilog. > VHDL seems to force you to type in more stuff to do the same thing > Verilog can do in few number of lines, but Verilog's type check is > weaker compared to VHDL. > Regarding the Verilog code the guy who is likely a Quicklogic FAE wrote, > that code can be synthesized by any synthesis tool that supports > Verilog, and most CPLDs should be able to fit that in. > Several vendors sell prototyping boards with CPLDs, and they typically > cost about $100. > Programming cables shouldn't cost any more than $100. > One more thing to note, when you see a poster who only seems to > promote one vendor's device, there is a pretty good chance that person's > paycheck comes from that vendor. > Although I recommended using Xilinx's devices/tools here, that is > because I have been using their free tools for about a year, and it > seems to be the most stable and generous among the choice I got. > I don't work for Xilinx or its distributors, and I don't have any > financial incentive promoting it. > I just think there stuff are the best at the moment. > > > > > Kevin Brace (In general, don't respond to me directly, and respond > within the newsgroup.) > > > > Patrick Robin wrote: > > > > Hi, > > > > I am new to this field. I am a senior software engineer with some > > college experience in basic digital design from 12 years ago. > > > > I also have experience programming AVR Atmel uC. > > > > I am contemplating moving one of my uC design to part hardware, part > > software to increase speed. It consists in a frequency and pulse width > > adjustable square wave generator. > > > > I would apreciate your opinion on how difficult and costly ($) would it > > be for someone like me to design a hardware (chip) with: > > > > -a 32 bit accumulator > > -a 32 bit comparator > > -one 32 bit register (A) to store the number to be added by the > > accumulator > > -one 32 bit register (B) to store the number to compare against the > > accumulator sum (C) > > -one digtal output =1 if C>B 0 otherwise or vice versa > > > > The accumulator should run at least at 25MHZ, preferably 50MHZ > > > > I could probably do this with individual components but I want to > > minimize part count. Please let me know of the best way to approach > > this. I don't want to invest in costly ($1000) programmators if > > possible. > > > > Of course if you already know of such a chip I would like to know also > > :) > > > > Thanks for your time. > > > > Patrick >Article: 41731
The easiest way to answer your questions would be for you to take a sample
design (doesn't have to be very big), let it go through the place and route,
then look at what it did in the floorplanner. It will probably be pretty
obvious that you could do at least as good a job, although it may take you
longer to do it. Many of my designs will not fit using the automatic
placement, but fit with room to spare after floorplanning.
Jimmy Zhang wrote:
> Well, I think I can say hand placement certainly make the design run faster,
> what about the resource utilization? If my dirty pair of hands scatter the
> blocks
> all over the real estate, does that mean I am wasting LUTs?
>
> --
> -----------------------------------------------------
> Click here for Free Video!!
> http://www.gohip.com/freevideo/
--
--Ray Andraka, P.E.
President, the Andraka Consulting Group, Inc.
401/884-7930 Fax 401/884-7950
email ray@andraka.com
http://www.andraka.com
"They that give up essential liberty to obtain a little
temporary safety deserve neither liberty nor safety."
-Benjamin Franklin, 1759
Article: 41732
I don't use synopsis, so I can't tell you what buttons to press. Generally speaking, you
compile it the same way you compile your code except you need to set the target library
name to be xilinxcorelib. Look in your user's manual for creating libraries.
Max Edmand wrote:
> Thanks a lot Ray,
>
> I am going to use Synopsys VHDL simulator,
> but not sure how to link xilinxcorelib
> library with synopsys. In other words how to
> "compile corelib library" ? does this compilation
> need to be done only once ??
>
> Ray Andraka <ray@andraka.com> wrote in message news:<3CAA5443.F119802C@andraka.com>...
> > Use any simulator you want. You just have to compile the
> > xilinxcorelib before you try using it. The corelib is VHDL
> > files, and can be found under the xilinx install directory.
> > Keep in mind the coregen simulation uses behavioral models,
> > not the primitives or even the synthesized code.
> > Nevertheless, as long as you compile the library, it doesn't
> > matter which sim you use.
> >
> > Max Edmand wrote:
> >
> > > Hi everybody,
> > >
> > > I'm wondering which simulation tool can be used
> > > to do behavioral simulation of a VHDL circuit which
> > > contains Cores from Xilinx Coregen. Porbably the first
> > > option is Xilinx ModelSim but we do not have the Unix
> > > version of it (if it exists at all !).
> > >
> > > So, could I use Synopsys Simulation tool? I think that's
> > > the most available tool for me right now. does any body
> > > have experience of linking Xilinx cores with Synopsys
> > > simulation tool on Unix platform? I would assume i need to
> > > add the xilinx core library path somewhere in synopsys...
> > >
> > > Any kinds of hint are highly appreciated,
> > >
> > > Thanks a lot,
> > > Max Edmand
> >
> > --
> > --Ray Andraka, P.E.
> > President, the Andraka Consulting Group, Inc.
> > 401/884-7930 Fax 401/884-7950
> > email ray@andraka.com
> > http://www.andraka.com
> >
> > "They that give up essential liberty to obtain a little
> > temporary safety deserve neither liberty nor safety."
> > -Benjamin Franklin,
> > 1759
>
> Max Edmand
--
--Ray Andraka, P.E.
President, the Andraka Consulting Group, Inc.
401/884-7930 Fax 401/884-7950
email ray@andraka.com
http://www.andraka.com
"They that give up essential liberty to obtain a little
temporary safety deserve neither liberty nor safety."
-Benjamin Franklin, 1759
Article: 41733
I'm still not following you here. If you do your design hierarchically and keep
in hierarchical in the edif netlist, what information is getting lost? You
still have the signal names with the bit numbering intact, you still have the
structure. Maybe I am missing your point.
Nicholas Weaver wrote:
> I>I don't buy this. The information is there in the form of the netlist. The
> >fact that we get the gains we do out of floorplanning indicates that the
> >synthesis is doing fine. Perhaps you mean the synthesis needs to infer
> >placement and add the placement info to the primitives?
>
> That there is convenient structure which the synthesis tool can easily
> exploit, as the high level information is there, while the P&R tool
> would have to infer and recover.
>
> It is much the same way where, yes, you can do all the compiler
> optimizations at the assembly level, but it is MUCH more
> straightforward to do alot of it earler in the process, in the
> intermediate form.
>
--
--Ray Andraka, P.E.
President, the Andraka Consulting Group, Inc.
401/884-7930 Fax 401/884-7950
email ray@andraka.com
http://www.andraka.com
"They that give up essential liberty to obtain a little
temporary safety deserve neither liberty nor safety."
-Benjamin Franklin, 1759
Article: 41734
OK, Uncle. I admit that I already do these things in my designs, so perhaps I am
not realizing the full benefit of Amplify. We do lots of gate level floorplanning
in the code, and use the appropriate attributes to make sure our planning is not
disrupted by the good intentions of the tools. Yes, we do a fair amount of
structural netlisting...anything that gets used in more than one design or that is
replicated in a design basically gets at least the registers structurally
instantiated and RLOC's in the code. This is done hierarchically, so it is not
nearly as onerous as it sounds...we get a lot of reuse out of some pretty basic
modules and the modules created from them. Before you jump to the conclusion that
my methodology is inefficient, I should mention that I do turn out somewhere
around 15-20M equivalent gates/year, last year that was 8 major designs (V1000 and
larger devices, all near top end of the clock rates for the device...several
needed heatsinks on the FPGAs) and several smaller ones.
I suppose it woud have been fairer for me to say I don't see the cost justified by
the added value _for_the_type_of_designs_I_do. In any event thanks for the
clarification on the capabilities of Amplify. I did look at it closely when it
came out, and found that I was already getting the gains it claimed and more with
my methodology. I think it likely is helpful for the average user who has only a
foggy inkling of the innards of the FPGA, and not much patience for physical
design.
Ken McElvain wrote:
> I think a more detailed description of what Amplify does is in order.
>
> The logical hierarchy of a design can be easily reorganized into
> a good physical hierarchy without touching the source code. This
> may not matter to some people who thought physically from the
> beginning of their design and have the experience to know up front
> what the organization should be. Part of this reorganization
> capability includes the ability to replicate chunks of RTL objects.
> You may find that replicating an FSM or counter into different parts
> of the chip yields large improvements.
>
> Because the floorplan definition in Amplify is at an RTL level and we
> worked very hard at making generated RTL object names repeatable even
> with design changes, the RTL floorplan can survive design changes.
> Gate level floorplans that don't stick to module boundaries often have
> to be redone for even trivial design changes. (If you are doing
> structural netlisting in your HDL and generating placements, then that
> would be an exception). Amplify will also perform boundary optimization
> on your floorplan which involve timing optimizations mixed with
> placing results back into the regions.
>
> The current version of Amplify (3.0) includes a full detail placer for
> regions that works in cooperation with timing optimization of the logic.
> This feature is currently only available for Virtex/VirtexE. Detail
> placement obviously gives Amplify much more accurate delay information.
>
> An experienced Amplify user can get substantial performance improvements
> in 3-5 iterations through P&R. The first iteration gets you calibrated
> and the following iterations are like a game of whack a mole where the
> mole doesn't come back up again.
>
> Amplify obviously works best when the critical paths in your design are
> through a chunks of RTL. If you are willing to do a structural design
> and hand place everything, then it won't be useful to you. Most designs
> aren't done that way.
>
> Ken McElvain CTO
> Synplicity, Inc.
>
> Ray Andraka wrote:
>
> > Frankly, I don't see the cost justified by the marginal added value with
> > amplify. You can do almost* everything it does with the area constraints in
> > the floorplanner, plus with the floorplanner you can lock down some and area
> > constrain other logic.
> >
> > *The one thing it does buy you is to take into consideration the layout
> > while doing the synthesis.
> >
> > Like you mention, there was a time when we did floorplanning with graph
> > paper. The GUI makes it easier, but I still use the graph paper method for
> > doing placement in the source.
> >
> >
> > Phil Hays wrote:
> >
> >
> >>Jimmy Zhang wrote:
> >>
> >>
> >>>Just keep hearing about this hand placement thing, don't know how it
> >>>is done in reality. Does someone actually use their hands to do the
> >>>placement as opposed to CAD based P&R. Any hints?
> >>>
> >>The first way I learned to do this was with a paper diagram of the
> >>target chip, writing the constraints with a text editor, and coloring on
> >>the paper to indicate what had been put where. I didn't do the best of
> >>jobs (had an register reversed, with the msb where the lsb should be),
> >>but it was still ~30% faster resulting clock speed than the automatic
> >>placement. Made place and route times drop nicely as well. It was even
> >>better than that once I got the twist removed. But this is as close to
> >>"by hand" as I can picture.
> >>
> >>The floorplanner that Xilinx provides is just a nicely automated way of
> >>doing the same sort of puzzle. Do the data path(s) first, fit things
> >>together in a "logical" fashion, and for the first one floor plan at
> >>least plan on spending some time fiddling. Some people seem to get this
> >>skill right away, and some take longer.
> >>
> >>A slightly "higher level" way of gaining much of the benefit from
> >>floorplanning with potentially rather less effort is to use a "physical
> >>design" tool. Synplicity had the first ("Amplify") aimed at FPGA design
> >>(and I'm not sure if Mentor, Synopsys or anyone else have anything in
> >>this space yet), however there were physical design tools for ASIC
> >>design long before Amplify. These work by putting large chunks of the
> >>design into subsections of the target chip.
> >>
> >>Synopsys's ASIC physical design tool set:
> >>
> >>http://www.synopsys.com/products/phy_syn/phy_syn.html
> >>
> >>Amplify is at:
> >>
> >>http://www.synplicity.com/products/amplify.html
> >>
> >>--
> >>Phil Hays
> >>
> >
> > --
> > --Ray Andraka, P.E.
> > President, the Andraka Consulting Group, Inc.
> > 401/884-7930 Fax 401/884-7950
> > email ray@andraka.com
> > http://www.andraka.com
> >
> > "They that give up essential liberty to obtain a little
> > temporary safety deserve neither liberty nor safety."
> > -Benjamin Franklin, 1759
> >
> >
> >
--
--Ray Andraka, P.E.
President, the Andraka Consulting Group, Inc.
401/884-7930 Fax 401/884-7950
email ray@andraka.com
http://www.andraka.com
"They that give up essential liberty to obtain a little
temporary safety deserve neither liberty nor safety."
-Benjamin Franklin, 1759
Article: 41735In article <3CAE6202.4DECF164@andraka.com>, Ray Andraka <ray@andraka.com> wrote: >I'm still not following you here. If you do your design hierarchically and keep >in hierarchical in the edif netlist, what information is getting lost? You >still have the signal names with the bit numbering intact, you still have the >structure. Maybe I am missing your point. Well, there have been a few academically developed but uncommercialized mapping techniques which work better if you don't have to reinfer structure from the netlist, but actively combine synthesis and placement: eg, gama-mapping and Koch's datapath placement, which are convenient to do in a higher level form, or at least in the academic world. -- Nicholas C. Weaver nweaver@cs.berkeley.eduArticle: 41736
Comments inserted in the QuickLogic Pitch... clevin1234 wrote: > > A few items need to be considered here. > If you would attempt to implement this design in a CPLD even though they are > flash based and offer the benefits of ISP they can be weak at implementing > wide counters or accumulators due to product term limitations within the > Macro Cells. Wide counters a no big problem. In any device, a 32 bit counter will need more than one layer of logic, and some tips can be taken from devices like 74HC161. > Another issue is utilization, the design that you have > described requires 97 DFF's. Not quite. 64 of those are latches. In devices like Atmels ATF150x family, you can overlay Registers and Combin Latches in the same macrocell. This is done in CUPL HDL, which allows the best HW access. On their web is a design that packs 4 x 8 bit PWMs into a 32 macrocell device, using this feature. We have also done 3 x Variable Freq PWMs in a 32 macrocell device. This uses a PwmFullScale register, to set variable timebase, and then 3 compare + comparitor channels. General PWM comments: The accumulator scheme is akin to DDS, and can have phase jitter effects. ( averages are good, but cycle-cycle jitter is clock related ) For PWM, I prefer a variable FullScale, plus the variable compare. This gives fine, jitter free frequency control, fine PWM control, and if your system tolerates a frequency band for PWM, very fine PWM control. You also can use fewer total registers : At 25MHz, 20 bits of counter will take you to a 20Hz PWM frequency, over 23 bits, and you are below 1Hz. What is the application target Freq Band ? All up, sounds to me like an application for a 128 Macrocell ATF1508. > CPLD's tend to have trouble maintaining pin > locking when a design becomes over 70 % utilized. What good is ISP if you > can't maintain your pin out through design cycles? The design would require > around a 200 MacroCell CPLD for a safe margin. 70% of what ? There are many resource measurements in a CPLD, for reference here are the FIT stats for the example quoted: Logic Array Block Logic Cells I/O Pins Foldbacks TotalPT FanIN Cascades A: LC1 - LC16 20/16(125%) 15/16(93%) 8/16(50%) 59/80(73%) (39) 0 B: LC17 - LC32 28/16(175%) 16/16(100%) 8/16(50%) 76/80(95%) (39) 0 Total dedicated input used: 4/4 (100%) Total I/O pins used 31/32 (96%) Total Logic cells used 48/32 (150%) Total Flip-Flop used 28/32 (87%) Total Foldback logic used 16/32 (50%) Total Nodes+FB/MCells 64/32 (200%) Total cascade used 0 Total input pins 15 Total output pins 20 Total Pts 135 > Large CPLD's tend to get rather expensive > $20.00 > Antifuse devices can actually maintain 100% pin > locking and 100% utilization due to an abundance of internal routing > resources. The advantage of a OTP device with a design like this is that > you have already proven the functionality in software so there is little > risk that any changes will be required. It is easy to equip prototype boards > with sockets while you are verifying the design if you encounter problems. > With an SRAM based FPGA there is a need to provide a serial boot rom that > initializes the FPGA at power up. This is an additional device that you will > have to provide and maintain yourself and will require the purchase of a > programmer to support it. Another issue is that in the event of a power > glitch the SRAM based FPGA needs to go through an initialization sequence > which could be detrimental to a critical application. Another disadvantage > with an SRAM based device is that unlike antifuse devices, they tend to be > rather power hungry. With a QuickLogic solution the device is alive at power > up, and will consume a fraction of the power of an SRAM device. The > production devices will also be provided to you pre-programmed. Think of it > like a quick turn custom ASIC for around $10.00. What Package / Logic / Volumes is this number for ? > As far as free tools go, > beware, you get what you pay for. The free tools from Xilinx will not > support Verilog or VHDL designs. <snip> > > Patrick Robin wrote: > > > > > > Hi, > > > > > > I am new to this field. I am a senior software engineer with some > > > college experience in basic digital design from 12 years ago. > > > > > > I also have experience programming AVR Atmel uC. > > > > > > I am contemplating moving one of my uC design to part hardware, part > > > software to increase speed. It consists in a frequency and pulse width > > > adjustable square wave generator. > > > > > > I would apreciate your opinion on how difficult and costly ($) would it > > > be for someone like me to design a hardware (chip) with: > > > > > > -a 32 bit accumulator > > > -a 32 bit comparator > > > -one 32 bit register (A) to store the number to be added by the > > > accumulator > > > -one 32 bit register (B) to store the number to compare against the > > > accumulator sum (C) > > > -one digtal output =1 if C>B 0 otherwise or vice versa > > > > > > The accumulator should run at least at 25MHZ, preferably 50MHZ > > > > > > I could probably do this with individual components but I want to > > > minimize part count. Please let me know of the best way to approach > > > this. I don't want to invest in costly ($1000) programmators if > > > possible. > > > > > > Of course if you already know of such a chip I would like to know also > > > :) > > > > > > Thanks for your time. > > > > > > Patrick > >Article: 41737
when i load a vcd file in Debussy?it says: testbench.d.hash_U1.inst.mem[786431:0]:bit size is out of range Exception found at line 850 ,fsdbRC is -15,skip that line and continue running. then it pop up a small windos.it says: Parsing vcd header by idcode scheme failed in fact,it gives up load the vcd file,so i cann't observer waveform.In my design,the memory generated by xilinx is 8K(Single_dual port ram 96*8192). how do i?Article: 41738
clevin1234 wrote:
>
> As far as free tools go,
> beware, you get what you pay for. The free tools from Xilinx will not
> support Verilog or VHDL designs.
>
That is not true at all.
You might be referring to Xilinx's WebFitter program, but I am talking
ISE WebPACK here.
I started using ISE WebPACK about a year ago, and it already came with a
free synthesis tool and a free (albeit somewhat crippled) version of
ModelSim.
For a circuit size of what you wrote (the Verilog code), even the
somewhat crippled version of ModelSim (ModelSim XE-Starter) should be
more than enough.
Does Quicklogic offer either one of those for free?
I checked out Quicklogic's website, but it looks like it doesn't even
come with a free synthesis tool. (Only a schematic tool.)
Kevin Brace (In general, don't respond to me directly, and respond
within the newsgroup.)
Article: 41739"Kelvin Hsu" <qijun@okigrp.com.sg> wrote in message news:<3ca1b8c3@news.starhub.net.sg>... > Hi, > > I am doing gate level simulation and I realized that it is so difficult to > probe internal signals since they are > all changed into a strange format and the format is also keeping changing > everytime I re-run the simulation. > > Is there any method so that I can have the internal signal names to be fixed > in the simulation( I mean the > registers)...I think in Synopsys I can see the format they write netlists. > But Xilinx is lot of messy. > > Thanks. > > > > module whatever( > ); > input clk_12m; > output buffer_full2; > input rxd; > output clk_out; > wire IO33_OBUF; > wire rxd_out_OBUF; > wire rxd_1_OBUF; > wire rst_n_IBUF; > wire \clockrecovery/beta_tmp_0 ; > wire \clockrecovery/x_0 ; > wire \clockrecovery/x_1 ; // This is the result my > definition of reg [7:0] x; > wire \clockrecovery/beta_tmp_1 ; > wire \clockrecovery/Mmult_beta_X_x_inst_lut2_20 ; > wire \clockrecovery/N1682 ; > wire \clockrecovery/Mmult_beta_X_x_inst_cy_88 ; > wire \clockrecovery/x_2 ; Try chipscope from xilinxArticle: 41740
"Alexander Miks" <monstrum@tiscali.se> schrieb im Newsbeitrag news:nDpr8.1110$m4.20430@news010.worldonline.se... > I've built a small prototypeboard for experimenting with this Altera PLD. > Basically, all pins are routed to some expansions connectors. But I really > don't know what happened, because first I managed to download a simple > design into the chip. It was just an input connected through a T-flipflop to > an outout. Then I hooked up a led to the output (through a 1k resistor), and > had a 1kHz clock connected to the input. Everything worked, wow I though. > But then I touched the chip and noticed it was very hot. The led still > toggled as it was supposed to, but the programmer got no contact. I've > dubble-checked all connections and there are no shorts or missroutings. I've > heard of the so called latch-up effect on the inputs when they're not > connected but can that really have made the chip get hot and crack? Hmm, probably, probably not. The are some things to consider. First, the chip is a CPLD right? The classic CPLDs consume a lot of stand-by current, so even if there is nothing going on inside, the get reasonable hot. Second, the Altera design enviroment drives all unused outputs to LOW, not TRISTATE. This is at least true for the Flex10K series, I dont know about the CPLDs. So when you have some other logic outputs conneted to your CPLD and the are driving a HIGH, you have a nice short ciruit -> HOT. -- MfG FalkArticle: 41741
Hi, I had a need for lots of 16-word ram blocks in an acex 1k30 device. From what i can see in the data sheet, you can only use parts of EAB ram blocks to do that. For a spartan xc2s30, it says the CLB function generators can be used as distributed ram blocks. Is it right that acex devices can't do that? Can the spartan CLB ram blocks be used as 16-word 'pipes' for delaying signals? I have 7 identical functions, each of which use a 16-word ram block used from EABs. With 6 functions, everything fits ok in quartus2. With 7 functions, quartus2 says an error of 7 EABs needed (acex 1k30 only has 6 EABs). Is there a way of using a single EAB as multiple small ram blocks? I'll eventually need 42 16-word ram blocks as delay pipes. Can i do that in a xc2s30? Acex 1k30?Article: 41743
Hi,
I`m new using Modelsim. I have several questions about simulating
with Modelsim:
1.When I simulate a structural VHDL design including
instantiations of components, should I be careful with anything in its
testbench? Modelsim always gives me errors like: "U|Z|... The
aritmethic operation response will be X"; If I simulate the components
alone, and the design without the components, the errors donīt appear
and everything goes well. So I suppose it could something I donīt take
care of in testbenches of structutal VHDL designs (Some initial
values...).
2.Modelsim simulates VHDL, Verilog, and Mixed HDL, doesnīt it? It
doesnīt simulate schematic desings, does it? So if I would like to
simulate a schematic, a solution could be writing the equivalent
structural VHDL desing.Is it true? What other solutions do exist?
Thanks a lot,
Itsaso
Article: 41744"Russell Shaw" <rjshaw@iprimus.com.au> schrieb im Newsbeitrag news:3CAEF0B9.2604727E@iprimus.com.au... > Hi, > > I had a need for lots of 16-word ram blocks in an acex 1k30 > device. From what i can see in the data sheet, you can only > use parts of EAB ram blocks to do that. For a spartan xc2s30, > it says the CLB function generators can be used as distributed > ram blocks. Is it right that acex devices can't do that? ;-) Iam waiting for the comment of the Xilinx guys. I can see their big smiles ahead, when they read this. > Can the spartan CLB ram blocks be used as 16-word 'pipes' > for delaying signals? It can, either a 16x1 bit Single Port RAM, Dual Port RAM (using 2 LUTs) or shift register (SRL16). Altera cant offer RAM made of LUTs, since Xilinx owns the patent. > I have 7 identical functions, each of which use a 16-word > ram block used from EABs. With 6 functions, everything fits > ok in quartus2. With 7 functions, quartus2 says an error of > 7 EABs needed (acex 1k30 only has 6 EABs). Is there a way > of using a single EAB as multiple small ram blocks? AFAIK not in parallel, you have to do some kind of muxing. > I'll eventually need 42 16-word ram blocks as delay pipes. > Can i do that in a xc2s30? Acex 1k30? In a Spartan-II easy, in ACEX it will be troublesome. -- MfG FalkArticle: 41745
"Itsaso Zuazua" <izuazua@ikerlan.es> schrieb im Newsbeitrag news:709383e9.0204060515.3ec4c24f@posting.google.com... > Hi, > I`m new using Modelsim. I have several questions about simulating > with Modelsim: > > 1.When I simulate a structural VHDL design including > instantiations of components, should I be careful with anything in its > testbench? Modelsim always gives me errors like: "U|Z|... The > aritmethic operation response will be X"; If I simulate the components > alone, and the design without the components, the errors donīt appear > and everything goes well. So I suppose it could something I donīt take > care of in testbenches of structutal VHDL designs (Some initial > values...). Right. Especially all internal signals need to be initialized by the user at the beginning, otherwise a operation using an undefined input will result in an undefined output. Use a *.do file to do this. Simply mark your signals in the SIGNALS window (hold SHIFT to mark multiple signals), Choose FORCE from the menu, initialize your signals. Use DEPOSIT, not FREEZE or FORCE as a drive option. After you did this, use SAVE TRANSCRIPT in the FILE menu to create your scrip (*.do) file for later use. -- MfG FalkArticle: 41746
Make sure EVERYTHING is set/reset by either using a reset signal from the test bench and into the device, something like Xilinx's ROC component inside the chip itself. This should make sure all signals are as they should be. Any errors before/during the reset need to be understood. Depositing values is one way round this, but is not like a real chip. Niv. Itsaso Zuazua <izuazua@ikerlan.es> wrote in message news:709383e9.0204060515.3ec4c24f@posting.google.com... > Hi, > I`m new using Modelsim. I have several questions about simulating > with Modelsim: > > 1.When I simulate a structural VHDL design including > instantiations of components, should I be careful with anything in its > testbench? Modelsim always gives me errors like: "U|Z|... The > aritmethic operation response will be X"; If I simulate the components > alone, and the design without the components, the errors donīt appear > and everything goes well. So I suppose it could something I donīt take > care of in testbenches of structutal VHDL designs (Some initial > values...). > > 2.Modelsim simulates VHDL, Verilog, and Mixed HDL, doesnīt it? It > doesnīt simulate schematic desings, does it? So if I would like to > simulate a schematic, a solution could be writing the equivalent > structural VHDL desing.Is it true? What other solutions do exist? > > Thanks a lot, > > ItsasoArticle: 41747
Russell, you are describing an application where Xilinx devices are undisputedly superior. You can use any LUT as a 16-bit synchronous-write RAM ( and you have hundreds or thousands of them.) Better yet, in all Virtex-family and in Spartan-II devices, you can use any LUT as a shift register of length n, where you define n by the four LUT inputs. This is called SRL16. For a nice desciption, click on http://www.xilinx.com/support/techxclusives/SRL16-techxclusive2.htm Peter Alfke, Xilinx Applications =================================== Russell Shaw wrote: > Hi, > > I had a need for lots of 16-word ram blocks in an acex 1k30 > device. From what i can see in the data sheet, you can only > use parts of EAB ram blocks to do that. For a spartan xc2s30, > it says the CLB function generators can be used as distributed > ram blocks. Is it right that acex devices can't do that? > > Can the spartan CLB ram blocks be used as 16-word 'pipes' > for delaying signals? > > I have 7 identical functions, each of which use a 16-word > ram block used from EABs. With 6 functions, everything fits > ok in quartus2. With 7 functions, quartus2 says an error of > 7 EABs needed (acex 1k30 only has 6 EABs). Is there a way > of using a single EAB as multiple small ram blocks? > > I'll eventually need 42 16-word ram blocks as delay pipes. > Can i do that in a xc2s30? Acex 1k30?Article: 41748
I hear the newest Altera FPGA product line (Stratix?) has ram blocks in 3 levels of granularity, from little chuncks on up to big 'uns. You don't have to give up any of your logic resources to use them either. Russell Shaw <rjshaw@iprimus.com.au> wrote in message news:<3CAEE835.362054C7@iprimus.com.au>... > Hi, > > I had a need for lots of 16-word ram blocks in an acex 1k30 > device. From what i can see in the data sheet, you can only > use parts of EAB ram blocks to do that. For a spartan xc2s30, > it says the CLB function generators can be used as distributed > ram blocks. Is it right that acex devices can't do that? > > Can the spartan CLB ram blocks be used as 16-word 'pipes' > for delaying signals?Article: 41749
Chipscope, as awesome as it is, is only useful after its been loaded into an actual FPGA. I think the question was regarding simulation of a gate level netlist. One messy way to do it is to bring the signal in question up to primary I/O. The other way is dependant on the sythesizer you are using but usually the is a way to force the syhtesizer to mainatin register/port names/meaning. In Synplicity for example, you apply the "syn_hier hard" attribute to the module you want to look at at gate. Regards pmanakkil@iprimus.com.au (Thomas) wrote in message news:<d72b1b1c.0204060151.6e54c2e@posting.google.com>... > "Kelvin Hsu" <qijun@okigrp.com.sg> wrote in message news:<3ca1b8c3@news.starhub.net.sg>... > > Hi, > > > > I am doing gate level simulation and I realized that it is so difficult to > > probe internal signals since they are > > all changed into a strange format and the format is also keeping changing > > everytime I re-run the simulation. > > > > Is there any method so that I can have the internal signal names to be fixed > > in the simulation( I mean the > > registers)...I think in Synopsys I can see the format they write netlists. > > But Xilinx is lot of messy. > > > > Thanks. > > > > > > > > module whatever( > > ); > > input clk_12m; > > output buffer_full2; > > input rxd; > > output clk_out; > > wire IO33_OBUF; > > wire rxd_out_OBUF; > > wire rxd_1_OBUF; > > wire rst_n_IBUF; > > wire \clockrecovery/beta_tmp_0 ; > > wire \clockrecovery/x_0 ; > > wire \clockrecovery/x_1 ; // This is the result my > > definition of reg [7:0] x; > > wire \clockrecovery/beta_tmp_1 ; > > wire \clockrecovery/Mmult_beta_X_x_inst_lut2_20 ; > > wire \clockrecovery/N1682 ; > > wire \clockrecovery/Mmult_beta_X_x_inst_cy_88 ; > > wire \clockrecovery/x_2 ; > > > Try chipscope from xilinx
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