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I don't work with a design nowhere near your size (Mine only takes 50% of Spartan-II XC2S150.), but it might be a good idea to do a Post P&R simulation before firing up your design. About 8 months ago, I was having problems with my design which worked fine during an RTL simulation. After wasting two weeks trying to figure out the problem (Not having an oscilloscope or a logic analyzer didn't help at all.), I did a Post P&R simulation, and yes, some output signals where going undefined. After turning off bunch of synthesis options, the design simulated correctly during a Post P&R simulation, and in worked fine when I fired up the board. So, ever since that bad experience, I always do a Post P&R simulation before burning a Configuration PROM. If doing a Post P&R simulation is too time consuming (I am sure it is.), you may want to try a Post synthesis simulation (gate level simulation), where you should be able to catch problems related to the synthesis tool not synthesizing the design correctly. Kevin Brace (In general, don't respond to me directly, and respond within the newsgroup.) al wrote: > > We were using 3.1i and works fairly stable with no major problems. Last > week, we loaded up the 4.1i and decided to give it a try. We used the same > set of VHDL design files, UCF constraint and batch file. At first, tool > seems working fine -- we are able to save compile time by about 40% and all > timing constraints are meet. Well, not so happy yet -- the output binary > doesn't not work in our hardware, seems like there is some sort of timing > problem somewhere. We called up xilix hotline, this support guy by the name > of Justin have no idea of what he is talking about -- keep telling me to do > a post route timing simulation on my 1.6 million gate design. Anyway, bad > tool + bad support = unhappy customer.Article: 41826
Same VHDL design files... What about edif? Are you using the XST synthesis? I've found signals that synthesize once with an FD or FDR can end up in a different run with an FDS primitive resulting in a different power-up state when I'm relying on the power-up states rather than a superfluous (from a system perspective) reset signal. If the edif files are the same or if your use of the reset is pervasive, my thought on what might be different doesn't work. al wrote: > We were using 3.1i and works fairly stable with no major problems. Last > week, we loaded up the 4.1i and decided to give it a try. We used the same > set of VHDL design files, UCF constraint and batch file. At first, tool > seems working fine -- we are able to save compile time by about 40% and all > timing constraints are meet. Well, not so happy yet -- the output binary > doesn't not work in our hardware, seems like there is some sort of timing > problem somewhere. We called up xilix hotline, this support guy by the name > of Justin have no idea of what he is talking about -- keep telling me to do > a post route timing simulation on my 1.6 million gate design. Anyway, bad > tool + bad support = unhappy customer.Article: 41827
I don't know much about image processing, but if you are going with a
PCI card route (Rather than using a dedicated card.), Nallatech
(http://www.nallatech.com) has several Xilinx FPGA-based PCI cards with
a DIME slot.
I believe they have some DIME modules with a DSP on them, but I am not
sure if they will fit within your budget.
I don't know how much their PCI cards cost (One with Virtex XCV300-6
that supports 64-bit PCI and another one with two Spartan-II XC2S150.)
because they don't list the price on their website. (I didn't feel like
asking them.)
An alternative will be an Insight Electronics Spartan-II PCI 200 board
recently released that has a P160 expansion connector.
The PCI card itself is cheap ($225), but that's without a one project
license for LogiCORE PCI which costs about $2,000. (Educational
institutions can get it for $500 I heard.)
You can try out a free Opencores.org PCI IP core if you cannot afford
Xilinx's one, or try doing your own if neither one of them work. (I have
done my own PCI IP core for Spartan-II, so it is possible, but it takes
a lot of time . . . )
As long as you use Spartan-II, you can use the free ISE WebPACK, so at
least you won't have to pay for tools.
Insight Electronics used to have a Spartan-II PCI card with a DIME slot
on it ($145. That's the one I have.), but somehow they replaced with
their own P160 expansion slot.
I have never used DIME, but I still feel like they should have kept the
DIME slot.
As a matter of disclosure, I don't work for any of the companies
I described here, and neither do I own their stocks.
I don't get paid to promote the boards I just mentioned, but I have used
ISE WebPACK and the older Insight Electronics Spartan-II PCI card
myself, and I am happy with them.
Kevin Brace (In general, don't respond to me directly, and respond
within the newsgroup.)
Frank de Groot wrote:
>
> Hi guru's,
>
> I need an off-the-shelf PCI PC addin card that I can use to do some
> specialized coprocessing.
> BUT that board should not be move expensive than 500$.
> Am I unrealistic? If not, could you give me a link, a brand name, a type
> number?
> Just the simplest FPGA and a processor, like a transputer or an ARM will do,
> better would be an 80x86 processor.
>
> Any other solutions? I need to do pattern matching and quite complex pattern
> generation.
> I might be able to do that without a CPU on the FPGA board maybe?
> Is there another solution (like SPLD, CPLD, CSOS, TTL array) that may be
> sufficient and would be cheaper? Should I opt for a CPU-only board instead?
> Any websites that have specs & prices of coprocessor boards, FPGA boards?
>
> Thanks very much for your help.
>
> Frank de Groot
> Oslo, Norway
Article: 41828Hi Kevin, Thanks for your elaborate reply. I will order the Spartan II from Insight Electronics. Does the "no one project license for LogiCORE PCI" mean that I am not legally allowed to develop on the kit? Does it mean that I get the hardware, but no means to actually use the kit due to the fact that I have no access to it via PCI? You have to excuse me, I am a newbie. I am an electronic engineer by education, but a programmer by profession. I need a fast coprocessor for a certain 'killer app', but I don't know much about these kits. I am almost sure a FPGA is the best solution, but I would like to know why there is such a think as 'development kits'. Is there also a 'final deploy' solution that is faster or cheaper? Or is the development kit also the card that is going to be sold to my customers, finally? And I noticed that this kit has an external power supply. Are there even cheaper boards that have about 50,000 usable gates that have no frills like RS232, LEDS etc and do not need an external power supply? I hope to sell thousands of those boards. Do you remember the ChessMachine, a popular PC addin card based on an ARM processor, around 1992? My project is something similar, but not for chess... Thanks for your help, I was searching the web for hours. I just asked Insight Electronics some questions about the PCI licensing too, so if you are busy please then just answer the question about 'final deploy' vs. 'development kit', I am a newbie and at a loss... Frank "Kevin Brace" <ihatespam99kevinbraceusenet@ihatespam99hotmail.com> wrote in message news:a8t9aq$1ko$1@newsreader.mailgate.org... > An alternative will be an Insight Electronics Spartan-II PCI 200 board > recently released that has a P160 expansion connector. > The PCI card itself is cheap ($225), but that's without a one project > license for LogiCORE PCI which costs about $2,000. (Educational > institutions can get it for $500 I heard.)Article: 41829
Kevin Brace wrote: > I don't work with a design nowhere near your size (Mine only takes 50% > of Spartan-II XC2S150.), but it might be a good idea to do a Post P&R > simulation before firing up your design. I agree whole heartedly. I would never count on a design until I had done a Post P&R simulation. On the otherhand, I would never waste time with a post P&R simulation until I had the other levels of simulation working correctly. BTW, Al, the quality of support does vary, but generally, the support is fairly good if you push the support person hard enough. For me, the major frustration is that the support is required in the first place for problems like these. It embarasses me to have to tell my boss that the "new" software is stopping my progress. I feel like I am a Beta tester for the software people. It seems like about half the time I call, the problem turns out to be an unreported bug in the software. Am I really pushing the envelope that hard? The other frustration factor is just getting through to a support person. (Hold times on the phone are longer than appropriate.) On the other hand, eventually, usually, they will figure out a workaround for the bug. Thanks, Theron > > About 8 months ago, I was having problems with my design which worked > fine during an RTL simulation. > After wasting two weeks trying to figure out the problem (Not having an > oscilloscope or a logic analyzer didn't help at all.), I did a Post P&R > simulation, and yes, some output signals where going undefined. > After turning off bunch of synthesis options, the design simulated > correctly during a Post P&R simulation, and in worked fine when I fired > up the board. > So, ever since that bad experience, I always do a Post P&R simulation > before burning a Configuration PROM. > If doing a Post P&R simulation is too time consuming (I am sure it is.), > you may want to try a Post synthesis simulation (gate level simulation), > where you should be able to catch problems related to the synthesis tool > not synthesizing the design correctly. > > Kevin Brace (In general, don't respond to me directly, and respond > within the newsgroup.) > > al wrote: > > > > We were using 3.1i and works fairly stable with no major problems. Last > > week, we loaded up the 4.1i and decided to give it a try. We used the same > > set of VHDL design files, UCF constraint and batch file. At first, tool > > seems working fine -- we are able to save compile time by about 40% and all > > timing constraints are meet. Well, not so happy yet -- the output binary > > doesn't not work in our hardware, seems like there is some sort of timing > > problem somewhere. We called up xilix hotline, this support guy by the name > > of Justin have no idea of what he is talking about -- keep telling me to do > > a post route timing simulation on my 1.6 million gate design. Anyway, bad > > tool + bad support = unhappy customer.Article: 41830
I am looking for feedback on people's expriences using either Xilinx or third-party FPGA evaluation/test platforms as part of or in conjunction with their development processes. For example, did the use of the platform save development time/money over not using them? What are people's thoughts & experiences of using such platforms - do they have significant advantages over just simulating the design? I'd appreciate any and all responses. Thanks in advance!Article: 41831
Yes, but do vhdl simulators have a library of noise generators? (with user-definable spectrum) I have all kinds of analog things going on that are unsuitable for simulation due to complexity. Its easier and faster to test with a cro than to attempt a simulation of the whole thing. Steve Casselman wrote: > > haha can't resist.. oscilloscopes are for weenies I just never make a > mistake. > Really tools like simulation are there because they are useful during > development. You need the right tool for the right job some times its a > scope and sometimes it a simulator. > > Steve > > > I use an oscilloscope. Simulation? That's for weenies;)Article: 41832
al wrote: > > We were using 3.1i and works fairly stable with no major problems. Last > week, we loaded up the 4.1i and decided to give it a try. We used the same > set of VHDL design files, UCF constraint and batch file. At first, tool > seems working fine -- we are able to save compile time by about 40% and all > timing constraints are meet. Well, not so happy yet -- the output binary > doesn't not work in our hardware, seems like there is some sort of timing > problem somewhere. We called up xilix hotline, this support guy by the name > of Justin have no idea of what he is talking about -- keep telling me to do > a post route timing simulation on my 1.6 million gate design. Anyway, bad > tool + bad support = unhappy customer. Well, the easiest way is to comment out all the code except a small piece that flashes a LED. Now keep adding in chunks of code and see what happens...Article: 41833
Are you talking about evaluation (prototype) boards? Kevin Brace (In general, don't respond to me directly, and respond within the newsgroup.) RAcoops wrote: > > I am looking for feedback on people's expriences using either Xilinx or > third-party FPGA evaluation/test platforms as part of or in conjunction with > their development processes. For example, did the use of the platform save > development time/money over not using them? What are people's thoughts & > experiences of using such platforms - do they have significant advantages over > just simulating the design? I'd appreciate any and all responses. Thanks in > advance!Article: 41834
Patrick Robin wrote: > Thanks for your ideas. > > I really don't need 32 bits for the accumulator to get the frequency resolution I need, Last > time I did the calculation I think I needed 27-28 bits for a 50MHZ accumulator. But I have > been mentioning 32 bits since it is a multiple of 8 and most discreet ships are 4 or 8. But I > guess with a PLD it is fully configurable. > > Patrick > Here is my suggestion: If you want to specify the frequency as a binary multiple of 0.5 Hz, build a 27-bit accumulator and bring in the 21 LSBs from the outside. They define the frequency in multiples of 0.5 Hz. The remaining 6 MSBs have zero as the adder input. Clock this accumulator with a frequency of 2exp26 Hz, i.e 67.108864 MHz, or thereabouts if you are not so concerned about the exact frequency and its binary representation in integer Hz.. The MSB ( single bit) output of the accumulator is your output frequency. You can decode either the 4, 5, or 6 MSBs to create the duty cycle with an accuracy of 6, or 3, or 1.5%. This ia a trivial decoding job. The chip has 21 inputs to define the frequency, 4 to 6 inputs to define the duty cycle, and one output. This circuit fits easily into the smallest CoolRunner CPLD. I like CoolRunner because it has the lowest power consumption in the industry, and because I happen to work at Xilinx. But any other CPLD would also do the trick. If you are concerned about the accumulator speed, you can pipeline the carry to your heart's content, as often as you want. It does not affect the Direct Digital Synthesis output. Fun project... Peter AlfkeArticle: 41835
I don't necessarily consider this bad support. For the Xilinx guy to help you, you have to tell him what is wrong, and you are just telling him "it doesn't work". To tell him specifically what is wrong, you have to run a postroute simulation. Actually, if you did that, you might not have to call him at all. Maybe the design is underconstrained and the 3.1 placment had enough margin to allow it to work, while the 4.1 placement, while meeting the imposed constraints, doesn't meet the real-world constraints. You won't know until you simulate. "al" <a-ng7@ti.com> wrote in message news:a8t1b8$9m9$1@tilde.csc.ti.com... > We were using 3.1i and works fairly stable with no major problems. Last > week, we loaded up the 4.1i and decided to give it a try. We used the same > set of VHDL design files, UCF constraint and batch file. At first, tool > seems working fine -- we are able to save compile time by about 40% and all > timing constraints are meet. Well, not so happy yet -- the output binary > doesn't not work in our hardware, seems like there is some sort of timing > problem somewhere. We called up xilix hotline, this support guy by the name > of Justin have no idea of what he is talking about -- keep telling me to do > a post route timing simulation on my 1.6 million gate design. Anyway, bad > tool + bad support = unhappy customer. > >Article: 41836
I am talking about evaluation/prototype boards that Xilinx adverstises on their website (<$1000 in most cases) + third party tools (www.xilinx.com -> buy online). I am trying to find out how people have used these boards in industry and whether they proved cost-effective (speaking more to the prototyping aspect).Article: 41837
Hi,all I'm using xilinx foundation 3.1i.It has been working very well till recent days.My design is implementated in xcv100e.The result of simulation and verification is different though the timing constraint is met. The FAE here adviced me to use service pack 7 because i've ever spent 2 days trying to install service pack 8 in my pc and then gave up.But I can't find service pack 7 at xilinx's website.Can anyone tell me where to get service pack 7?I'm in great hurry!Great thx in advance. mmArticle: 41838
Although I don't belong to the industry you are talking about, I have been using Insight Electronics Spartan-II PCI Development Kit ($145. Hardware only, no LogiCORE PCI license.) for my PCI IP core development. In my case, I don't have the money or knowledge to do my own PCB, so buying a prototype card was the only way to see if my design will indeed work in a real computer. It worked okay in two computers when I tested it just like the way it worked on a simulator. (RTL and Post P&R simulation) Whether or not it is cost effective for prototyping, I think so compared to doing my own. Kevin Brace (In general, don't respond to me directly, and respond within the newsgroup.) RAcoops wrote: > > I am talking about evaluation/prototype boards that Xilinx adverstises on their > website (<$1000 in most cases) + third party tools (www.xilinx.com -> buy > online). I am trying to find out how people have used these boards in industry > and whether they proved cost-effective (speaking more to the prototyping > aspect).Article: 41839
has anyone ever used an equivalence checker to check a synthesized netlist with the RTL code? i am thinking i can save a lot of time if i follow this approach instead of doing exhaustive gate level sims. if anyone has done this kind of thing, do the tools accept EDIF format (Verplex, Formality)?Article: 41840
is there any way to uniquify a synplicity netlist? i am trying to do a bottom-up compile where i compile modules individually and tie them together at the top level. i am running into problems in simulation because there are multiple instantiations of the same type of LUT. is there a way to avoid this?Article: 41841
Frank de Groot wrote:
>
> Hi Kevin,
>
> Thanks for your elaborate reply.
> I will order the Spartan II from Insight Electronics.
>
> Does the "no one project license for LogiCORE PCI" mean that I am not
> legally allowed to develop on the kit? Does it mean that I get the hardware,
> but no means to actually use the kit due to the fact that I have no access
> to it via PCI?
I am not 100% sure about it, so take it with a grain of salt,
but I believe the a one project license means that you can use LogiCORE
PCI only for the purpose of prototyping a product called A and when A is
being sold.
If you want to do another product called B, I believe the one project
license is not going to allow it legally.
In that case, you will have to shell out $5,000 for a full license. (May
let you upgrade the license from the one project license, for something
less, but I am not sure.)
You should be able to download a copy of the licensing agreement from
Xilinx's website if you search for it.
I am not paid to say anything, so I can propose alternatives
besides using Spartan-II with Xilinx's LogiCORE PCI.
You can use PLX Technology's PCI bridge chip instead of LogiCORE PCI.
I am sure the PCI bridge chip itself costs less than $20 in volume, and
you won't have to deal with licensing issues, but you may have to design
your own PCI card for it.
On the backend side of the PLX PCI bridge, you can place any FPGAs.
Besides Xilinx, almost all FPGA vendors offer a PCI IP core for
use in their own devices.
I am not a huge fan of it because it is anti-fuse, but Quicklogic has an
FPGA called QuickPCI that has a built-in PCI interface in it.
However, it is an anti-fuse device, so you can burn the chip only once,
but the design will be more secure when you sell it as a finished
product compared to SRAM-based FPGAs. (Bit stream files of SRAM-based
FPGAs can be stolen in theory, although someone from Xilinx will
certainly try to dispute that.)
However, prototyping in anti-fuse FPGAs I think can be costly.
> You have to excuse me, I am a newbie. I am an electronic engineer by
> education,
> but a programmer by profession. I need a fast coprocessor for a certain
> 'killer app',
> but I don't know much about these kits. I am almost sure a FPGA is the best
> solution,
> but I would like to know why there is such a think as 'development kits'.
Development kits exist because not everyone who wants to build
their own PCI cards have the knowledge and resources to make their own
PCI cards.
To make a PCI card, someone will realistically need,
1) An oscilloscope with at least 300MHz bandwidth
2) A PCB CAD tool
3) Nice to have a logic analyzer with at least 60 channels
4) Nice to have a PCB signal integrity tool
Getting all of those can cost as much as a buying a pretty
expensive car (> $20,000), plus not everyone has the analog skills (PCB
layout, analog circuit analysis, etc.).
So, it make sense from a business perspective that if someone has all of
the above armed with analog knowledge, that person/company probably can
serve some customers who only want to design inside the FPGA like
myself.
Of course, the PCI IP core can be a big issue, considering the price for
the license, but for that, you can use Opencores.org PCI IP core or do
your own which can take a lot of time.
> Is there also a 'final deploy' solution that is faster or cheaper?
> Or is the development kit also the card that is going to be sold to my
> customers, finally?
If you are making it in a large volume, you should make your own
PCB.
Buy FPGAs at a large volume to get volume discount.
If you make the board in volume, that should keep the costs low.
> And I noticed that this kit has an external power supply. Are there even
> cheaper boards that have about 50,000 usable gates that have no frills like
> RS232, LEDS etc and do not need an external power supply? I hope to sell
> thousands of those boards. Do you remember the ChessMachine, a popular PC
> addin card based on an ARM processor, around 1992? My project is something
> similar, but not for chess...
>
Here is the board I use for development of my PCI IP core that
was discontinued recently.
http://208.129.228.206/solutions/kits/xilinx/spartan-iipci.html
It only costs $145 for the board only.
Still, the chip used in the board is larger than the older board
(XC2S150 vs. XC2S200), so I think the price increase is reasonable.
But, they should have kept the DIME slots I think.
> Thanks for your help, I was searching the web for hours.
> I just asked Insight Electronics some questions about the PCI licensing too,
> so if you are busy please then just answer the question about 'final deploy'
> vs. 'development kit', I am a newbie and at a loss...
>
> Frank
>
You may want to check this one out before placing an order.
http://www.nallatech.com/products/dime_select/strathnuey/index.asp
I feel like the above board is better for you because Nallatech seems to
have a lot of DIME boards compared to Insight Electronics' P160 slot
which is new.
Also, you may want to post the same question at news:comp.arch.embedded
to get different answers from different people.
Kevin Brace (In general, don't respond to me directly, and respond
within the newsgroup.)
Article: 41842I can actually think of two reasons you would want to do exhaustive gate-level simulations.. (1) Logical correctness - Did synthesis work properly? (2) Gate-Level timing. Being more of an ASIC and even microprocessor designer, I have typically used static timing analysis instead of the gate-level simulation approach. (The problem is finding that "worse-case" vector set...) In practice, synthesis usually either works or fails pretty badly (simple vectors seem to find the problems). If you are working with an FPGA, the "pain" of formal verification (and even gate-level simulation for logical correctness) may be better spent just loading up the FPGA and seeing what happens. If it doesn't work, then the real fun begins.. "strut911" <strut911@hotmail.com> wrote in message news:4379d3e0.0204081930.4ac14e6b@posting.google.com... > has anyone ever used an equivalence checker to check a synthesized > netlist with the RTL code? i am thinking i can save a lot of time if i > follow this approach instead of doing exhaustive gate level sims. if > anyone has done this kind of thing, do the tools accept EDIF format > (Verplex, Formality)?Article: 41843
You mention all timing constraints were met. What about constraint coverage?
It is entierly possible to have all constraints met with only a small portion
of the design actually constrained. If your design is passing a functional
simulation and timing, but does not work, the next step is to carefully examine
your timing constraints to make sure you haven't got something important
unconstrained, followed by doing a post-route simulation to verify that the
routed design does indeed match the input design. There have been a few cases
where the xilinx tool is the culprit, but much more often it is the result of a
change in the synthesizer.
al wrote:
> We were using 3.1i and works fairly stable with no major problems. Last
> week, we loaded up the 4.1i and decided to give it a try. We used the same
> set of VHDL design files, UCF constraint and batch file. At first, tool
> seems working fine -- we are able to save compile time by about 40% and all
> timing constraints are meet. Well, not so happy yet -- the output binary
> doesn't not work in our hardware, seems like there is some sort of timing
> problem somewhere. We called up xilix hotline, this support guy by the name
> of Justin have no idea of what he is talking about -- keep telling me to do
> a post route timing simulation on my 1.6 million gate design. Anyway, bad
> tool + bad support = unhappy customer.
--
--Ray Andraka, P.E.
President, the Andraka Consulting Group, Inc.
401/884-7930 Fax 401/884-7950
email ray@andraka.com
http://www.andraka.com
"They that give up essential liberty to obtain a little
temporary safety deserve neither liberty nor safety."
-Benjamin Franklin, 1759
Article: 41844On Mon, 08 Apr 2002 17:54:09 GMT, Chip Fox <chip.f@ix.netcom.com> wrote: >Hi, > >Can anyone tells me why the VHDL code below appears to synthesize OK under >Xilinx WebPack and load into ModelSimXE and simulate OK, except that the ROM >data output is always zero? > >I know there's probably a lot of monkey-motion in this code. But I already >tried the simple versions, and out of desparation, I tried adapting something >out of a Xilinx Q&A item. > >Humbly, >Chip I think you will find the guidance you need here: http://www.fpga-faq.com/FAQ_Pages/0031_How_to_initialize_Block_RAM.htm ROMs are initialized just like RAMs, and you need to do it twice, once for the simulator, and with different syntax for synthesis (and on to the P&R tools). =================== Philip Freidin philip@fliptronics.com Host for WWW.FPGA-FAQ.COMArticle: 41845
"Theron Hicks (Terry)" wrote:
>
>
> I agree whole heartedly. I would never count on a design until I had done a Post
> P&R simulation. On the otherhand, I would never waste time with a post P&R
> simulation until I had the other levels of simulation working correctly.
I am glad I am not the only one who advocates doing a Post P&R
simulation to make sure the synthesis tool synthesized the design
correctly.
And yes, I don't do it that often because it seems to run about 1/50 to
1/100 of the speed of an RTL simulation.
Kevin Brace (In general, don't respond to me directly, and respond
within the newsgroup.)
Article: 41846Isn't there a free PCI core at opencores.org? Steve > > Does the "no one project license for LogiCORE PCI" mean that I am notArticle: 41847
Hi: we are using virtexe. there are 4 board. after several month, 2 board's virexe's several pin is almost shorted with ground, only 20 ohm. if we use it as input then all the signal is ground. if we use it as output, there will be signal on it. but compared with other signals it is only 1V for high level. and I am sure there is no short on the board. Can any one tell me what is the problem? Bests qyshengArticle: 41848
HI, Whatever the XFAE said was true.A timing simulation is a must for a million gate design.Moreover , you should have sorted almost 75% of your issues at the synthesis level. Use the timing analyzer and analyse against your constraints.Then try out other conditions to see if your design timings are stretchable.If not--then you know the problem lies in your design. One more suggestion--Use 4.2i and get POST -TRANSLATE, POST-MAPPING simulation to save your time. Don't blame the FAE---He is from my tribe ;-) regards, SANKET. Russell <rjshaw@iprimus.com.au> wrote in message news:<3CB2399D.D30C984E@iprimus.com.au>... > al wrote: > > > > We were using 3.1i and works fairly stable with no major problems. Last > > week, we loaded up the 4.1i and decided to give it a try. We used the same > > set of VHDL design files, UCF constraint and batch file. At first, tool > > seems working fine -- we are able to save compile time by about 40% and all > > timing constraints are meet. Well, not so happy yet -- the output binary > > doesn't not work in our hardware, seems like there is some sort of timing > > problem somewhere. We called up xilix hotline, this support guy by the name > > of Justin have no idea of what he is talking about -- keep telling me to do > > a post route timing simulation on my 1.6 million gate design. Anyway, bad > > tool + bad support = unhappy customer. > > Well, the easiest way is to comment out all the code except a small > piece that flashes a LED. Now keep adding in chunks of code and see > what happens...Article: 41849
Hi
I'm simulating a SpartanII Design using CLKDLLs with Modelsim XE. It
seems to me that ModelSim can't handle those String Literals in a
Schematic's autogenerated vhf file when I try to generate a 2x Clock
with the DLL. The value has to be set by hand from "2" to 2.0 .
Does anyone know of a Solution so that the REAL value is inserted
automatically instead of the String?
ModelSim's Error Message:
# ERROR: toplevel_io.vhf(148): Type error in string literal
The Code in my VHF File:
This Value needs to be set to 2.0
XLXI_4 : CLKDLL |
-- synopsys translate_off v
GENERIC MAP ( CLKDV_DIVIDE => "2" )
-- synopsys translate_on
PORT MAP (
...
Andreas Koschak
Hardware Design Engineer
Liechti AG
CH-Kriegstetten
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