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Yes, the term "gate" is an imperfect measure and is susceptible to vendor manipulation. Historically, an ASIC gate is the size of a "typical" 2-input nand gate. A 2-input nand has 4 transistors. But they can be tiny transistors or huge transistors ... hence the "typical" 2-input nand. Gil Kevin Brace wrote: > To tell you the truth, I don't really trust the gate count number > Xilinx's MAP reports (MAP is one of the backend tools before PAR. (P&R)) > because it counts RAM bits as "equivalent gates." (I personally call > this "System Gate marketing.") > Anyhow, if I totally trust the numbers MAP reports when I don't use > Block RAM or Distributed RAM, I will say that Spartan-II XC2S150 has > about 25,000 ASIC gates, and the largest XC2S200 has about 33,000 ASIC > gates. > If you don't care about 5V I/O, you can use the newer Spartan-IIE, which > the biggest chip has 300,000 system gates. > The system gate marketing seems to inflate the realistic gate count by a > factor of 6, so the actual ASIC gates will be around 50,000. > Also, when you say ASIC gates, do you mean, 1 ASIC gate = 1 NAND gate? > (1 NAND gate I believe uses 4 transistors.) > I am sure about the performance because it can vary by design. > > > > Kevin Brace (In general, don't respond to me directly, and respond > within the newsgroup.) > > > > Gil Herbeck wrote: > >>Thanks. At least you have used Xilinx Spartan-II. I've never done >>an FPGA and don't know Spartan-II from a Virtex from a ... (I'm an >>ASIC guy). >> >>Maybe you can comment on capacity and performance with the Spartan-II? >> >>Gil >> >>Article: 41976
I don't concur. It is very, no extremely, rare that the P&R tools screw up a
design. A post P&R won't tell much of anything that a thorough static timing
analysis and functional (pre-PAR) simulation won't tell you. It can actually be
rather dangerous, as it can be very difficult to come up with a set of vectors
that cover all paths, especially in a large design.
To check on the synthesized results, use the mapped output from the synthesis
for a post synthesis functional simulation. It will run a lot faster than the
timing annotated post PAR simulation.
Theron Hicks wrote:
> "Kevin Brace" <ihatespam99kevinbraceusenet@ihatespam99hotmail.com> wrote in
> message news:a8tpjg$5a0$1@newsreader.mailgate.org...
> >
> >
> > "Theron Hicks (Terry)" wrote:
> > >
> > >
> > > I agree whole heartedly. I would never count on a design until I had
> done a Post
> > > P&R simulation. On the otherhand, I would never waste time with a post
> P&R
> > > simulation until I had the other levels of simulation working correctly.
> >
> >
> > I am glad I am not the only one who advocates doing a Post P&R
> > simulation to make sure the synthesis tool synthesized the design
> > correctly.
> > And yes, I don't do it that often because it seems to run about 1/50 to
> > 1/100 of the speed of an RTL simulation.
>
> I just assumed that everyone did a post P & R simulation before commiting a
> design. I typically do so with a higher clock frequency than I will
> actually use to verify how much design headroom exists.
>
> Theron
> >
> >
> >
> > Kevin Brace (In general, don't respond to me directly, and respond
> > within the newsgroup.)
--
--Ray Andraka, P.E.
President, the Andraka Consulting Group, Inc.
401/884-7930 Fax 401/884-7950
email ray@andraka.com
http://www.andraka.com
"They that give up essential liberty to obtain a little
temporary safety deserve neither liberty nor safety."
-Benjamin Franklin, 1759
Article: 41977Ray Andraka wrote: > I don't concur. It is very, no extremely, rare that the P&R tools screw up a > design. A post P&R won't tell much of anything that a thorough static timing > analysis and functional (pre-PAR) simulation won't tell you. If the design had a life, health or safety impact, I would use every verification tool in the toolbox, including post PAR timing simulation. Unless that applies, I agree with Ray that there is little reason to do so. I've found exactly one problem with post P&R timing simulations, and it was my error in entering the static timing constraints. Oh, and don't forget to check for tilde. http://toolbox.xilinx.com/docsan/xilinx4/data/docs/dev/trace8.html "In a timing report, a tilde (~) preceding a delay value indicates that the delay value is approximate. Values with the tilde cannot be calculated exactly because of excessive delays, resistance, or capacitance on the net, that is, the path is too complex to calculate accurately." -- Phil HaysArticle: 41978
hello
i am new to vhdl and digital design.
if we just observe the following code
case1)
p1 : process
begin
if clk'event and clk ='1' then
for i in 0 to 9 loop
result <= mul1 * mul2; -- mul1 and mul2 and result are defined
--as signals earlier
end loop;
end p1;
case2) p1 : process
variable result;
begin
if clk'event and clk ='1' then
for i in 0 to 9 loop
result := mul1 * mul2; -- unlike in case1 ONLY mul1 and mul2
-- are defined as signals
end loop;
end p1;
so if we observe the two codes the loop will be executed in just one clock
cycle in case2 whereas in case1 only for one i(loop index) it will be executed.
i think i am clearing in saying this.
now my doubt is
if we synthesise both the codes what makes the difference?
also should i need to initialise any counter in case1 and get the
functionality as in case2?
how should we interpret the result of the synthesis?
also if i use only variables in my modelling
then will it be synthesized accurately?
can anyone help me.
thank u
prasad.
Article: 41979First I must say I work at an IP Development company (Parthus Technologies). With that said, my group develops hardware-based acceleration products like Hardware-based Java JIT compilers, Hardware based decompilers, and various other things. I say that because you need to know what type of logic we develop to guage how the FPGA speeds are running. These designs run comfortably at 200MHz in Low-Power TSMC 0.18um process. In a Virtex-E 1600 they easily achieve 25MHz (with nominal tuning I'd say 33MHz). To say the least you're not going to break any speed records here. The Hardware-based acceleration products are called MachStream. We have a development board that includes an ARM9-based SoC ( InfoStream ) that is interfaced through the memory bus to the Virtex. A serial cable is included for comunication to a PC. You can read about InfoStream and MachStream at http://www.parthus.com . Though it is not generally sold as a development platform, if you would like more information about the board and other IP development efforts you'll want to contact me at work. mailto: john.derrick@parthus.com Thanks, John Derrick "Gil Herbeck" <gil@radix20.com> wrote in message news:3CB61C7B.700@radix20.com... > I need to prototype an ASIC design and am looking for > advice on type of FPGA and on FPGA board as well. > > The board needs to have an ARM9, external memory, an > interface to a PC (serial is ok), the FPGA (or ASIC), > and a header to plug in a daughter card with some pins > routed to the FPGA. > > The ASIC will have between 100K and 500K ASIC Logic > Gates. It will run at about 150 MHz. It needs about > 200 KB of internal RAM. And it will have a lot of > multipliers. There will probably be some pipelining > in the ASIC to meet speed - and probably deeper pipes > in the FPGA. We want to match the FPGA to the ASIC > as closely as possible. > > I think the key factors in FPGA selection are: > - Capacity. We want to fit in one FPGA. > - Performance. We want to run at speed. > - "ASIC-like" synthesis library (see below)? > - Availability of board described above. > > "ASIC-like" synthesis library... The datapath > content on the ASIC may force us to use one of the > datapath synthesis tools. These tools don't support > FPGA architectures directly. I've heard that since > the Actel architecture is "fine-grain" that it works > best for these types of designs. > > Any advice will be much appreciated. > > Thanks, > Gil >Article: 41980
Jason Zimmernann wrote:
>
> I am currently thinking about using the Opencores PCI Bridge as a
> starting point for development. I need to develop a PCI bridge with a
> switchable backend (or maybe just the IBM CoreConnect bus, depending
> on how easy it would be to drive it with an FSM instead of a
> processor).
>
> My question: Has ANYONE had ANY experience, good or bad, with the
> Opencores bridge? I notice that a lot of people decide to write their
> own, and I'm all for that normally, but I would like to try and
> minimize the amount of work that goes into the PCI interface.
Although I haven't used Opencores.org PCI IP core myself, from
my own experience doing my own PCI IP core, it might not be a good idea
to use it in a commercial product. (Your application sounds like a
commercial product to me.)
Yes, I guess I can get criticized for saying that because some may argue
that it is free and that's the only one available, but whoever doesn't
like my comment should read this column first before criticizing me.
http://www.eetimes.com/story/OEG20010326S0018
I know not everyone with Jim Turley's pointed opinions all the time (I
totally disagree with his latest "Software engineers will replace
hardware engineers because C will replace HDL." argument.), and when he
wrote this article, he still worked at ARC Cores, so his opinions were
probably biased. (Since then he has started his own consulting
business.)
I am sure it is in ARC Cores interest to trash freely available IP cores
because if there were so good, I am sure most commercial IP core
companies will be out of business by now, but he is still right that in
practice, no one seems to use those freely available IP cores in any
'serious' commercial products that I have heard of.
However, I think it is possible to develop higher quality free IP cores,
but the current members' mentality seems to be, "Let's just upload the
code. Who cares if it works or not."
As long as that mentality persists, no one will likely use their IP
cores in commercial products.
So, whatever I say from here will be biased because I have some
experience doing my own PCI IP core.
In that case of Opencores.org PCI IP core, first of all, the whole P&R
log file posted on their website seems to indicate that it met 33MHz
PCI's stringent Tsu < 7ns requirement, so that's good.
They wrote their own testbench code, so probably it will probably work
fine in most systems, however, it is always possible that they forgot to
test something, and it may not work well in some computers.
However, the biggest the I think is, looking at their code, they seem to
do low level gate level coding in HDL, which makes the code very hard to
understand besides the original authors. (I am aware that it is always
hard to understand someone else's work, but this one is pretty bad I
think.)
I think they should have used schematics instead if they were going to
code that way.
For an open source project, I think it is fatal to code it in a way that
no one else other than the original authors can understand.
I will guess that they did so in order to meet 33MHz PCI's Tsu < 7ns
requirement, but after months of tweaking my design, I can get mine to
easily meet Tsu < 7ns without resorting to low level gate level coding.
(I used RTL coding to keep the code 'sane'.)
Not to be mistaken, I do have some portions like a parity generator
that's in gate level coding, but almost all the control logic part
(i.e., FSM) is all done in RTL.
So, my point is, if their PCI IP core works fine in its present form
(The user not having to modify the PCI IP core itself. In other words,
treating it as a blackbox.), that's good for you, but if you have to
modify it to meet your needs or fix bugs, you are on your own, and with
the way they coded it, it will likely be very hard to do so.
Sure, the original authors will always be available probably to help you
out, and they will likely fix the bugs, but how can you force them if
you are not paying them anything?
Even if they fix the problem eventually, the pace may not be as fast as
you may like, and your company's product might be late to the market.
> As you
> can see from my project description below, there is a LOT more to do
> here than just the PCI. (I do realize that yes, I could buy the
> Xilinx core, but two things concern me with that route: i would like
> to perform some of the PCI central resource functions in the FPGA
> alongside the master core--it would be ideal to have the Xilinx board
> drive a bus outside of a PC, and there is some custom wiring to do
> here as well as FPGA programming--, and the price is a little steep
> for me--at least until I can justify it.)
>
I see your point.
$2,000 for a single license or $5,000 for a regular license is a lot of
money, and if you cannot sell enough of them, it can end up being very
costly.
Someone else said this in this newsgroup sometime ago, so I will repeat
it (I am not getting paid to say so.), but how much is the license
compared to your monthly salary?
Isn't it at most two months worth? (The original poster said two weeks.)
If you consider that you might have to 'fight' to get the PCI IP core
working, you might be better off paying for a PCI IP core.
Alternatively, how about if you use to PLX's PCI bridges and put
your favorite FPGA on the backend, or Quicklogic's QuickPCI which has a
built-in PCI in it? (All Quicklogic FPGAs are all anti-fuse.)
At least you won't have to pay a one time licensing fee.
> (My application:
> On a Xilinx FPGA, there will be the PCI bridge, a processor core, and
> a state machine. The Xilinx board talks to a digital transciever
> (basically a nice A/D and D/A with Intersil (formerly Harris) DDC and
> DUC chips) over the PCI bus. The processor will be used for some
> configuration tasks, but while no configuration is going on, the state
> machine will send data to and gather data from the transciever.
> Probably on another FPGA I will do some coding/decoding operations.)
>
> thanks!
> j.
>
> -------------------
> Jason W. Zimmermann
Throughout this posting I have been pretty much a nay-sayer, but
at least I will say that, I don't work for any of the companies I
mentioned, neither do I own stocks of those companies.
Although I mentioned several commercial products that you can use, I
don't necessarily endorse any of those products, and neither do I get
paid to talk about them.
I don't have anything against Opencores.org, but to say the least, I
think they have too many projects going on, and the quality of the IP
cores hasn't improved that much since it got started.
Kevin Brace (In general, don't respond to me directly, and respond
within the newsgroup.)
Article: 41981Thanks. It is starting to look like the performance is going to be a problem. What is your sense regarding capacity? (I'm using the TSMC 0.13um process, but I think I can correlate to your process.) Can you comment on the comparison of your ASIC gate count (or square mm) to your FPGA implementation? What I'm trying to get a feel for is conversion of ASIC "gates" to FPGA "resources". What was the size of the ASIC that corresponds to your 25-33MHz Virtex-E 1600? Gil John E. Derrick wrote: > First I must say I work at an IP Development company (Parthus Technologies). > > With that said, my group develops hardware-based acceleration products like > Hardware-based Java JIT compilers, Hardware based decompilers, and various > other things. I say that because you need to know what type of logic we > develop to guage how the FPGA speeds are running. These designs run > comfortably at 200MHz in Low-Power TSMC 0.18um process. In a Virtex-E 1600 > they easily achieve 25MHz (with nominal tuning I'd say 33MHz). To say the > least you're not going to break any speed records here. The Hardware-based > acceleration products are called MachStream. > > We have a development board that includes an ARM9-based SoC ( InfoStream ) > that is interfaced through the memory bus to the Virtex. A serial cable is > included for comunication to a PC. You can read about InfoStream and > MachStream at http://www.parthus.com . Though it is not generally sold as a > development platform, if you would like more information about the board and > other IP development efforts you'll want to contact me at work. mailto: > john.derrick@parthus.com > > Thanks, > John Derrick > > > "Gil Herbeck" <gil@radix20.com> wrote in message > news:3CB61C7B.700@radix20.com... > >>I need to prototype an ASIC design and am looking for >>advice on type of FPGA and on FPGA board as well. >> >>The board needs to have an ARM9, external memory, an >>interface to a PC (serial is ok), the FPGA (or ASIC), >>and a header to plug in a daughter card with some pins >>routed to the FPGA. >> >>The ASIC will have between 100K and 500K ASIC Logic >>Gates. It will run at about 150 MHz. It needs about >>200 KB of internal RAM. And it will have a lot of >>multipliers. There will probably be some pipelining >>in the ASIC to meet speed - and probably deeper pipes >>in the FPGA. We want to match the FPGA to the ASIC >>as closely as possible. >> >>I think the key factors in FPGA selection are: >>- Capacity. We want to fit in one FPGA. >>- Performance. We want to run at speed. >>- "ASIC-like" synthesis library (see below)? >>- Availability of board described above. >> >>"ASIC-like" synthesis library... The datapath >>content on the ASIC may force us to use one of the >>datapath synthesis tools. These tools don't support >>FPGA architectures directly. I've heard that since >>the Actel architecture is "fine-grain" that it works >>best for these types of designs. >> >>Any advice will be much appreciated. >> >>Thanks, >>Gil >> >> > >Article: 41982
Hello!
Has anyone experienced any problems with Nios 2.0 (build 224) in Quartus II
2.0? I can't generate it with SOPC builder - it always terminates with an
error. Even Altera representatives and their official support were of no
help (!?) until recently - they said it will be fixed in next update. My OS:
win98.
Error excerpt:
--------------------------------------------------------
# 2002.03.26 16:47:16 (*) Running Generator Program for boot_monitor
Bad file boot_monitor_contents.srec at
c:/vhdl/excalibur/nios2/bin/format_conversion_utils.pm line 923.
Error: Generator program
for module 'boot_monitor' did NOT run successfully.
---------------------------------------------------------
Regards,
Matjaz Finc
Article: 41983Ray Andraka <ray@andraka.com> writes: > Even if you write your own you run into the attributes and generics > issue. Attributes pass through to the edif netlist but generally have no > meaning within VHDL. It is through user attributes that we can set > parameters that do not appear in the code. Generics are used to pass > parameters into VHDL components, but can't be passed out to the netlist > (generics can be thought of as parameter INPUTs to your code). The > requirement for both comes up because there are primitives in the FPGA > which require some sort of parameterization , be it an initialization > value (sucha s for RAMs, LUTs) or to set up a mode in a black box (such as > a DCM) that is set outside of the context of the netlist of your > design. Without wishing to ignite anything - the Altera LPMs use the generics for simulation, which Synplify passes through the EDIF netlist on the blackboxes and then the P&R tool deals with it from there. Any chance of Xilinx imitating this? > The safest way to deal with these, I think, is to use a proxy that your > code reads and generates both the attribute and the generic value from. > Then to update, change the proxy so that the change automatically > propagates to both parameters. > Is there a 'standard' way of doing this or does everyone do it their own way? Any interest in coming up with a standard way of doing it if there isn't already one? Also, it seems I have to put a component declaration in for synth, even though I already have the unisim.vcomponents library for simulation, so yet more duplication! Sorry if I sound grumpy, I was in early :-) Martin -- martin.j.thompson@trw.com TRW Conekt, Solihull, UK http://www.trw.com/conektArticle: 41984
Kevin Brace <ihatespam99kevinbraceusenet@ihatespam99hotmail.com> wrote in message news:<a9518u$6ui$1@newsreader.mailgate.org>... > Speedy Zero Two wrote: > > > > > I have used the older Spartan-II PCI Development Kit with > > > XC2S150-5CPQ208 (A smaller chip than the board you are interested.) for > > > my own PCI IP core development, and I will call myself a happy customer > > > of that board considering how cheap it was. ($145 for the older one. The > > > newer one is a little more expensive.) > > > I used the free ISE WebPACK throughout the development, and when I did > > > some simple testing of the PCI card with my PCI IP core inside using two > > > computers I had, the PCI card worked fine in both computers. > > > > > > > a credit to your design. > > > > > Thanks. > > > > > > > I spoke to an apps engineer and he was vague as to what was available via > > the design center. > > can you help in explaining? > > > > > As of now, the reference design for Spartan-II PCI 200 hasn't > been uploaded yet, although the reference design for the older > Spartan-II PCI 150 card is still there. > The older reference design included a one that turns on and off an > on-board LED connected to one of the Spartan-II's pin, and another one > that makes the Spartan-II PCI card an 8MB memory card. > There were both written in VHDL, and it was for LogiCORE PCI only. > I don't know what the new reference design is going to be like, but I > will guess that it will likely be an 8MB memory card reference design > for LogiCORE PCI again. > Unless you are going to shell out $2,000 for a one project license or a > $5,000 regular license, the reference design will be pretty useless. > Although you should be able to use Opencores.org PCI IP core with it. > > > > > > If I purchase this kit , do I get a working PCI design ?/ > > > > Thanks for your help > > > > Dave > > > > (reply direct if you like, the spammers do :-) ) > > > Not really, unless you are going to use Opencores.org PCI IP > core or do your own PCI IP core. > The previous Spartan-II PCI card came with a .mcs file for the > Configuration PROM on the card that contained the LED reference design I > mentioned, but you cannot carve out the LogiCORE PCI from it, and attach > your own backend design. (Maybe it is not absolutely impossible to do > so, but to do that, you will have to deal with the bit stream fuse map. > I will rather develop my own PCI IP core than doing so risking the > chip.) > When I first plugged in the PCI card into a computer around August of > 2001, the card already had the LED design bit stream installed, so if > you buy the card, and plug it into a computer, the card will work, but > it will be pretty useless because you won't be able to modify the > design. > > > > Kevin Brace (In general, don't respond to me directly, and respond > within the newsgroup.) I'm wondering that there is no reply from somebody who has tested the PCI opencore on that demo-board. IS there really nobody out there?? (sorry, but I want to go for sure before investigating) MartinArticle: 41985
In article <22f10f27.0204111935.2d488e51@posting.google.com>, K PRASAD
<prasadkdnvs@rediffmail.com> writes
>hello
>i am new to vhdl and digital design.
>if we just observe the following code
>
>case1)
>
> p1 : process
> begin
> if clk'event and clk ='1' then
> for i in 0 to 9 loop
> result <= mul1 * mul2; -- mul1 and mul2 and result are defined
> --as signals earlier
> end loop;
> end p1;
>
>case2) p1 : process
> variable result;
> begin
> if clk'event and clk ='1' then
> for i in 0 to 9 loop
> result := mul1 * mul2; -- unlike in case1 ONLY mul1 and mul2
> -- are defined as signals
> end loop;
> end p1;
>
> so if we observe the two codes the loop will be executed in just one clock
> cycle in case2 whereas in case1 only for one i(loop index) it will be executed.
> i think i am clearing in saying this.
> now my doubt is
>
> if we synthesise both the codes what makes the difference?
>
> also should i need to initialise any counter in case1 and get the
> functionality as in case2?
> how should we interpret the result of the synthesis?
> also if i use only variables in my modelling
> then will it be synthesized accurately?
>
>can anyone help me.
>thank u
>prasad.
The "trick" with loops is to "unroll" the loop.
So instead of for i in 0 to 9 loop, think of it as
case1)
result <= mul1 * mul2; -- i = 0
result <= mul1 * mul2;
result <= mul1 * mul2;
result <= mul1 * mul2;
result <= mul1 * mul2;
result <= mul1 * mul2;
result <= mul1 * mul2;
result <= mul1 * mul2;
result <= mul1 * mul2;
result <= mul1 * mul2; -- i =9
Now you have made 10 assignments to the same signal, but NO TIME HAS
PASSED - all assignments schedule events 1 delta cycle in the future.
Then, because of the way signals work, each later assignment cancels the
previous assignment - so the code is equivalent to writing
result <= mul1 * mul2;
Note this is because you are in a process, and statements execute
sequentially in a process.
On our courses, we call this "last assignment wins", i.e. when making
multiple assignments to a signal in a process all in the same delta
cycle.
Finally, because you are making a signal assignment in a clocked
process, result will become a set of flip-flops.
case2)
result := mul1 * mul2; -- i = 0
result := mul1 * mul2;
result := mul1 * mul2;
result := mul1 * mul2;
result := mul1 * mul2;
result := mul1 * mul2;
result := mul1 * mul2;
result := mul1 * mul2;
result := mul1 * mul2;
result := mul1 * mul2; -- i =9
In this case, result updates straight away because it is a variable.
By the end of the loop, result contains mul1 * mul2.
However this time, nothing will happen. Why? Because you have not
assigned result to a signal, and variables are local to the process. So
result cannot be seen outside the process, hence the synthesis tool
should optimise it away.
For synthesis of signals in a clocked process :
In clocked processes a signal assignment results in flip-flops
For synthesis of variables in a clocked process :
In a clocked process, if you read a variable value then assign it,
you get a flip-flop.
In a clocked process, if you assign a variable then read it, you get
a piece of wire.
In your example above, you get a piece of wire, but then it is not seen
outside the process so it gets optimised to nothing.
Regarding your questions, neither example is a counter, if I've
understood you correctly.
And yes, you can use variables as long as you understand the rules
above, and remember to copy its value into a signal if you want to see
it outside the process.
I hope this helps,
Alan
--
Alan Fitch
DOULOS Ltd.
Church Hatch, 22 Market Place, Ringwood, Hampshire BH24 1AW, United Kingdom
Tel: +44 1425 471223 Email: alan.fitch@doulos.com
Fax: +44 1425 471573 Web: http://www.doulos.com
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are not the views of Doulos Ltd., unless specifically stated.
Article: 41986"Matjaz Finc" <matjaz.finc@fe.uni-lj.si> wrote in message news:a961r4$o9$1@planja.arnes.si... > Hello! > > Has anyone experienced any problems with Nios 2.0 (build 224) in Quartus II > 2.0? I can't generate it with SOPC builder - it always terminates with an > error. Even Altera representatives and their official support were of no > help (!?) until recently - they said it will be fixed in next update. My OS: > win98. Though I can't help with the specifics, I have found that all of the tools run far more smoothly under windows 2k. I used to dual-boot, but frankly I don't bother with win9x now. Another tip is to make sure all tools run from paths with no spaces. The batch command line scripts etc have a habit of sometimes not working with spaces. (e.g. Leonardo integration etc) PaulArticle: 41987
i am also an ASIC designer who has to wear the hat of an FPGA guy. actually, i prefer FPGA because of the error margin you can have compared to ASIC. anyways, your goal of meeting exactly the same speed as your ASIC is probably unachievable. usually, there has to be some sort of tradeoff. i think one of the biggest mistakes in ASIC prototyping on FPGAs is the belief that you can just dump the code. the best FPGA code is written for an FPGA. likewise for an ASIC. also, an FPGA is more unforigiving than an ASIC if you do not follow good design rules. the layers of logic to meet timing is also less because you are not using ASIC cells directly. if i were you, i would start with the Xilinx Virtex-2 series. they are the fastest in the xilinx family and the XC2V6000 is quite large (6-million Virtex-2 Gates which equates to about 200-300,000 ASIC gates, maybe a little more. gate count in FPGA marketing speak is very unreliable. there are many tricks that you might have to pull also. depending on where your critical path may be, you might have to instantiate FPGA specific logic structures using xilinx coregen. an example would be a mux in your datapath. coregen would create the mux in an optimized fashion, probably using tristate buffers or something. the gurus on this board know this kind of thing the best. also, you will have to make a choice between designing your own board or buying an off the shelf XC2V6000 board (haven't seen one yet) and interfacing it to an ARM processor through cables. my suggestion would be to buy a ready made FPGA system initially to run basic tests and get familiar with the tool flow and at the same time start on a custom board design. the last option would be to just buy/rent one of those ASIC prototyping tools. these will be expensive though, but if your time to market and manpower is worth more than the cost of the system, you might want to go with the proven package. just my two cents. good luck. maybe you can post your results or progress. i am interested to see how it goes. chrisArticle: 41988
Ray,
Please enlighten me. In 4.1 the simulation options are
1. Simulate Behavioral VHDL Model
2. Simulate Post-Translate VHDL Model
3. Simulate Post-Map VHDL Model
4. Simulate Post-Place & Route VHDL Model
Can you clarify what each of these really accomplishes?
#1, I assume is simulation of the code as written and assumes delta delays
I am uncertain as to precisely what #2 and #3 do.
#4 I assume is the actually delays including routing, etc.
If I understand correctly you use #3 as your last level of simulation.
Also, you make a comment that seems to imply that the different levels of simulation
require different test vectors. (I would have thought that each would use the same
test vectors.) Is that because of the real world of chip delays vs. ideal delays?
Another comment, I have seen some realy screwed up placements in the floorplanner.
I assume that you must be floorplanning your designs quite carefully. How do you do
that? (floorplanner vs. UCF vs. ??) If you are using something other than
floorplanner, can you recommend a tutorial, etc.?
Perhaps I should be just setting things up very carefully with the timing
constraints. I am having trouble figuring how to set timing constraints for
critical internal signals.
Thanks,
Theron Hicks
Ray Andraka wrote:
> I don't concur. It is very, no extremely, rare that the P&R tools screw up a
> design. A post P&R won't tell much of anything that a thorough static timing
> analysis and functional (pre-PAR) simulation won't tell you. It can actually be
> rather dangerous, as it can be very difficult to come up with a set of vectors
> that cover all paths, especially in a large design.
>
> To check on the synthesized results, use the mapped output from the synthesis
> for a post synthesis functional simulation. It will run a lot faster than the
> timing annotated post PAR simulation.
>
> Theron Hicks wrote:
>
> > "Kevin Brace" <ihatespam99kevinbraceusenet@ihatespam99hotmail.com> wrote in
> > message news:a8tpjg$5a0$1@newsreader.mailgate.org...
> > >
> > >
> > > "Theron Hicks (Terry)" wrote:
> > > >
> > > >
> > > > I agree whole heartedly. I would never count on a design until I had
> > done a Post
> > > > P&R simulation. On the otherhand, I would never waste time with a post
> > P&R
> > > > simulation until I had the other levels of simulation working correctly.
> > >
> > >
> > > I am glad I am not the only one who advocates doing a Post P&R
> > > simulation to make sure the synthesis tool synthesized the design
> > > correctly.
> > > And yes, I don't do it that often because it seems to run about 1/50 to
> > > 1/100 of the speed of an RTL simulation.
> >
> > I just assumed that everyone did a post P & R simulation before commiting a
> > design. I typically do so with a higher clock frequency than I will
> > actually use to verify how much design headroom exists.
> >
> > Theron
> > >
> > >
> > >
> > > Kevin Brace (In general, don't respond to me directly, and respond
> > > within the newsgroup.)
>
> --
> --Ray Andraka, P.E.
> President, the Andraka Consulting Group, Inc.
> 401/884-7930 Fax 401/884-7950
> email ray@andraka.com
> http://www.andraka.com
>
> "They that give up essential liberty to obtain a little
> temporary safety deserve neither liberty nor safety."
> -Benjamin Franklin, 1759
Article: 41989Gil, It might be worth your while to take a look at Altera's Excalibur ARM FPGA. It's a device that put an ARM 922T processor on the same die as a 100K, 400K, or 1M marketing gate FPGA array (if you have good idea of the number of registers in your design, it's better to use that to determine size requirements rather than ASIC gates). Inside the Excalibur part, the ARM will run at 200 MHz and is attached (via AMBA AHB bus) to 256K Bytes SRAM, 128K Bytes dual-port SRAM, an SDRAM controller, a serial port, and several other peripherals. The device is available today and Altera sells a development board with the 1M gate version of the part on it. The development board also has PMC connectors on it for expansion daughter cards. You can get more details on Altera's web site. In case you're not familiar with the clocking differences between an FPGA and an ASIC, I should point out that the much-used practice of gating clocks in ASICs is generally a big no-no in FPGAs. Synplicty's Certify is a tool which can convert gated-clocks in your design to the more FPGA-friendly use of clock enables if you don't want to do it manually. There's sort of a trade-off between keeping your design as close to your ASIC as possible (gated clocks) and getting the most speed out of the FPGA (clock enables). -Pete- Gil Herbeck <gil@radix20.com> wrote in message news:3CB61C7B.700@radix20.com... > I need to prototype an ASIC design and am looking for > advice on type of FPGA and on FPGA board as well. > > The board needs to have an ARM9, external memory, an > interface to a PC (serial is ok), the FPGA (or ASIC), > and a header to plug in a daughter card with some pins > routed to the FPGA. > > The ASIC will have between 100K and 500K ASIC Logic > Gates. It will run at about 150 MHz. It needs about > 200 KB of internal RAM. And it will have a lot of > multipliers. There will probably be some pipelining > in the ASIC to meet speed - and probably deeper pipes > in the FPGA. We want to match the FPGA to the ASIC > as closely as possible. > > I think the key factors in FPGA selection are: > - Capacity. We want to fit in one FPGA. > - Performance. We want to run at speed. > - "ASIC-like" synthesis library (see below)? > - Availability of board described above. > > "ASIC-like" synthesis library... The datapath > content on the ASIC may force us to use one of the > datapath synthesis tools. These tools don't support > FPGA architectures directly. I've heard that since > the Actel architecture is "fine-grain" that it works > best for these types of designs. > > Any advice will be much appreciated. > > Thanks, > Gil >Article: 41990
"Jim Raynor" <chris@ultrasonix.com> schrieb im Newsbeitrag news:6Bjt8.529$UH1.98590@news2.telusplanet.net... > hi, > > Does anyone know where to get a complete price list for all the Xilinx's > FPGAs (Virtex 2, Virtex E, Spartan 2 E, etc)? The price list doesn't have > to be accurate 'cause I just want to get an idea which FPGAs I am going to > use in the new design in term of processing power and $$$. www.nuhorizons.com -- MfG FalkArticle: 41991
Hello, I have a question. Is it possible to do single reads and writes to a DDR SDRAM? I am designing a simple SDRAM controller and don't want to use the burst feature. I don't see how you could set the burst length to 1 in the mode register. It only offers 2,4,8 or full page. The remaining possibilities say "reserved". I am using a Micron part. Is it possible? I have taken a reference design written in VHDL, rewrote it in verilog and modified it to only handle single reads/writes. It originally supported a burst length of 4. I am getting ready to test it and beginning to wonder if it is possible and if so what the sequence to set if would be. Thanks, GregArticle: 41992
I'm interfacing a Spartan2 (the 150 part) with a small embedded PC via ISA/PC-104. There are no problems having the PC write into the FPGA, but we cannot get the FPGA to interface properly when the PC attempts a read from the FPGA. I'm certain it is not our VHDL implementation as the inport and outport code are practically the same (we split the functionality up since we knew exactly how many of each port we needed anyway). We merely decode the address and look at the /IOR and /IOW signal for the appropriate operation and look at the LSB of the address and the /BHE signal to determine an 8 bit or 16 bit operation. Anyway, concerning the ports the PC reads from. We latch data into them which sits there available for the PC to read. When we bring the output of those latches out to pins it is correct, however, when we look at the output from the tristates onto the data bus the signal is weak and noisy. Therefore, the PC always reads a value of zero on the data bus (though it appears to be getting above 3.3V which should satisfy the TTL standard, which has me a bit perplexed). When we synthesize and P&R the design it defaults to OBUFT_S_12 tristates. I was wondering if increasing them to 24mA tristates might help since I'm not sure of the drive necessary when driving the ISA data bus. Or perhaps using an external IC such as a 74HCT245 or something might help. I'd be grateful if anyone could give me some insight into this problem. Thanks everyone. SeanArticle: 41993
SNUG Boston 2002
September 23 - 24, 2002
Boston Marriott Newton Hotel
CALL FOR PAPERS!
Share your experiences - the success of our users group depends on the
active participation of users who are willing to share their experiences
with others. If you have experiences with Synopsys tools that would be
of interest to other users, you are encouraged to present at SNUG Boston
2002.
The Call For Papers for SNUG Boston 2002 is open until May 3, 2002.
Full information about the conference, and topics of interest, is
available at http://www.snug-universal.org/northamerica/na_boston.htm
Dates for Authors to Remember
March 25 - May 3, 2002 Call for Papers
May 15, 2002 Notification of Acceptance
June 10, 2002 In-Depth Outline due
July 1, 2002 Draft Paper due
July 22, 2002 Final Paper due for CD
August 5, 2002 Draft Slides due
August 19, 2002 Final Slides due for CD and proceedings book
September 23-24 , 2002 SNUG Boston 2002 Conference
Thank you,
Brian Kane
SNUG Boston Technical Committee Chairperson
Article: 41994Set the memory to full page mode and abort the operation after one cycle. "Greg" <gsletch@yahoo.com> wrote in message news:1c163be7.0204120615.1a3ac30c@posting.google.com... > Hello, > > I have a question. Is it possible to do single reads and writes to a > DDR SDRAM? I am designing a simple SDRAM controller and don't want to > use the burst feature. I don't see how you could set the burst length > to 1 in the mode register. It only offers 2,4,8 or full page. The > remaining possibilities say "reserved". I am using a Micron part. Is > it > possible? I have taken a reference design written in VHDL, rewrote it > in verilog and modified it to only handle single reads/writes. It > originally supported a burst length of 4. I am getting ready to test > it and beginning to wonder if it is possible and if so what the > sequence to set if would be. > > Thanks, > GregArticle: 41995
One cycle is still 2 transfers, isn't it? I'd suggest that on the reads you ignore the word you don't want and on the writes use the DM bits to mask off the bytes. If you don't want to use the burst feature, why not design a single data rate SDRAM controller? You won't have better access times by going DDR, only better data transfer because of bursts. name wrote: > Set the memory to full page mode and abort the operation after one cycle. > > "Greg" <gsletch@yahoo.com> wrote in message > news:1c163be7.0204120615.1a3ac30c@posting.google.com... > > Hello, > > > > I have a question. Is it possible to do single reads and writes to a > > DDR SDRAM? I am designing a simple SDRAM controller and don't want to > > use the burst feature. I don't see how you could set the burst length > > to 1 in the mode register. It only offers 2,4,8 or full page. The > > remaining possibilities say "reserved". I am using a Micron part. Is > > it > > possible? I have taken a reference design written in VHDL, rewrote it > > in verilog and modified it to only handle single reads/writes. It > > originally supported a burst length of 4. I am getting ready to test > > it and beginning to wonder if it is possible and if so what the > > sequence to set if would be. > > > > Thanks, > > GregArticle: 41996
For a DDR you -must- do an even number of data transfers. At 2 per clock, it's impossible not to. Think of it as 1,2,4 instead of 2,4,8. Be aware of odd address starts, and burst wrap. Use the DQM lines to block writes, ignore the reads. In my design I set the burst to max length, and terminated the burst when I was done. (Or ignored it if I had nothing else to do.) I did find a bug in the Micron model relating to DQM. Be careful. EMail me if you need more help. On 12 Apr 2002 07:15:35 -0700, gsletch@yahoo.com (Greg) wrote: >Hello, > >I have a question. Is it possible to do single reads and writes to a >DDR SDRAM? I am designing a simple SDRAM controller and don't want to >use the burst feature. I don't see how you could set the burst length >to 1 in the mode register. It only offers 2,4,8 or full page. The >remaining possibilities say "reserved". I am using a Micron part. Is >it >possible? I have taken a reference design written in VHDL, rewrote it >in verilog and modified it to only handle single reads/writes. It >originally supported a burst length of 4. I am getting ready to test >it and beginning to wonder if it is possible and if so what the >sequence to set if would be. > >Thanks, >GregArticle: 41997
FWIW, I would -never- try to drive an ISA bus with a 3.3V part. Get a 5V level shifter in there. YMMV, but that's my story, and I'm sticking to it. On 12 Apr 2002 08:35:37 -0700, creon100@yahoo.com (Sean) wrote: >I'm interfacing a Spartan2 (the 150 part) with a small embedded PC via >ISA/PC-104. There are no problems having the PC write into the FPGA, >but we cannot get the FPGA to interface properly when the PC attempts >a read from the FPGA. I'm certain it is not our VHDL implementation >as the inport and outport code are practically the same (we split the >functionality up since we knew exactly how many of each port we needed >anyway). We merely decode the address and look at the /IOR and /IOW >signal for the appropriate operation and look at the LSB of the >address and the /BHE signal to determine an 8 bit or 16 bit operation. > >Anyway, concerning the ports the PC reads from. We latch data into >them which sits there available for the PC to read. When we bring the >output of those latches out to pins it is correct, however, when we >look at the output from the tristates onto the data bus the signal is >weak and noisy. Therefore, the PC always reads a value of zero on the >data bus (though it appears to be getting above 3.3V which should >satisfy the TTL standard, which has me a bit perplexed). When we >synthesize and P&R the design it defaults to OBUFT_S_12 tristates. I >was wondering if increasing them to 24mA tristates might help since >I'm not sure of the drive necessary when driving the ISA data bus. Or >perhaps using an external IC such as a 74HCT245 or something might >help. I'd be grateful if anyone could give me some insight into this >problem. Thanks everyone. > >SeanArticle: 41998
That sounds like new behavior for synplicity if true. Synplicity used to
complain if you had generics on black boxes, and those did not get passed to the
netlist Generics were originally intended to control the synthesis, and still
often does so putting them on black boxes hadn't made much sense. Now where
they are used as initialization attributes it makes a lot more sense, but
caution must be taken to avoid including a generic that controls the
elaboration.
Martin Thompson wrote:
> Ray Andraka <ray@andraka.com> writes:
>
> > Even if you write your own you run into the attributes and generics
> > issue. Attributes pass through to the edif netlist but generally have no
> > meaning within VHDL. It is through user attributes that we can set
> > parameters that do not appear in the code. Generics are used to pass
> > parameters into VHDL components, but can't be passed out to the netlist
> > (generics can be thought of as parameter INPUTs to your code). The
> > requirement for both comes up because there are primitives in the FPGA
> > which require some sort of parameterization , be it an initialization
> > value (sucha s for RAMs, LUTs) or to set up a mode in a black box (such as
> > a DCM) that is set outside of the context of the netlist of your
> > design.
>
> Without wishing to ignite anything - the Altera LPMs use the generics
> for simulation, which Synplify passes through the EDIF netlist on the
> blackboxes and then the P&R tool deals with it from there. Any chance
> of Xilinx imitating this?
>
> > The safest way to deal with these, I think, is to use a proxy that your
> > code reads and generates both the attribute and the generic value from.
> > Then to update, change the proxy so that the change automatically
> > propagates to both parameters.
> >
>
> Is there a 'standard' way of doing this or does everyone do it their
> own way?
>
> Any interest in coming up with a standard way of doing it if there
> isn't already one?
>
> Also, it seems I have to put a component declaration in for synth,
> even though I already have the unisim.vcomponents library for
> simulation, so yet more duplication!
>
> Sorry if I sound grumpy, I was in early :-)
>
> Martin
>
> --
> martin.j.thompson@trw.com
> TRW Conekt, Solihull, UK
> http://www.trw.com/conekt
--
--Ray Andraka, P.E.
President, the Andraka Consulting Group, Inc.
401/884-7930 Fax 401/884-7950
email ray@andraka.com
http://www.andraka.com
"They that give up essential liberty to obtain a little
temporary safety deserve neither liberty nor safety."
-Benjamin Franklin, 1759
Article: 41999Just wanted to clarify a few things... I work for a university lab, and this is a research project, not a commercial product. Consequently, two main issues are driving my decision. First, I must use the hardware that is available to me. Which in this case contains a Xilinx part as the PCI interface. Other people are working on other aspects of the project (networking and security), and this is the platform we must all coexist on. Second, I must really justify the cost if I don't use something that is freely available. I am *hoping* that the opencores code can be used as somewhat of a "black box", but with the Wishbone stuff replaced with a different backend. Kevin, I appreciate the honesty, and also the fast reply. After our experience (admittedly a long time ago) with another Open core, I hesitate to use something off of that site. Getting the code to synthesize was hard enough being that it was "someone else's code", but on top of that we couldn't get it to work well enough for our purposes so we wrote our own. I do not like to generalize about a "movement", as it were, from one experience, and it really looks attractive to have the PCI master logic already done--but then again, once burned... j. p.s.: fyi, we may be moving to a VirtexII-based board in the future, and i think i read somewhere that they want $15,000 for the newer PCI core...which is a lot compared against my stipend... :)
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