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I'm posting this for others. It has already been found to fix the problem. 1. the problem is that Cygwin leaves registry entries behind. So, if you install, then uninstall Cygwin. Theninstall to another location there are registry entries poinging to the old location. 2. FIX: regedit search for 'Cygwin' keep pressing F3 until you find an entry that shows the old path. Make it the correct new path. Press F3 to check all other entries (in case it left more). Then all should work.Article: 51226
Has anyone else out there had problems running Synplify under Windows XP? On the machines I've tried it on the 'Run' button is greyed out and neither the synthesize, compile, or synthesis check functions under the run menu will work. There doesn't seem to be anything special about XP installations in the release notes and I'm certain it's not a licensing issue because it works on '98, NT, and 2000 machines. This is a wierd one... MichaelArticle: 51227
Can i connect a bidirectional IO pin on Spartan II device to a 5V CMOS device ? For driving out, i would tristate the output and let an external resistor pull it upto 5V. While receiving, will i have problems making the 5V CMOS device overdrive ? i mean there will be a fight between the internal pullup and external one. -RahArticle: 51228
Just watch out if you intend to use Synplify for DP RAM inferrence because it can't do it. I can't speak for the other tools Igor Orlovich wrote: > Have you tried simply following Xilinx's examples of inferring Dual Port Ram > instead? > sean da wrote: > > >>I used Xilinx Core Generator to build simulation model for dualport >>Ram, and it went through the synthesis phase by XTS, but during >>implementation phase, I got the error message said "dualport_ram is >>unexpected, ....", dualport_ram is my dualport RAM name. What is the >>black box name should I put in my code to pass this implementation >>phase as well as Place/Route phase? Thanks! > >Article: 51229
I found a bug in quartus2 Web V2.2. When tring to place legacy components in schematic editor, such as the 74165b shiftregister, its connectors are off grid. This makes it somewhat hard to connect. Did anyone figure a workaround ? Their support is useless : login(!), place a question, relogin(!) to get a reply, so I didn't ask there. Rene -- Ing.Buero R.Tschaggelar - http://www.ibrtses.com & commercial newsgroups - http://www.talkto.netArticle: 51230
This design is a cascade of decade counters, with the carry in on the least significant counter grounded so it will count... The final carry out does indeed go to a pin. XST does synthesize it.... I am sure the logic is there.. I am used to using Synpify (don't have it now) and am used to looking at the schematic. Clyde rickman wrote: > "Clyde R. Shappee" wrote: > > > > The carry chain starts at a node tied to a logic zero.... > > > > Forget the application.... for now, you are asking too many questions and going > > too deep. > > > > Same question, said a different way, what if I had a decoder whose address was > > internally derived, did not come in from the outside, and I wanted to insure that > > from address in to decode out, the prop delay was less than Y ns. > > > > The VHDL is well constructed. I am just trying to (as I said before, possibly as > > only an exercise) figure out how to constrain the timing for the least delay. > > I understand what you are trying to do, but not why you are doing it > this way. A carry chain does not start at a grounded input for purposes > of timing. That grounded input is *always* grounded and so will not be > used in any timing analysis. In this design the addends are the only > inputs. If they are also grounded or tied high they will also not be > used for timing. In fact, this would explain why you get no logic. In > the same way that a compiler will precalculate math on constants and not > produce code to do that, the synthesizer will perform the logic > operations on fixed inputs and produce a single output corresponding to > the result. > > If your addends are not fixed, then they either have to come from FFs or > from IO pins. The timing tools just do not calculate timing on purely > combinatorial logic that is not connected to an IO. The backend tools > will remove logic that is not sourced and driving either FFs or IO > pins. Unfortunately the tools are only designed to help solve real > problems in real chips, not theoretical analysis of simplified designs. > But this is not hard to work around. > > So what is driving the adders and where do the outputs go in your test > desigin? > > -- > > Rick "rickman" Collins > > rick.collins@XYarius.com > Ignore the reply address. To email me use the above address with the XY > removed. > > Arius - A Signal Processing Solutions Company > Specializing in DSP and FPGA design URL http://www.arius.com > 4 King Ave 301-682-7772 Voice > Frederick, MD 21701-3110 301-682-7666 FAXArticle: 51231
Rah, Spartan II is equivalent to Virtex, so the following applies: http://www.xilinx.com/products/virtex/techtopic/vtt002.pdf It states that you can do this in Virtex (or Spartan II -- same thing) in the table on page 2 which lists what you have proposed ( a pullup to 5V, tristate or pull to '0' when driving, and leave tristate while receiving, and make sure the 5V CMOS driver can drive the added pullup that you put there). Austin Rah wrote: > Can i connect a bidirectional IO pin on Spartan II device to a 5V CMOS > device ? > For driving out, i would tristate the output and let an external > resistor pull it upto 5V. > While receiving, will i have problems making the 5V CMOS device > overdrive ? i mean there will be a fight between the internal pullup > and external one. > > -RahArticle: 51232
"Clyde R. Shappee" wrote: > > This design is a cascade of decade counters, with the carry in on the least significant > counter grounded so it will count... > > The final carry out does indeed go to a pin. > > XST does synthesize it.... I am sure the logic is there.. I am used to using Synpify > (don't have it now) and am used to looking at the schematic. > > Clyde Since it is a counter, it has FFs. The grounded carry in is not part of the timing since the ground never changes. Your long signal paths will be the lsb FF to the msb FF and the lsb FF to the carry output pin. One will be controlled by the clock period constraint and the other by an OFFSET OUT constraint. If the decade counters are being placed separately, the synthesizer is not constructing a single long carry chain which is what you need for the fastest carry propagation. But then I don't know that you can do this will decade counters. Since each decade is only 4 bits, I assume that two LUTs are being used (5 inputs) to generate the carry out of each decade. There may well be some special techniques to optimize this path. Now wasn't that easy? All you had to do was tell us what you were doing rather than what you thought you wanted to do. -- Rick "rickman" Collins rick.collins@XYarius.com Ignore the reply address. To email me use the above address with the XY removed. Arius - A Signal Processing Solutions Company Specializing in DSP and FPGA design URL http://www.arius.com 4 King Ave 301-682-7772 Voice Frederick, MD 21701-3110 301-682-7666 FAXArticle: 51233
I instantiate dual ports fine in Synplify. If you want different clock domains or advances features, the synthesizer may fall short leaving direct instantiation of the Xilinx primitives as a better implementation method. If you need simple operation, the tool works fine. I can't comment about XST either but the limitations of Synplify are reasonable. "name" <nospamforme@someplace.com> wrote in message news:3E1B3B35.4000302@someplace.com... > Just watch out if you intend to use Synplify for DP RAM inferrence > because it can't do it. I can't speak for the other tools > > Igor Orlovich wrote: > > Have you tried simply following Xilinx's examples of inferring Dual Port Ram > > instead? > > sean da wrote: > > > > > >>I used Xilinx Core Generator to build simulation model for dualport > >>Ram, and it went through the synthesis phase by XTS, but during > >>implementation phase, I got the error message said "dualport_ram is > >>unexpected, ....", dualport_ram is my dualport RAM name. What is the > >>black box name should I put in my code to pass this implementation > >>phase as well as Place/Route phase? Thanks! > > > > >Article: 51234
Hello, I wonder if any of you ever used the USB described in the fantastic OPENCORE site by Mr Rudolf Usselmann (a Verilog project). I would like to implement it on a Spartan II system (Trenz Electronics kit) that has a built in Philips PDIUSBP11A chip... but the I do not know how to interface to the transcever pins mentioned in the design (txdp, txdn, txoe, rxd, rxdp, rxdn). Could anyone explain me how to do this? Thank you in advance, FB (fba@free.fr)Article: 51235
Hi, First I need to say that I didn't receive any post from Allan in Outlook Express... I just read them on google since I didn't really understand what you guys were talking about :) > > If you rejected them, please let us know why. Presumably there are > > additional requirements not mentioned in your post. > > Allan I'm sorry about the double-posting. I didn't know that the same people were reading both newsgroups...As for the additional requirements, I'll tell you what is the project so you'll understand my needs: I have a vhdl code that implement a Analog to digital converter using sigma-delta modulation. I'd like to take the one-bit output and filter it in the analog world to analyse its performance. I agree that I could first write modelsim's simulation result to a text file that could be imported into Spice, but this is a pain since I need to do a lot of simulations with large files. I was pretty sure that there existed a tool to automate this process but from your answers there is only vhdl-ams that could do the job. However, I'm not very proficient with vhdl and learning an new language is not really an option. Multisim2001 seems to be doing exactly what I need...but I'd like to here some review of this product before making the switch. It looks more like a learning tool than a designers tool. Thank you very much David "Uncle Noah" <nkavv@skiathos.physics.auth.gr> wrote in message news:b7a879e0.0301070920.3ee57e5@posting.google.com... > allan_herriman.hates.spam@agilent.com (Allan Herriman) wrote in message news:<3e1a7494.97634440@netnews.agilent.com>... > > On Tue, 7 Jan 2003 00:36:13 -0500, "David" <gretzteam@hotmail.com> > > wrote: > > > > >Hi, > > >I have some vhdl code of a sigma-delat modulator that produces a one-bit > > >output... use modelsim to simulate the vhdl code and pspice for analog > > >simulations but I never had to mix those two. I could possibly write the > > >Does anyone know a software that allows to perform vhdl simulation as part > > >of an analog circuit? > > > received two suggestions about how to perform this simulation. > > If you rejected them, please let us know why. Presumably there are > > additional requirements not mentioned in your post. > > Allan > > Those solutions referred could do the work, thus I agree with Alan. I > used to simulate a 8-bit adder providing inputs about the same way. > However, if you are capable in VHDL, and want an integrated solution > you could write the Sigma-Delta is VHDL-AMS (easy to get example in the > net). Then, your problem would be the tool, for free evaluation AMSWizard, > or Dolphin Smash probably. > These simulators interface the analog and digital simulation "islands" > by the appropriate boundary conditions. There is a slight possibility > the Smash tool does exactly what you want for both VHDL/Verilog against > SPICE. > > Uncle "The G.B. Man" NoahArticle: 51236
David wrote: <snip> > I have a vhdl code that implement a Analog to digital converter using > sigma-delta modulation. I'd like to take the one-bit output and filter it in > the analog world to analyse its performance. Seems complicated having VHDL in the loop ? - why not just re-create the Feedback register of the SDM in spice, and then model the Integrator/comparitor as normal. SDMs self-regulate by this feedback, whilst if you feed the ADC bitstream from a file, you will have to exactly match the analog values, or your integrator will saturate . The limit to SDM performance is real world noise sources, harder to simulate - noise on the feedback register Q, and the PSRR of the analog blocks, for example. -jgArticle: 51237
John Williams wrote: > > "Max K." wrote: >> >> hello, >> me & my partner need to test this chip. >> >> is there a systematic way of functional testing of an FPGA chip ? > > I have a paper here called "Testing FPGA Devices using JBITS" which > considers exactly this problem. The authors are all from Xilinx - > Sundararajan, McMillian and Guccione. > > I found it on the web, if you search for the title and authrs names > you should find it. Hi, Found it, it's paper E5 on this page (careful line wrap): http://www.klabs.org/richcontent/MAPLDCon01/ProgramSessions/Session_E.ht ml -- rk, Just an OldEngineer "A good engineer gets stale very fast if he doesn't keep his hands dirty." -- Wernher von Braun, 1964Article: 51238
On Wed, 8 Jan 2003 00:21:03 +0100, "fb" <fba@free.fr> wrote: >Hello, > >I wonder if any of you ever used the USB described in the fantastic OPENCORE >site by Mr Rudolf Usselmann (a Verilog project). > I would like to implement it on a Spartan II system (Trenz Electronics kit) >that has a built in Philips PDIUSBP11A chip... but the I do not know > how to interface to the transcever pins mentioned in the design (txdp, >txdn, txoe, rxd, rxdp, rxdn). Could anyone explain me how to do this? > >Thank you in advance, > > >FB (fba@free.fr) > > The transceiver has vpo, vmo, oe#, rcv, vp, vm pins. These map to the pins you list in the respective order. You may have to invert the oe (output enable) signal because it is not clear whether the IP's signal is active low or not. The transceiver has active low enable. Muzaffer Kal http://www.dspia.com ASIC/FPGA design/verification consulting specializing in DSP algorithm implementationsArticle: 51239
Rene, A fix for this problem is under development. More details about its availability will be posted as soon as the fix is tested and released in the very near future (no later than end of this week). Thanks for bringing this problem to our attention. - Subroto Datta Altera Corporation "Rene Tschaggelar" <tschaggelar@dplanet.ch> wrote in message news:3E1B4021.2090607@dplanet.ch... > I found a bug in quartus2 Web V2.2. > When tring to place legacy components in schematic editor, > such as the 74165b shiftregister, its connectors are off > grid. This makes it somewhat hard to connect. > > Did anyone figure a workaround ? > > Their support is useless : login(!), place a question, > relogin(!) to get a reply, so I didn't ask there. > > Rene > -- > Ing.Buero R.Tschaggelar - http://www.ibrtses.com > & commercial newsgroups - http://www.talkto.net >Article: 51240
Thanks for the quick reply. Amazingly quicker than the mentioned 'MySupport', but then again not - proves my point. Rene Subroto Datta wrote: > Rene, > A fix for this problem is under development. More details about its > availability will be posted as soon as the fix is tested and released in the > very near future (no later than end of this week). Thanks for bringing this > problem to our attention. > > - Subroto Datta > Altera Corporation > > "Rene Tschaggelar" <tschaggelar@dplanet.ch> wrote in message > news:3E1B4021.2090607@dplanet.ch... > >>I found a bug in quartus2 Web V2.2. >>When tring to place legacy components in schematic editor, >>such as the 74165b shiftregister, its connectors are off >>grid. This makes it somewhat hard to connect. >> >>Did anyone figure a workaround ? >> >>Their support is useless : login(!), place a question, >>relogin(!) to get a reply, so I didn't ask there.Article: 51241
I'm really sorry. I meant Digital to Analog conversion. That is why I need vhdl because everything is digital up to the output of the SDM. I don't think I can create the SDM in spice. Thanks David Jim Granville <jim.granville@designtools.co.nz> wrote in message news:<3E1B79EF.29BD@designtools.co.nz>... > David wrote: > <snip> > > I have a vhdl code that implement a Analog to digital converter using > > sigma-delta modulation. I'd like to take the one-bit output and filter it in > > the analog world to analyse its performance. > > Seems complicated having VHDL in the loop ? - why not just > re-create the Feedback register of the SDM in spice, and then > model the Integrator/comparitor as normal. > SDMs self-regulate by this feedback, whilst if you feed > the ADC bitstream from a file, you will have to exactly match > the analog values, or your integrator will saturate . > > The limit to SDM performance is real world noise sources, > harder to simulate - noise on the feedback register Q, and the > PSRR of the analog blocks, for example. > > -jgArticle: 51242
Sometime an abnormal byteblaster cable can lead to it. change one . Note, here "abnormal" means that you can download the .sof into FPGA but can't indentify the epc2 with the same byteblaster cable. Rene Tschaggelar <tschaggelar@dplanet.ch> wrote in message news:<3E195744.7040100@dplanet.ch>... > 123 wrote: > > when I use altera's epc2 chip to download my program,but > > byteblaster cann't identify the epc2! > > You have to do 'multidevice JTAG chain' configuration and then > 'detect configuration' > If have an FPGA and an EPC2, the sequence matters. > > What FPGA is there too ? According to what picture did > you do the configuration ? > > ReneArticle: 51243
> >I wonder if any of you ever used the USB described in the fantastic OPENCORE > >site by Mr Rudolf Usselmann (a Verilog project). > > I would like to implement it on a Spartan II system (Trenz Electronics kit) > >that has a built in Philips PDIUSBP11A chip... but the I do not know > > how to interface to the transcever pins mentioned in the design (txdp, > >txdn, txoe, rxd, rxdp, rxdn). Could anyone explain me how to do this? > > > >Thank you in advance, > > > > > >FB (fba@free.fr) > > > > > > The transceiver has vpo, vmo, oe#, rcv, vp, vm pins. These map to the > pins you list in the respective order. You may have to invert the oe > (output enable) signal because it is not clear whether the IP's signal > is active low or not. The transceiver has active low enable. > > Muzaffer Kal > > http://www.dspia.com > ASIC/FPGA design/verification consulting specializing in DSP algorithm implementations Thank you very much for your help. So actually the inferface with the transceiver is really simple... OE# is active low, so no inversion is required. The only little problem is that on my FPGA board, the RCV signal is not routed to the Spartan II. I can easily regenerate it as is is the difference between both USB signals (i.e. (USB+) and not (USB-)), I just hope that it will not introduce subtle timing problems since there will be a small delay with this extra level of logic compared to the other signals that are fed through direcly. I suppose that an extra level of "empty" (buffer or the like) logic could be added to the other "receive" signals to correct the timings if necessary. There are certainly cleaner methods but I am just a newbie and I am not yet 100% familiar with the synchronous design methods so any advice is welcome... Yours, FB Yours, Frederic BastenaireArticle: 51244
Hi all,
In my design, it needs to transfer 64-bit data between the Spartan II and
the PC via a 8-bit bus.
When the PC reads the hard-coded data(initialized in code segment 1), it
works fine. The PC can
read the hard-coded data. However, when the PC writes data to the board, it
can't read back. The
storage part code is in code segment 2. In segment 2, in the two lines:
data_store(counter2) := tmp_bit;
debug_data <= to_StdlogicVector(tmp_bit);
the 8-bit debug_data is connected to the FPGA's I/O pins so that the data is
viewed using logic
analyzer. It's found that the 8-bit debug_data is the same as the data
written to the board by
the PC. So, it's sure that the tmp_bit do contain the input data, but I
don't know why the
data_sotre can't store it, and each time the PC reads all zero.
I've got 5 warnings of the following type in Xinlinx ISE 4.2i:
WARNING:DesignRules:372 - Netcheck: Gated clock. Clock net N217 is sourced
by a
combinatorial pin. This is not good design practice. Use the CE pin to
control the loading of data into the flip-flop.
Will the problem be related to the warnings ?
Thx for ur kind attention and help.
tk
--------------
VHDL code
--------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity data_tran is
Port ( PC_R_nW_buf : in std_logic; -- PC Read/(Write)'
PC_Rcv_nDS : in std_logic; -- PC Receive/(Data strobe)'
PC_INIT_buf : in std_logic;
data : inout std_logic_vector(7 downto 0);
D2_nDS : inout std_logic := '1';
D2_nRcv : inout std_logic := '0';
debug_data : out std_logic_vector(7 downto 0));
end data_tran;
architecture Behavioral_data_tran of data_tran is
component IBUF
port ( I : in std_logic;
O : out std_logic);
end component;
signal PC_R_nW : std_logic;
signal PC_INIT : std_logic;
signal d_in : std_logic_vector(7 downto 0);
signal d_out : std_logic_vector(7 downto 0);
signal q : std_logic_vector(7 downto 0);
signal pcwe : std_logic; -- PC write enable
signal pcnre : std_logic; -- (PC read enable)'
signal tmp_bit : bit_vector(7 downto 0);
begin
BUF1: IBUF port map(I => PC_R_nW_buf, O => PC_R_nW);
BUF2: IBUF port map(I => PC_INIT_buf, O => PC_INIT);
process(PC_INIT, PC_R_nW, PC_Rcv_nDS)
type data_array is array (0 to 7) of bit_vector(7 downto 0);
variable counter : integer range 0 to 7;
variable counter2 : integer range 0 to 7;
variable data_store : data_array;
begin
if (PC_INIT = '1') then
-- code segment 1 start
-- data_store(0) := "00000001";
-- data_store(1) := "00000010";
-- data_store(2) := "00000100";
-- data_store(3) := "00001000";
-- data_store(4) := "00010000";
-- data_store(5) := "00100000";
-- data_store(6) := "01000000";
-- data_store(7) := "10000000";
-- code segment 1 end
if (PC_R_nW = '1') then
counter := 0;
D2_nDS <= '1';
pcwe <= '0';
pcnre <= '0';
elsif (PC_R_nW = '0') then
counter2 := 0;
D2_nRcv <= '1';
pcwe <= '1';
pcnre <= '1';
end if;
end if;
if (PC_R_nW = '1') then
if (PC_Rcv_nDS = '1') then
D2_nDS <= '1';
end if;
elsif (PC_R_nW = '0') then
if (PC_Rcv_nDS = '1') then
D2_nRcv <= '1';
end if;
end if;
if (PC_R_nW = '1' and PC_INIT = '0'
and PC_Rcv_nDS = '0' and D2_nDS = '1') then
d_out <= to_StdlogicVector(data_store(counter));
if (counter = 7) then
counter := 0;
else
counter := counter + 1;
end if;
D2_nDS <= '0';
elsif (PC_R_nW = '0' and PC_INIT = '0'
and PC_Rcv_nDS = '0' and D2_nRcv = '1') then
-- code segment 2 start
data_store(counter2) := tmp_bit;
debug_data <= to_StdlogicVector(tmp_bit);
-- code segment 2 end
if (counter2 = 7) then
counter2 := 0;
else
counter2 := counter2 + 1;
end if;
D2_nRcv <= '0';
end if;
end process;
d_in <= data when pcwe = '1' else d_out;
q <= d_in;
data <= q when pcnre = '0' else "ZZZZZZZZ";
tmp_bit <= to_bitvector(d_in);
end Behavioral_data_tran;
Article: 51245
> Will the problem be related to the warnings ?
>
> Thx for ur kind attention and help.
>
> tk
I haven't checked through the logic of your design but you've
written it in a combinatorial way that isn't ideally suited to
FPGAs.
FPGAs have fast clock nets to allow every flip flop to be
clocked off one clock (in the simplest case). If only this clock
net is used to clock each flip flop then all the Place
and Route tools have to worry about is the combinatorial logic delay
between flip flops. The clock frequency is entered as a constraint
so the tools know the period they are dealing with.
The 'normal' code structure for ensuring that only the clock net
is used to clock each flip flop is
process(rst,clk)
begin
if(rst = '1') then -- Asynch reset
signals <= '0'; -- or whatever reset value you need
elsif(rising_edge(clk)) then -- All signals are assigned 'within' this and
updated
-- on the rising edge of the clock if enabled
as below.
if(X = '1') then -- X and Y are now used as clock enables
signals <= assigned;
elsif(Y = '1') then
signals <= assigned_to_something_else;
else
signals <= default_value;
end if;
end if;
end process;
If you go to the Downloads page of the web site below there's an example
of an interface written to drive a USB interface module designed for
use with the BurchED FPGA evaluation board. This is fairly well commented
and is similar to what you seem to be trying. It might be worth looking
at for more help.
Hope this helps.
Nial.
------------------------------------------------
Nial Stewart Developments Ltd
FPGA and High Speed Digital Design
www.nialstewart.co.uk
Article: 51246In Xilinx ISE 5.1i, 1)How to get the delay for internal clock to internal signal pin? 2)How to give timing constraint for internal clock to internal signal pin? 3)How to give timing constraint for internal signal pin to another internal signal pin? One basic question is xilinx tool changes net names during implementation. How to find out my signal?Article: 51247
In my case strobe is much longer than CLK (I latch values from computer's LPT into CPLD). Seems that it is the simples case you describe. Thank you all.Article: 51248
thx for ur help : ) "Nial Stewart" <nial@spamno.nialstewart.co.uk> wrote in message news:3e1c1739$0$29919$fa0fcedb@lovejoy.zen.co.uk... > > Will the problem be related to the warnings ? > > > > Thx for ur kind attention and help. > > > > tk > > I haven't checked through the logic of your design but you've > written it in a combinatorial way that isn't ideally suited to > FPGAs. > > FPGAs have fast clock nets to allow every flip flop to be > clocked off one clock (in the simplest case). If only this clock > net is used to clock each flip flop then all the Place > and Route tools have to worry about is the combinatorial logic delay > between flip flops. The clock frequency is entered as a constraint > so the tools know the period they are dealing with. > > The 'normal' code structure for ensuring that only the clock net > is used to clock each flip flop is > > process(rst,clk) > begin > if(rst = '1') then -- Asynch reset > > signals <= '0'; -- or whatever reset value you need > > elsif(rising_edge(clk)) then -- All signals are assigned 'within' this and > updated > -- on the rising edge of the clock if enabled > as below. > > if(X = '1') then -- X and Y are now used as clock enables > signals <= assigned; > > elsif(Y = '1') then > signals <= assigned_to_something_else; > > else > signals <= default_value; > end if; > > end if; > > end process; > > > If you go to the Downloads page of the web site below there's an example > of an interface written to drive a USB interface module designed for > use with the BurchED FPGA evaluation board. This is fairly well commented > and is similar to what you seem to be trying. It might be worth looking > at for more help. > > Hope this helps. > > > Nial. > ------------------------------------------------ > Nial Stewart Developments Ltd > FPGA and High Speed Digital Design > www.nialstewart.co.uk > > > > > >Article: 51249
In article <d977c973.0301080042.3070fd27@posting.google.com>, Frederic Bastenaire <fba@free.fr> wrote: >> >I wonder if any of you ever used the USB described in the fantastic OPENCORE >> >site by Mr Rudolf Usselmann (a Verilog project). >> > I would like to implement it on a Spartan II system (Trenz Electronics kit) >> >that has a built in Philips PDIUSBP11A chip... but the I do not know >> > how to interface to the transcever pins mentioned in the design (txdp, >> >txdn, txoe, rxd, rxdp, rxdn). Could anyone explain me how to do this? >> > >> >Thank you in advance, >> > >> > >> >FB (fba@free.fr) >> > >> > >> >> The transceiver has vpo, vmo, oe#, rcv, vp, vm pins. These map to the >> pins you list in the respective order. You may have to invert the oe >> (output enable) signal because it is not clear whether the IP's signal >> is active low or not. The transceiver has active low enable. >> >> Muzaffer Kal >> >> http://www.dspia.com >> ASIC/FPGA design/verification consulting specializing in DSP algorithm >implementations > >Thank you very much for your help. > >So actually the inferface with the transceiver is really simple... >OE# is active low, so no inversion is required. The only >little problem is that on my FPGA board, the RCV signal is not routed >to the >Spartan II. You mentioned above that you have a Trenz board. The specs for their TE-XC2SE board show rcv connected to pin B9, vm on C9, and vp on D9. I think your problem will be that the Trenz board has the transceiver mode pin unconnected (mode 1, for differential input on VPO/VMO) while Usselmann's design produces single-ended output requiring mode 0. You should be able to fix this by adding a kludge wire to ground from pin 1 of the PDIUSBP11A chip. -- Caleb Hess hess@cs.indiana.edu
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