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"Clyde R. Shappee" wrote: > > Hello all, > > I have some combinatorial logic that I want to constrain in a Xilinx > device to minimize the propagation delay end to end. > > I tried this: > > NET "S(1)" TNM_NET = "group1"; > NET "S(6)" TNM_NET = "group2"; > > TIMESPEC "TScarry" = FROM "group1" TO "group2" 6 ns; > > and XST complains it cannot find the nets S(1) and S(6). Is this the > proper way to do it? > > I went into the floor planner and poked around and figured out that my > net names are changed by the tool, as they are not in the design at > all. I tried the Keep constraint, to try and coerce the tool into > keeping my name, and it still complains. > > So, the bottom line questions: > > Is this the correct approach? > > How do I determine correctly what names my nets have been given? You did not say how you are entering your design. If you are using an HDL you might try looking at the generated output (EDIF or XNF) to find your nets. They may have been optimized away or otherwise renamed. Then check to see if the logic was optimized away by the mapper. If your inputs and outputs are not from an IO pin, they will be optimized away since they are not driven. I think there is a switch to prevent this, but it is not a useful design without IO. If you are using purely combinatorial logic between IO pins, you may want to use a spec for pin to pin timings. I don't remember the format, but it does not involve the internal nets, just the IO pins. There is not much use to timing internal paths that are not clock related, unless this is an exercise. -- Rick "rickman" Collins rick.collins@XYarius.com Ignore the reply address. To email me use the above address with the XY removed. Arius - A Signal Processing Solutions Company Specializing in DSP and FPGA design URL http://www.arius.com 4 King Ave 301-682-7772 Voice Frederick, MD 21701-3110 301-682-7666 FAXArticle: 51201
Thomas Rudloff <thomas_rudloff@gmx.net> wrote in message news:<3E16530E.5D688342@gmx.net>... > Use impedance matching at the FPGA and put serial termination > resistors close to the RAMs. Note that the common PC133 SDRAM DIMMs include 10 ohm series termination resistors on the DQs and the clocks. See page 5 of http://download.micron.com/pdf/datasheets/modules/sd8_16c32_64x64ag_c.pdf --MikeArticle: 51202
> I heard that this was because of the recession. I was told by someone > from a recruitment agency that deals with both contractors and permanent > staff that this is a really bad time to be a contractor. In the boom of the 90s a lot of recruitment agencies were set up, recently several have gone bust. Contractors' companies are usually at the bottom of the heap when it comes to settling bills. > One explanation > is that companies will only lay-off permanent staff when they have to > because of the cost and potential legal repercussions. Contract staff > are easier to get rid of because there is no promise to maintain > employment in the first place. This is the sort of terminology that causes confusion over IR35 as mentioned above. There should be no 'employment' of contractors. There is just a contract with their company to supply someone (usually a named person), but agencies mostly just think of contractors as temps. > Therefore, when a company is short of > cash, the first jobs to go are the contract jobs. The upside is that when things start to recover and companies start spending a bit more on development but aren't positive enough to recruit permanent staff contracting can quickly pick up. Unfortunately there's no sign of this in the UK yet. The UK IT market's also been depressed by the 'Fast Track Visa' scheme introduced by New Labour, and the trend to sub-contract work to India/China. Nial Stewart. ------------------------------------------------ Nial Stewart Developments Ltd FPGA and High Speed Digital Design www.nialstewart.co.ukArticle: 51203
valentin tihomirov <valentin@abelectron.com> wrote in message news:3e198cc4$1_2@news.estpak.ee... > Hello, > I have a synchronous system, but there is a parameter that comes (n bits > long) that comes from external world. This value is stored int input buffer > (register). The master device that provides this value also provides a > strobe signal for the register. I don't know whether this STOBE signal > should be LATCH (active high) or FF (load a value on L2H trasition). I have > another question. Is there any problem when data is being stored into > register and read simultaneously? This should lead to inconsistent state > when some of the bits read from the register are updated while others still > arn't. Which is a standard way to synchronise data load? Asynchronous > handshking? > > _______ ____________________ > | | | | > VALUE ==+ REG | | System with clock| > | +--->| | > STROBE --+ | | | > |_______| | | > | | > |____________________| If your system clock is fast enough a clean way of doing this is to use it to detect the strobe going high and use this to register the value into your 'system clock' domain. Nial ------------------------------------------------ Nial Stewart Developments Ltd FPGA and High Speed Digital Design www.nialstewart.co.ukArticle: 51204
My design entry is VHDL. Yes, this is sort of an exercise. I am between designs and am exploring some ideas I have not had time for before, and trying to learn more on the tool set, like how to use constraints better, looking at floor planning, etc. The chain of combinatorial logic starts from an internal node and does end up on a pin, in this example, but might not in real life. It is a carry chain in a string of counters. Re-use of this design may not send the last carry out to a pin. What I noticed in the floor plan editor, is the placed logic was way spread out. I did locate what I think are the proper nodes (but I am guessing) and put them in the constraints, and now the design is placed much tighter from a real estate standpoint. I have neither an .xnf or .edf file in my design directory. Any clues as to where to look next? Thanks for the reply. Clyde rickman wrote: > "Clyde R. Shappee" wrote: > > > > Hello all, > > > > I have some combinatorial logic that I want to constrain in a Xilinx > > device to minimize the propagation delay end to end. > > > > I tried this: > > > > NET "S(1)" TNM_NET = "group1"; > > NET "S(6)" TNM_NET = "group2"; > > > > TIMESPEC "TScarry" = FROM "group1" TO "group2" 6 ns; > > > > and XST complains it cannot find the nets S(1) and S(6). Is this the > > proper way to do it? > > > > I went into the floor planner and poked around and figured out that my > > net names are changed by the tool, as they are not in the design at > > all. I tried the Keep constraint, to try and coerce the tool into > > keeping my name, and it still complains. > > > > So, the bottom line questions: > > > > Is this the correct approach? > > > > How do I determine correctly what names my nets have been given? > > You did not say how you are entering your design. If you are using an > HDL you might try looking at the generated output (EDIF or XNF) to find > your nets. They may have been optimized away or otherwise renamed. > Then check to see if the logic was optimized away by the mapper. If > your inputs and outputs are not from an IO pin, they will be optimized > away since they are not driven. I think there is a switch to prevent > this, but it is not a useful design without IO. > > If you are using purely combinatorial logic between IO pins, you may > want to use a spec for pin to pin timings. I don't remember the format, > but it does not involve the internal nets, just the IO pins. There is > not much use to timing internal paths that are not clock related, unless > this is an exercise. > > -- > > Rick "rickman" Collins > > rick.collins@XYarius.com > Ignore the reply address. To email me use the above address with the XY > removed. > > Arius - A Signal Processing Solutions Company > Specializing in DSP and FPGA design URL http://www.arius.com > 4 King Ave 301-682-7772 Voice > Frederick, MD 21701-3110 301-682-7666 FAXArticle: 51205
Valentin, I would recommend reading the "Moving Data across Asynchronous Clock Boundaries" article by Peter Alfke: http://www.eedesign.com/editorial/2000/design0003.html Regards, -- Georgi "valentin tihomirov" <valentin@abelectron.com> wrote in message news:<3e198cc4$1_2@news.estpak.ee>... > Hello, > I have a synchronous system, but there is a parameter that comes (n bits > long) that comes from external world. This value is stored int input buffer > (register). The master device that provides this value also provides a > strobe signal for the register. I don't know whether this STOBE signal > should be LATCH (active high) or FF (load a value on L2H trasition). I have > another question. Is there any problem when data is being stored into > register and read simultaneously? This should lead to inconsistent state > when some of the bits read from the register are updated while others still > arn't. Which is a standard way to synchronise data load? Asynchronous > handshking? > > > > > _______ ____________________ > | | | | > VALUE ==+ REG | | System with clock| > | +--->| | > STROBE --+ | | | > |_______| | | > | | > |____________________|Article: 51206
Clyde, For async logic, you should assign them with TPSYNC "Clyde R. Shappee" wrote: > Hello all, > > I have some combinatorial logic that I want to constrain in a Xilinx > device to minimize the propagation delay end to end. > > I tried this: > > NET "S(1)" TNM_NET = "group1"; > NET "S(6)" TNM_NET = "group2"; > > TIMESPEC "TScarry" = FROM "group1" TO "group2" 6 ns; > > and XST complains it cannot find the nets S(1) and S(6). Is this the > proper way to do it? > > I went into the floor planner and poked around and figured out that my > net names are changed by the tool, as they are not in the design at > all. I tried the Keep constraint, to try and coerce the tool into > keeping my name, and it still complains. > > So, the bottom line questions: > > Is this the correct approach? > > How do I determine correctly what names my nets have been given? > > ClydeArticle: 51207
Clyde, For async logic, you should assign them with TPSYNC in addition to what you have already. http://toolbox.xilinx.com/docsan/xilinx5/data/docs/cgd/cgd0215_29.html If you're using XST as your synthesis tool, you'll have NGC file as your netlist output. You can use 5.1i's RTL schematic viewer to verify what name has been given by the synthesis tool. XST, by default, names bus members with <>. You get EDN/EDF as your netlist output with Synplify/Spectrum. If net is being optimized out, then KEEP will do the trick. You'll have to place KEEP on the input and output of the optimized comp in order for it to work. If it's a dangling net, than you'll need to use the SAVE constraint. http://toolbox.xilinx.com/docsan/xilinx5/data/docs/cgd/cgd0195_28.html Regards, Wei "Clyde R. Shappee" wrote: > Hello all, > > I have some combinatorial logic that I want to constrain in a Xilinx > device to minimize the propagation delay end to end. > > I tried this: > > NET "S(1)" TNM_NET = "group1"; > NET "S(6)" TNM_NET = "group2"; > > TIMESPEC "TScarry" = FROM "group1" TO "group2" 6 ns; > > and XST complains it cannot find the nets S(1) and S(6). Is this the > proper way to do it? > > I went into the floor planner and poked around and figured out that my > net names are changed by the tool, as they are not in the design at > all. I tried the Keep constraint, to try and coerce the tool into > keeping my name, and it still complains. > > So, the bottom line questions: > > Is this the correct approach? > > How do I determine correctly what names my nets have been given? > > ClydeArticle: 51208
In article <3e198cc4$1_2@news.estpak.ee>, valentin@abelectron.com says... > Hello, > I have a synchronous system, but there is a parameter that comes (n bits > long) that comes from external world. This value is stored int input buffer > (register). The master device that provides this value also provides a > strobe signal for the register. I don't know whether this STOBE signal > should be LATCH (active high) or FF (load a value on L2H trasition). I have > another question. Is there any problem when data is being stored into > register and read simultaneously? This should lead to inconsistent state > when some of the bits read from the register are updated while others still > arn't. Which is a standard way to synchronise data load? Asynchronous > handshking? Without seeing the exact specifications of your system, I can't say for sure if the strobe should be used as a clock or a latch but that should be apparent from the timings. To determine when it is safe to use the data in the clock domain of your design, the most common way to do that would be to double latch the strobe signal into that clock domain. When the second latch is seen active in the new clock domain, it is safe to read the register data in that clock domain. Single latching is also an option if you allow enough settling time but that requires you do some caluculations based on some characteristics of your FPGA's flip flops and acceptable mean time to failure. -- Rich Iachetta iachetta@us.ibm.com I do not speak for IBM.Article: 51209
Can you tell me what version of Cygwin you are using? In earlier versions of Nios/SOPC Builder only certain versions of Cygwin were supported. See the readme for more on the exact versions. If you have a later version this should be fixed. It has to do with the /cygwin pathing. Please respond and we'll figure it out. Kerri "Matjaz Finc" <matjaz.finc@fe.uni-lj.si> wrote in message news:<avbi8a$t64$1@planja.arnes.si>... > Under which OS? > > Mine works fine under WinXP. > > Maybe try mk_custom_sdk in bash shell. > > Matjaz > > "Peter Wtorek" <umwtorek@cc.umanitoba.ca> wrote in message > news:au8mu4$hhm$2@canopus.cc.umanitoba.ca... > > Hello, > > > > Having a small problem when generating a SOPC core using the SOPC > > Builder application. > > > > After I press "Generate", the system begins building the binary files. > > It runs into a problem when running the "nios-convert" application. > > The following errors are generated: > > > > # 2002.12.23 21:13:53 (*) cd d:/quartus/testproj ; nios-convert > > --outfile=nios_dev_board_flash_0_contents.srec --address_low=16384 > > --address_high=32768 > > Can't locate strict.pm in @INC (@INC contains: > > > /cygdrive/d/altera/excalibur/sopc_builder_2_5/bin/perl_lib:/cygdrive/d/alter > a/excalibur/sopc_builder_2_5/bin/europa:/cygdrive/d/altera/excalibur/sopc_bu > ilder_2_5/bin: > > .) at - line 3. > > BEGIN failed--compilation aborted at - line 3. > > # mk_custom_sdk: WARNING 512 cd d:/quartus/testproj ; nios-convert > > --outfile=nios_dev_board_flash_0_contents.srec --address_low=16384 > > --address_high=32768 > > ERROR: Could not build Peripheral Contents for nios_0 > > > > Error in processing. System NOT successfully generated. > > > > As you can see, the perl interpreter cannot find strict.pm, although it > > is indeed located within: > > > > /cygdrive/d/altera/excalibur/sopc_builder_2_5/bin/perl_lib > > > > So the @INC array is correct, but it cannot find the proper perl > > module. Any help here? Thanks. > >Article: 51210
When I close LeonardoSpectrum LS2002d_22,
Have a error message follow , Can help me ?
Thank you
_________________________________________________________
Microsoft Visual C++ Debug Library
Debug Assertion Failed!
Program : c:\MGC\LeoSpec\LS2002d_22\bin\win32\leonardo.exe
File : dbgheap.c
Line : 1011
Expression : _CrtIsValidHeapPointer(pUerData)
For information on how your program can cause an assertion
failure, see the Visual C++ documentation on asserts.
( Press Retry to debug the application)
______________________________________________________
Article: 51211"Clyde R. Shappee" wrote: > > My design entry is VHDL. > > Yes, this is sort of an exercise. I am between designs and am exploring > some ideas I have not had time for before, and trying to learn more on the > tool set, like how to use constraints better, looking at floor planning, > etc. > > The chain of combinatorial logic starts from an internal node and does end > up on a pin, in this example, but might not in real life. It is a carry > chain in a string of counters. Re-use of this design may not send the > last carry out to a pin. Ok, but if it starts at a node, what is the node? It is not typical to try to constrain timing from a combinatorial element to another. You might be able to do this, but it would be simpler if you just used FFs as your starting points and FFs as your ending point. Then you can use the clock period as your constraint and the tools will tell you the longest path between FFs. Right now if your starting point is not a FF it is likely being optimized away since combinatorial logic with no input is of no use. > What I noticed in the floor plan editor, is the placed logic was way spread > out. I did locate what I think are the proper nodes (but I am guessing) > and put them in the constraints, and now the design is placed much tighter > from a real estate standpoint. If you are designing something with a carry chain, it should be mapped in a column. But if it is not using the carry chain, you may end up with spread out logic. What is the logical construct you are trying to design? Adders and counters should all be synthesized correctly. Perhaps your VHDL is not well constructed. I belive some synthesis tools have trouble doing this correctly if you don't use just the right syntax. > I have neither an .xnf or .edf file in my design directory. Any clues as to > where to look next? Check the documentation for the synthesis tool to see what it produces as an output. -- Rick "rickman" Collins rick.collins@XYarius.com Ignore the reply address. To email me use the above address with the XY removed. Arius - A Signal Processing Solutions Company Specializing in DSP and FPGA design URL http://www.arius.com 4 King Ave 301-682-7772 Voice Frederick, MD 21701-3110 301-682-7666 FAXArticle: 51212
How does this information change since I am using 4.2 sp 3? Thanks for the input. CRS Chen Wei Tseng wrote: > Clyde, > > For async logic, you should assign them with TPSYNC in addition to what > you have already. > > http://toolbox.xilinx.com/docsan/xilinx5/data/docs/cgd/cgd0215_29.html > > If you're using XST as your synthesis tool, you'll have NGC file as your > netlist output. You can use 5.1i's RTL schematic viewer to verify what > name has been given by the synthesis tool. XST, by default, names bus > members with <>. > > You get EDN/EDF as your netlist output with Synplify/Spectrum. > > If net is being optimized out, then KEEP will do the trick. You'll have to > place KEEP on the input and output of the optimized comp in order for it > to work. If it's a dangling net, than you'll need to use the SAVE > constraint. > > http://toolbox.xilinx.com/docsan/xilinx5/data/docs/cgd/cgd0195_28.html > > Regards, Wei > > "Clyde R. Shappee" wrote: > > > Hello all, > > > > I have some combinatorial logic that I want to constrain in a Xilinx > > device to minimize the propagation delay end to end. > > > > I tried this: > > > > NET "S(1)" TNM_NET = "group1"; > > NET "S(6)" TNM_NET = "group2"; > > > > TIMESPEC "TScarry" = FROM "group1" TO "group2" 6 ns; > > > > and XST complains it cannot find the nets S(1) and S(6). Is this the > > proper way to do it? > > > > I went into the floor planner and poked around and figured out that my > > net names are changed by the tool, as they are not in the design at > > all. I tried the Keep constraint, to try and coerce the tool into > > keeping my name, and it still complains. > > > > So, the bottom line questions: > > > > Is this the correct approach? > > > > How do I determine correctly what names my nets have been given? > > > > ClydeArticle: 51213
The carry chain starts at a node tied to a logic zero.... Forget the application.... for now, you are asking too many questions and going too deep. Same question, said a different way, what if I had a decoder whose address was internally derived, did not come in from the outside, and I wanted to insure that from address in to decode out, the prop delay was less than Y ns. The VHDL is well constructed. I am just trying to (as I said before, possibly as only an exercise) figure out how to constrain the timing for the least delay. CRS rickman wrote: > "Clyde R. Shappee" wrote: > > > > My design entry is VHDL. > > > > Yes, this is sort of an exercise. I am between designs and am exploring > > some ideas I have not had time for before, and trying to learn more on the > > tool set, like how to use constraints better, looking at floor planning, > > etc. > > > > The chain of combinatorial logic starts from an internal node and does end > > up on a pin, in this example, but might not in real life. It is a carry > > chain in a string of counters. Re-use of this design may not send the > > last carry out to a pin. > > Ok, but if it starts at a node, what is the node? It is not typical to > try to constrain timing from a combinatorial element to another. You > might be able to do this, but it would be simpler if you just used FFs > as your starting points and FFs as your ending point. Then you can use > the clock period as your constraint and the tools will tell you the > longest path between FFs. > > Right now if your starting point is not a FF it is likely being > optimized away since combinatorial logic with no input is of no use. > > > What I noticed in the floor plan editor, is the placed logic was way spread > > out. I did locate what I think are the proper nodes (but I am guessing) > > and put them in the constraints, and now the design is placed much tighter > > from a real estate standpoint. > > If you are designing something with a carry chain, it should be mapped > in a column. But if it is not using the carry chain, you may end up > with spread out logic. What is the logical construct you are trying to > design? Adders and counters should all be synthesized correctly. > Perhaps your VHDL is not well constructed. I belive some synthesis > tools have trouble doing this correctly if you don't use just the right > syntax. > > > I have neither an .xnf or .edf file in my design directory. Any clues as to > > where to look next? > > Check the documentation for the synthesis tool to see what it produces > as an output. > > -- > > Rick "rickman" Collins > > rick.collins@XYarius.com > Ignore the reply address. To email me use the above address with the XY > removed. > > Arius - A Signal Processing Solutions Company > Specializing in DSP and FPGA design URL http://www.arius.com > 4 King Ave 301-682-7772 Voice > Frederick, MD 21701-3110 301-682-7666 FAXArticle: 51214
Hi, I have some vhdl code of a sigma-delat modulator that produces a one-bit output. I'd like to be able to simulate this one-bit output when it is fed into an analog circuit with transistors, resistors etc...a spice simulation. I usually use modelsim to simulate the vhdl code and pspice for analog simulations but I never had to mix those two. I could possibly write the modelsim waveform to a text file and then edit the file to meet pspice requirement but this is a pain. Does anyone know a software that allows to perform vhdl simulation as part of an analog circuit? I saw that multisim2001 seems to do it, but honestly, if I remember, the electronic workbench software 10 years ago didn't worth much...is it still the case? Should I ask somewhere else? Thanks a lot DavidArticle: 51215
On Tue, 7 Jan 2003 00:36:13 -0500, "David" <gretzteam@hotmail.com> wrote: >Hi, >I have some vhdl code of a sigma-delat modulator that produces a one-bit >output. I'd like to be able to simulate this one-bit output when it is fed >into an analog circuit with transistors, resistors etc...a spice simulation. >I usually use modelsim to simulate the vhdl code and pspice for analog >simulations but I never had to mix those two. I could possibly write the >modelsim waveform to a text file and then edit the file to meet pspice >requirement but this is a pain. >Does anyone know a software that allows to perform vhdl simulation as part >of an analog circuit? >I saw that multisim2001 seems to do it, but honestly, if I remember, the >electronic workbench software 10 years ago didn't worth much...is it still >the case? > >Should I ask somewhere else? You recently asked this same question in sci.electronics.design and received two suggestions about how to perform this simulation. http://groups.google.com/groups?threadm=YtqR9.15146%24KR6.244754%40weber.videotron.net If you rejected them, please let us know why. Presumably there are additional requirements not mentioned in your post. Regards, AllanArticle: 51216
Hello!
> In the ChipScope root, I found a log, full of notes about "Java
exceptions"
> related to a drop-down.
> Seems a problem of Java runtime.
There is a quite the same problem with corgen:
http://support.xilinx.com/xlnx/xil_ans_display.jsp?iLanguageID=1&iCountryID=
1&getPagePath=11386
this is because in windows versions after xp1 and inc xp1 {across all
platforms} Microsoft's license for java VM from sun was suspended and
revoked
so it was pulled out the front end
stupid really
you simply uninstall all previous versions of java vm or if you haven't put
sun systems version in yet
then install the latest sdk and jre je etc
there are many variants
but sun systems one works fine for me now
with all gui simulators etc running fine
Good luck, Sasa
Article: 51217The Stratix Data Sheet¹ shows in figure 64 (page 114) Stratix IOE in DDR Input I/O Configuration. Between the Pad (On-Chip Termination) and the input register there is a box titled "Input Pin to Input Register Delay". I found the following rather terse description in the data sheet "The Quartus II Compiler can program these delay to automatically minimize setup time while providing a zero hold time." There seem to be no options to set these delays while using the Quartus II MegaWizard to create a DDR input register. There appears to be a compile time "De/Increase Input Delay to Input Register logic option" in Quartus II. However, there is no input to the generated DDR input register to set the input delay. Is there a way to program these delays during run time (i.e. after the device has been configured)? Is any detailed documentation available? TIA Petter ¹) Digital Library CD October 2002 - DS-STXFAMILY-2.1 -- ________________________________________________________________________ Petter Gustad 8'h2B | ~8'h2B http://www.gustad.com/petterArticle: 51218
unless the decoder inputs and outputs connect to the outside, this is an academic
question. The signals eventually either have to go to a pin or to a flip-flop. If
internal only, then it is a flip-flop, in which case period or from:to constraints
between the ff's are sufficient. If one end of the signal goes to the outside, then
use an offset constraint. If you are trying to constrain a subset of the path, you'll
need to jump through a lot of hoops to make sure the signal name doesn't dissappear on
you. I think rickman was trying to understand why you would want to do this.
"Clyde R. Shappee" wrote:
> The carry chain starts at a node tied to a logic zero....
>
> Forget the application.... for now, you are asking too many questions and going
> too deep.
>
> Same question, said a different way, what if I had a decoder whose address was
> internally derived, did not come in from the outside, and I wanted to insure that
> from address in to decode out, the prop delay was less than Y ns.
>
> The VHDL is well constructed. I am just trying to (as I said before, possibly as
> only an exercise) figure out how to constrain the timing for the least delay.
>
> CRS
>
> rickman wrote:
>
> > "Clyde R. Shappee" wrote:
> > >
> > > My design entry is VHDL.
> > >
> > > Yes, this is sort of an exercise. I am between designs and am exploring
> > > some ideas I have not had time for before, and trying to learn more on the
> > > tool set, like how to use constraints better, looking at floor planning,
> > > etc.
> > >
> > > The chain of combinatorial logic starts from an internal node and does end
> > > up on a pin, in this example, but might not in real life. It is a carry
> > > chain in a string of counters. Re-use of this design may not send the
> > > last carry out to a pin.
> >
> > Ok, but if it starts at a node, what is the node? It is not typical to
> > try to constrain timing from a combinatorial element to another. You
> > might be able to do this, but it would be simpler if you just used FFs
> > as your starting points and FFs as your ending point. Then you can use
> > the clock period as your constraint and the tools will tell you the
> > longest path between FFs.
> >
> > Right now if your starting point is not a FF it is likely being
> > optimized away since combinatorial logic with no input is of no use.
> >
> > > What I noticed in the floor plan editor, is the placed logic was way spread
> > > out. I did locate what I think are the proper nodes (but I am guessing)
> > > and put them in the constraints, and now the design is placed much tighter
> > > from a real estate standpoint.
> >
> > If you are designing something with a carry chain, it should be mapped
> > in a column. But if it is not using the carry chain, you may end up
> > with spread out logic. What is the logical construct you are trying to
> > design? Adders and counters should all be synthesized correctly.
> > Perhaps your VHDL is not well constructed. I belive some synthesis
> > tools have trouble doing this correctly if you don't use just the right
> > syntax.
> >
> > > I have neither an .xnf or .edf file in my design directory. Any clues as to
> > > where to look next?
> >
> > Check the documentation for the synthesis tool to see what it produces
> > as an output.
> >
> > --
> >
> > Rick "rickman" Collins
> >
> > rick.collins@XYarius.com
> > Ignore the reply address. To email me use the above address with the XY
> > removed.
> >
> > Arius - A Signal Processing Solutions Company
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Article: 51219Just to add that the (current) 5.1i version of XPower reads VCD simulation data from the following simulators (in addition to Modelsim) : Cadence's Verilog XL Cadence's NC-Verilog Cadence's NC-VHDL Cadence's NC-SIM (Obviously the three service packs since 5.1i also support the above simulators.) Brendan Alan Raphael wrote: > Have you tried the Analyze Power (Xpower) tool built right into ISE 4.2i and 5.2i > See http://toolbox.xilinx.com/docsan/xilinx5/help/xpower/xpower.htm for details. > > XPower is a post-route (FPGA) and post-fit (CPLD) analysis tool that enables you to > interactively and automatically analyze power consumption for Xilinx FPGAs and > CPLDs. XPower includes both GUI (xpower) and batch (xpwr) applications. > > XPower is the first power-analysis software available for programmable logic > design. Earlier in the design flow than ever, you can analyze total device power, > power per-net, routed, partially routed or unrouted designs, all driven from a > comprehensive graphic interface or command-line driven batch-mode. XPower also > reads VCD simulation data from the ModelSim family of HDL simulators to set > estimation stimulus, reducing setup time, as well as from the additional simulators > listed in Simulator Support. > > Xefteris Stefanos wrote: > > Hello, > > My problem in a few words is this: I have done toggling activity > > estimation and now I want to use this to apply power estimation on my > > design.But,I havent yet found the way to incorporate the toggling > > estimation in my power estimation.Article: 51220
As for TPSYNC, SAVE, and KEEP constraints, they're the same in 4.2i Regards, Wei "Clyde R. Shappee" wrote: > How does this information change since I am using 4.2 sp 3? > > Thanks for the input. > > CRS > > Chen Wei Tseng wrote: > > > Clyde, > > > > For async logic, you should assign them with TPSYNC in addition to what > > you have already. > > > > http://toolbox.xilinx.com/docsan/xilinx5/data/docs/cgd/cgd0215_29.html > > > > If you're using XST as your synthesis tool, you'll have NGC file as your > > netlist output. You can use 5.1i's RTL schematic viewer to verify what > > name has been given by the synthesis tool. XST, by default, names bus > > members with <>. > > > > You get EDN/EDF as your netlist output with Synplify/Spectrum. > > > > If net is being optimized out, then KEEP will do the trick. You'll have to > > place KEEP on the input and output of the optimized comp in order for it > > to work. If it's a dangling net, than you'll need to use the SAVE > > constraint. > > > > http://toolbox.xilinx.com/docsan/xilinx5/data/docs/cgd/cgd0195_28.html > > > > Regards, Wei > > > > "Clyde R. Shappee" wrote: > > > > > Hello all, > > > > > > I have some combinatorial logic that I want to constrain in a Xilinx > > > device to minimize the propagation delay end to end. > > > > > > I tried this: > > > > > > NET "S(1)" TNM_NET = "group1"; > > > NET "S(6)" TNM_NET = "group2"; > > > > > > TIMESPEC "TScarry" = FROM "group1" TO "group2" 6 ns; > > > > > > and XST complains it cannot find the nets S(1) and S(6). Is this the > > > proper way to do it? > > > > > > I went into the floor planner and poked around and figured out that my > > > net names are changed by the tool, as they are not in the design at > > > all. I tried the Keep constraint, to try and coerce the tool into > > > keeping my name, and it still complains. > > > > > > So, the bottom line questions: > > > > > > Is this the correct approach? > > > > > > How do I determine correctly what names my nets have been given? > > > > > > ClydeArticle: 51221
Valentin, First thing you need to understand, is the timing relationship between the VALUE and STROBE input signals and the clock frequency of your synchronous system. The answer to the above will lead to different approaches for solving the problem. -- If the STROBE pulse duration is less than one clock period (plus required setup time), you will not be able to achieve stable synchronization - find a way to extend the STROBE pulse or increase the clock frequency. -- If the STROBE pulse duration is guaranteed to be more than one clock period and less then 3 clock periods (plus required setup time) then there could be two cases: ---- 1. The VALUE signal is guaranteed to be stable for period "setup time" before and "hold time" after any of the STROBE pulse edges than use the STROBE input as clock to REG in order to register (not latch) the VALUE. ---- 2. The VALUE signal is NOT guaranteed to be stable for period "setup time" before and "hold time" after any of the STROBE pulse edges than use the STROBE input as gate to REG in order to latch VALUE. ---- After VALUE is latched/registered (see 1 or 2), create three stage (sh_reg(2 downto 0)) shift register and feed STROBE to its serial input (sh_reg(0)). Use "sh_reg(1) AND NOT sh_reg(2)" to generate one clock synchronized strobe pulse, which can be used to qualify the already latched/registered VALUE. -- If the STROBE pulse duration is guaranteed to be more than three clock periods, there could be two cases: ---- 1. If the VALUE signal is stable on the rising edge of STROBE - use the above method via registering VALUE on the rising edge of STROBE. ---- 2. If the VALUE signal is stable on the falling edge of STROBE, or STROBE is to be used as gate to a latch - use "sh_reg(2) AND NOT sh_reg(1)" to generate one clock synchronized strobe pulse. Hope this helps! Regards, Oggie "valentin tihomirov" <valentin@abelectron.com> wrote in message news:<3e198cc4$1_2@news.estpak.ee>... > Hello, > I have a synchronous system, but there is a parameter that comes (n bits > long) that comes from external world. This value is stored int input buffer > (register). The master device that provides this value also provides a > strobe signal for the register. I don't know whether this STOBE signal > should be LATCH (active high) or FF (load a value on L2H trasition). I have > another question. Is there any problem when data is being stored into > register and read simultaneously? This should lead to inconsistent state > when some of the bits read from the register are updated while others still > arn't. Which is a standard way to synchronise data load? Asynchronous > handshking? > > > > > _______ ____________________ > | | | | > VALUE ==+ REG | | System with clock| > | +--->| | > STROBE --+ | | | > |_______| | | > | | > |____________________|Article: 51222
allan_herriman.hates.spam@agilent.com (Allan Herriman) wrote in message news:<3e1a7494.97634440@netnews.agilent.com>... > On Tue, 7 Jan 2003 00:36:13 -0500, "David" <gretzteam@hotmail.com> > wrote: > > >Hi, > >I have some vhdl code of a sigma-delat modulator that produces a one-bit > >output... use modelsim to simulate the vhdl code and pspice for analog > >simulations but I never had to mix those two. I could possibly write the > >Does anyone know a software that allows to perform vhdl simulation as part > >of an analog circuit? > received two suggestions about how to perform this simulation. > If you rejected them, please let us know why. Presumably there are > additional requirements not mentioned in your post. > Allan Those solutions referred could do the work, thus I agree with Alan. I used to simulate a 8-bit adder providing inputs about the same way. However, if you are capable in VHDL, and want an integrated solution you could write the Sigma-Delta is VHDL-AMS (easy to get example in the net). Then, your problem would be the tool, for free evaluation AMSWizard, or Dolphin Smash probably. These simulators interface the analog and digital simulation "islands" by the appropriate boundary conditions. There is a slight possibility the Smash tool does exactly what you want for both VHDL/Verilog against SPICE. Uncle "The G.B. Man" NoahArticle: 51223
>-- If the STROBE pulse duration is guaranteed to be more than one clock >period and less then 3 clock periods (plus required setup time) then >there could be two cases: How about using STROBE to clock a 1 into a FF and then using an async reset to clear that FF. (I don't like async kludges, but this is the sort of narrow place where I'll use them if I don't have a better idea.) -- The suespammers.org mail server is located in California. So are all my other mailboxes. Please do not send unsolicited bulk e-mail or unsolicited commercial e-mail to my suespammers.org address or any of my other addresses. These are my opinions, not necessarily my employer's. I hate spam.Article: 51224
"Clyde R. Shappee" wrote: > > The carry chain starts at a node tied to a logic zero.... > > Forget the application.... for now, you are asking too many questions and going > too deep. > > Same question, said a different way, what if I had a decoder whose address was > internally derived, did not come in from the outside, and I wanted to insure that > from address in to decode out, the prop delay was less than Y ns. > > The VHDL is well constructed. I am just trying to (as I said before, possibly as > only an exercise) figure out how to constrain the timing for the least delay. I understand what you are trying to do, but not why you are doing it this way. A carry chain does not start at a grounded input for purposes of timing. That grounded input is *always* grounded and so will not be used in any timing analysis. In this design the addends are the only inputs. If they are also grounded or tied high they will also not be used for timing. In fact, this would explain why you get no logic. In the same way that a compiler will precalculate math on constants and not produce code to do that, the synthesizer will perform the logic operations on fixed inputs and produce a single output corresponding to the result. If your addends are not fixed, then they either have to come from FFs or from IO pins. The timing tools just do not calculate timing on purely combinatorial logic that is not connected to an IO. The backend tools will remove logic that is not sourced and driving either FFs or IO pins. Unfortunately the tools are only designed to help solve real problems in real chips, not theoretical analysis of simplified designs. But this is not hard to work around. So what is driving the adders and where do the outputs go in your test desigin? -- Rick "rickman" Collins rick.collins@XYarius.com Ignore the reply address. To email me use the above address with the XY removed. Arius - A Signal Processing Solutions Company Specializing in DSP and FPGA design URL http://www.arius.com 4 King Ave 301-682-7772 Voice Frederick, MD 21701-3110 301-682-7666 FAX
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