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Eric Bohlman wrote: > > Spam Hater <spam_hater_7@email.com> wrote in > news:jve7cvgldg4va3thk6pbubq18rjuh07van@4ax.com: > > > I always forget which one is which, but I prefer the one where the > > outputs come directly from the flops. And yes, it's a -personal- > > bias. > > That's true of a correct implementation of either model. In a Mealy > machine, the output at time t+1 is a function of both the current state at > time t and the input at time t. In a Moore machine, the output is a > function of the current state only. Some people implement Mealy machines > sloppily, with the output being a *combinatorial* function of the current > state and the input, but that's not an inherent characteristic of the > model. Actually, that is not the "sloppy" Mealy machine, it is the literal Mealy machine. If you register the outputs in a Mealy machine so that the outputs are a function of the previous inputs and state, you have simply converted your machine to a Moore machine while leaving the outputs out of the state description. But it is still a Moore machine. Some people call this a modified Moore machine or even a modified Mealy machine. -- Rick "rickman" Collins rick.collins@XYarius.com Ignore the reply address. To email me use the above address with the XY removed. Arius - A Signal Processing Solutions Company Specializing in DSP and FPGA design URL http://www.arius.com 4 King Ave 301-682-7772 Voice Frederick, MD 21701-3110 301-682-7666 FAXArticle: 55951
I tend to call it "firmware" if it's programmable but it's sold and documented as hardware. That mostly means the user isn't expected to program it. That's not really clean. The end-user isn't expected to write device drivers, but they are "obviously" software. -- The suespammers.org mail server is located in California. So are all my other mailboxes. Please do not send unsolicited bulk e-mail or unsolicited commercial e-mail to my suespammers.org address or any of my other addresses. These are my opinions, not necessarily my employer's. I hate spam.Article: 55952
Hello everybody, I was wondering if someone tried the 'Internet Design Team' tool. This word was coined in the VitexE datasheet. Is it some broad concept that was introduced at that time in order to do multi-million gates design or does Xilinx, in their ISE, offer support for actual internet shared development of projects. ThanksArticle: 55953
Altera has some nice ones. I think tier NIOS development board is on special for $495. "Atif" <atif@kics.edu.pk> wrote in message news:6a0a3f23.0305232057.7dfb813c@posting.google.com... > I'm new to FPGA's. Can anyone please suggest me where to start? > AlsoI want to buy an FPGA board. Please tell me the specifications of > any FPGA board that costs about $200-$500. From where I'll purchase > it? > Thanks > AtifArticle: 55954
Altera has some nice ones. I think thier NIOS development board is on special for $495. "Atif" <atif@kics.edu.pk> wrote in message news:6a0a3f23.0305232057.7dfb813c@posting.google.com... > I'm new to FPGA's. Can anyone please suggest me where to start? > AlsoI want to buy an FPGA board. Please tell me the specifications of > any FPGA board that costs about $200-$500. From where I'll purchase > it? > Thanks > AtifArticle: 55955
Why is there such a large difference between the ratio of "flops"/IO on a CPLD vs a FPGA? Something like a UART takes a trivial amount of space in an FPGA, but would fill a medium sized CPLD (which will only be available in packages with 100+ IOs). -- Ben Jackson <ben@ben.com> http://www.ben.com/Article: 55956
"Alex Gibson" <alxx@ihug.com.au> wrote in message news:bamooh$5g2$1@lust.ihug.co.nz... > > > Try using modeltechxe from xilinx. > Not had a single problem with 5.6e. make that modelsimxe. Runs fine under windows xp pro and home. > > Suggest completely uninstalling -> reboot > delete any directories that may be left for modeltech. > Then reinstall. > > You may have caused this problem by installing over the top of > your previous modeltech install. > > Also when installing turn off antivirus software. > > Alex > >Article: 55957
"Steve Casselman" <sc_nospam@vcc.com> wrote in message news:<onYya.2207$qf4.35448016@newssvr21.news.prodigy.com>... > It is software.. When I put my design for an xr16 microcontroller for Virtex up on the web, I released it under the GPL. So the source code's GPL headers all say "This program is free software". I thought about this question at the time, and decided that's what it is. --Mike http://users.easystreet.com/mbutts/xr16vx_jhdl.htmlArticle: 55958
Hi all, This is my first post to this group. I am just starting out with programable logic, and have chosen the Xilinx XC9500 range of CPLD's to use. I have downloaded the datasheets for the 9536 and the 9572 and also a couple of app notes from the Xilinx site. The only thing I can't find is some information on the pinouts of these devices. It is not in the datasheets. With the micro-controllers I have been using the datasheet always provides a pinout and a "typical circuit" including the required external components to get the thing up and running... Am I missing something here? Can anyone point me in the right direction? Thanks for any and all advice, regards, James Fitzsimons (Remove the obvious from the email address if you want to contact me directly)Article: 55959
Ben Jackson wrote: > > Why is there such a large difference between the ratio of "flops"/IO > on a CPLD vs a FPGA? Something like a UART takes a trivial amount > of space in an FPGA, but would fill a medium sized CPLD (which will > only be available in packages with 100+ IOs). There is certainly a difference in the number of FFs between an FPGA and a CPLD. But otherwise there is still a great deal of functionality in a CPLD. I have not coded a UART in a long time and a UART can include a wide range of features. But if you wanted to implement a basic UART, not counting FIFOs or the baudrate generator, I don't see any reason that you couldn't implement one in a smaller CPLD of 64 macrocells. A UART needs a pair of doubled buffered 8 bit registers, plus control logic including a couple of counters (3/4 bit) for the bit and word timing in each direction. So you have 32 bits of register for the data and 14 bits of counters. Figure another dozen bits of FSM for control and you still have a few macro cells left over. Most CPLDs allow you to use the logic and register separately, so you still have tons of logic next to the 32 bits of data registers. This comes in a 48 pin TQFP which is only 9 mm on a side, including pins. I am not sure you can even find a UART in a package this small. The price is only $4 or so and the programming software is free. Now this may not use a lot of the FFs in an FPGA, especially since many have memory or SRLs for the registers and FIFOs, but it will use a bit more cells for logic than the CPLD since the FSM bits can't be done in a single LUT typically. So it will take only a portion of a small FPGA, but that FPGA will cost you $10 or more and come in a much larger package. If you don't have much else to put in it, you will be paying a lot more and using a lot more real estate on your board than a CPLD. I am doing a new design which needs 5 volt tolerance on a large number of pins. FPGAs with 5 volt inputs are long gone and the Xilinx CPLDs that fit this socket are very expensive. I found a Lattice CPLD that not only does the job very well, it is tons cheaper and allows you to trade off banks of logic as memory! This is getting very close to FPGA functionality and it uses a *lot* less power! Lattice is the company that bought the ORCA FPGA line from Lucent. I don't know how much they are promoting the ORCA parts, but they seem to be doing a lot with the technology underlying them. They have new FPGA and CPLD lines that are worth looking at. I had pretty much ignored them (looked but did not see...) until an FAE got me to look a bit harder. -- Rick "rickman" Collins rick.collins@XYarius.com Ignore the reply address. To email me use the above address with the XY removed. Arius - A Signal Processing Solutions Company Specializing in DSP and FPGA design URL http://www.arius.com 4 King Ave 301-682-7772 Voice Frederick, MD 21701-3110 301-682-7666 FAXArticle: 55960
"James Fitzsimons" <jamesfit@nospam.paradise.net.nz> wrote in message news:20030525175115412+1200@news.paradise.net.nz... > Hi all, > This is my first post to this group. I am just starting out with > programable logic, and have chosen the Xilinx XC9500 range of CPLD's to > use. I have downloaded the datasheets for the 9536 and the 9572 and also > a couple of app notes from the Xilinx site. > > The only thing I can't find is some information on the pinouts of these > devices. It is not in the datasheets. With the micro-controllers I have > been using the datasheet always provides a pinout and a "typical > circuit" including the required external components to get the thing up > and running... > Xilinx often puts the pinouts in a separate doc. I have a 'getting started' page on using the 9536 on my web site. It's somewhat out of date, it should use the WebPack software now. Leon -- Leon Heller, G1HSM leon_heller@hotmail.com http://www.geocities.com/leon_hellerArticle: 55961
James Fitzsimons wrote: > > Hi all, > This is my first post to this group. I am just starting out with > programable logic, and have chosen the Xilinx XC9500 range of CPLD's to > use. I have downloaded the datasheets for the 9536 and the 9572 and also > a couple of app notes from the Xilinx site. > > The only thing I can't find is some information on the pinouts of these > devices. It is not in the datasheets. With the micro-controllers I have > been using the datasheet always provides a pinout and a "typical > circuit" including the required external components to get the thing up > and running... > > Am I missing something here? Can anyone point me in the right direction? If they document the 9500 parts like they do the Coolrunner parts, there is a data sheet for the common specs of the family and a separate sheet for each of the different members. The pinouts will be in the device specific data sheets. But the package dimensions will be in yet another datasheet. -- Rick "rickman" Collins rick.collins@XYarius.com Ignore the reply address. To email me use the above address with the XY removed. Arius - A Signal Processing Solutions Company Specializing in DSP and FPGA design URL http://www.arius.com 4 King Ave 301-682-7772 Voice Frederick, MD 21701-3110 301-682-7666 FAXArticle: 55962
In article <3ED05CCA.A4C36FBE@yahoo.com>, rickman <spamgoeshere4@yahoo.com> wrote: >Ben Jackson wrote: >But if you wanted to implement a basic UART, >not counting FIFOs or the baudrate generator, It's actually clock dividers that turn out to hurt the most. Whether you use the extra speed to oversample, or just use a divider to run everything slower, you need a lot of bits (relative to the size of a small CPLD) to make it work. Now I see why Xilinx's new CoolRunner CPLDs have a dedicated clock divider. >A UART needs a pair of doubled buffered 8 bit registers, plus control >logic including a couple of counters (3/4 bit) for the bit and word >timing in each direction. So you have 32 bits of register for the data >and 14 bits of counters. Figure another dozen bits of FSM for control >and you still have a few macro cells left over. Which will be consumed by TX/RX, control lines (eg receive interrupt, read/write) and probably another 8 bit register to multiplex in/out datalines, and a bit to control whether they're tristated... What prompted my post was my experience trying to fit the PS/2 mouse core (from opencores.org) onto a XC9572 (note: just for fun!). I'm not even using most of the output (so several registers are optimized away). I've reworked the shift register to use a flag bit instead of a counter, which required reworking the reset part of the state machine, and I'm running it at a much lower clockspeed to save on the watchdog timeout bits and debounce counter. I've gotten the product terms down by counting to powers of 2 instead of arbitrary values. Still it just squeaks by. To actually get both X/Y and button data would require a larger part. And this doesn't even do anything complicated like accumulate net position -- it just does uart-like serial decoding and would require constant external sampling to accumulate a position. -- Ben Jackson <ben@ben.com> http://www.ben.com/Article: 55963
In article <3ED05CCA.A4C36FBE@yahoo.com>, rickman <spamgoeshere4@yahoo.com> wrote: >Ben Jackson wrote: >I found a Lattice CPLD that >not only does the job very well, it is tons cheaper and allows you to >trade off banks of logic as memory! This is getting very close to FPGA >functionality and it uses a *lot* less power! I forgot to ask in my reply: Which part? I went to latticesemi.com and to pare down the selection to reasonable items I tried DigiKey for prices, but they don't have anything. Neither does Mouser. Where are you buying them? -- Ben Jackson <ben@ben.com> http://www.ben.com/Article: 55964
> Having built my own Parallel Cable III and a board with a PC44 for > XC9536/72, my feeling is: don't do it. Just buy one of the ~$85 boards Why ? Its one of the easiest projects to do. The programming cable is basically a few wires - if they are short enough you can even get along without the driving xx245. The CPLD byself needs a power connection and a blocking cap. No problem if you got one or two hours to spare. > with an XC95108 on it. elexp.com (part# 01PLDT-3) has one that looks > nice for $100 in quantity 1. There are lots of others. Or better yet, > get an FPGA dev board. I had no idea how relatively wimpy CPLDs were! > If you want to replace a handful of 7400 series logic parts, a CPLD is > a good bet. If you want to replace a bus controller, microcontroller, > etc, then you need an FPGA (CPLDs that even come close in flexibility > are in very-hobbiest-unfriendly packages like FBGA and VQFP). Well, you can still get Spartans in PLCC packages for not-so-much money. But they are small.. Certainly, CPLDs are not meant to implement huge designs. Their structure is benefitial for designs with few states and lots of I/O - glue logic. But that does not mean you can not do interesting things with them: http://www.tuhh.de/~setb0209/cpu/mcpu.html I would not recommend to a newbie to try building a FPGA board. Too much hassle with the power supply, programming devices etc..Article: 55965
"James Fitzsimons" <jamesfit@nospam.paradise.net.nz> wrote in message news:20030525175115412+1200@news.paradise.net.nz... > Hi all, > This is my first post to this group. I am just starting out with > programable logic, and have chosen the Xilinx XC9500 range of CPLD's to > use. I have downloaded the datasheets for the 9536 and the 9572 and also > a couple of app notes from the Xilinx site. > > The only thing I can't find is some information on the pinouts of these > devices. It is not in the datasheets. With the micro-controllers I have > been using the datasheet always provides a pinout and a "typical > circuit" including the required external components to get the thing up > and running... > > Am I missing something here? Can anyone point me in the right direction? > > Thanks for any and all advice, > regards, > James Fitzsimons > > (Remove the obvious from the email address if you want to contact me > directly) few links that might be of use Have you had a close look at all the datasheets includinh the ones for each device in the family. ie for a xc9572xl pcc44 pin out look at the doc for that device. xc9572xl pc44 buying from xilinx comes out at around US$2 more depending where you are for postage have a look under cplds in the xilinx online store for the docs for each device Also the newer collrunner2's are very nice. especially the board that comes with the xilinx coolrunner2 design kit US$50 or can also get the same board from www.digilentinc.com who make it for xilinx with a few more options. http://www.digilentinc.com/XC2/index.html if you going to get one having the breadboard and extra connectors is really handy for using with your own boards or making addon boards with veroboard etc They also have peripheral boards http://www.digilentinc.com/Catalog/peripheral_boards.html http://www.xilinx.com/xlnx/xil_prodcat_product.jsp?title=cpldsolutions_cpldlearn_page http://www.xilinx.com/xlnx/xil_prodcat_product.jsp?title=cpldsolutions_cpldstart_page http://www.xilinx.com/xlnx/xil_prodcat_product.jsp?title=reference_designs http://www.xilinx.com/publications/products/cpld/logic_handbook.pdf http://www.xilinx.com/apps/epld.htm app notes http://www.xilinx.com/xlnx/xil_prodcat_product.jsp?title=reference_designs get your free webpack cd http://www.xilinx.com/ise/ise_promo/ise5_eval.htm download webpack http://www.xilinx.com/webpack/index.htm full is 171MB cpld is 108MB also get MXE simulator another 18MB for cpld or 65MB for full http://www.opencores.org/projects/ http://www.opencores.org/projects/usb/ http://www.opencores.org/projects/usb1_funct/ for another free book http://www.xess.com/pragmatic-2_1.html http://www.xess.com/ho03000.html#Examples http://www.xess.com/ho07000.html soft microprocessor http://www.xilinx.com/ipcenter/processor_central/picoblaze/member/ http://www.xilinx.com/xlnx/xil_prodcat_landingpage.jsp?title=Processor+Central http://www.xilinx.com/xlnx/xil_prodcat_product.jsp?title=third_party http://www.fpgacpu.org/ www.opencores.org/projects including a pic , 8051 , avr etc vhdl news:comp.arch.fpga news:comp.lang.vhdl http://www.vhdl.org/comp.lang.vhdl/ faqArticle: 55966
"James Fitzsimons" <jamesfit@nospam.paradise.net.nz> wrote in message news:20030525175115412+1200@news.paradise.net.nz... > Hi all, > This is my first post to this group. I am just starting out with > programable logic, and have chosen the Xilinx XC9500 range of CPLD's to > use. I have downloaded the datasheets for the 9536 and the 9572 and also > a couple of app notes from the Xilinx site. > > The only thing I can't find is some information on the pinouts of these > devices. It is not in the datasheets. With the micro-controllers I have > been using the datasheet always provides a pinout and a "typical > circuit" including the required external components to get the thing up > and running... > > Am I missing something here? Can anyone point me in the right direction? > > Thanks for any and all advice, > regards, > James Fitzsimons There is no *typical circuit* you hook up the power and the JTAG and the way you use it is totally up to you. I find the 9500XL parts one of the most handy parts around $1 or $2.40 for 36 or 72 macrocells. The 72 version has plenty of space to do a few registers and lots of combinational logic. Nice and easy to use, and great fun to learn. Have fun. RalphArticle: 55967
"Ben Jackson" <ben@ben.com> wrote in message news:VXVza.1011000$S_4.1022928@rwcrnsc53... > Why is there such a large difference between the ratio of "flops"/IO > on a CPLD vs a FPGA? Something like a UART takes a trivial amount > of space in an FPGA, but would fill a medium sized CPLD (which will > only be available in packages with 100+ IOs). > CPLD's are 1. Cheap 2. Fast 3. FLASH based (read secure) If you want a uart, TI make some very nice dual channel ones for $3. And $3 with a $2 cpld come nowhere near the cost of a FPGA on your board. CPLD's are great for replacement of lots of logic, memory mapping, latching, IO etc. RalphArticle: 55968
In article <bapvhe$2653e$1@ID-107613.news.dfncis.de>, Tim Boescke <tboescke@uwaterloo.ca> wrote: > >> Having built my own Parallel Cable III and a board with a PC44 for >> XC9536/72, my feeling is: don't do it. Just buy one of the ~$85 boards > >Why ? Its one of the easiest projects to do. The programming >cable is basically a few wires - if they are short enough >you can even get along without the driving xx245. The CPLD >byself needs a power connection and a blocking cap. No problem >if you got one or two hours to spare. In retrospect, I think the cost of the demo boards that are available is very reasonable, and as it turns out they're not as far from what I wanted as I thought when I decided to build. Let me refine my suggestion: If you are so cheap that you would cut any corner and bear any burden to avoid spending money, take a PC44 socket, turn it upside down, solder wires to the various pins (solder your decoupling caps on directly and only bring out one pair of power/ground). If you are slightly less cheap, buy a PC44-DIP adapter. Make sure you have a pair of breadboards that will sit side by side and hold this surprisingly wide card. If you are a lot more motivated, design and etch a PCB. Kind of a pain to get PC44 socket signals out on a single layer (can't solder to the top layer under the socket!). Get something like Mouser #517-974-01-36, which are pin sockets on 0.1" centers that you can use with breadboard jumpers. (those are 36 wide, cut to length, you can buy them in other lenghts). If you are even less cheap and less motivated, buy a demo board. >Well, you can still get Spartans in PLCC packages for not-so-much money. >But they are small.. Thanks for pointing that out! Xilinx really downplays their old product lines. -- Ben Jackson <ben@ben.com> http://www.ben.com/Article: 55969
Thanks for all the responses. Some of those links were really helpful. Turns out I am just blind and the datasheets I had downloaded did of course have the pinouts in them. They are just a bit different from the datasheets I am used to reading. I guess I should take a little more care and read slower ;-) I am really looking forward to delving into the world of programmable logic. Thanks for the help! Regards, James FitzsimonsArticle: 55970
rickman <spamgoeshere4@yahoo.com> wrote: : I am doing a new design which needs 5 volt tolerance on a large number : of pins. FPGAs with 5 volt inputs are long gone and the Xilinx CPLDs : that fit this socket are very expensive. I found a Lattice CPLD that : not only does the job very well, it is tons cheaper and allows you to : trade off banks of logic as memory! This is getting very close to FPGA : functionality and it uses a *lot* less power! SpartanII and XC95XL run from 3.3V but are perfectly 5Volt tolerant... -- Uwe Bonnes bon@elektron.ikp.physik.tu-darmstadt.de Institut fuer Kernphysik Schlossgartenstrasse 9 64289 Darmstadt --------- Tel. 06151 162516 -------- Fax. 06151 164321 ----------Article: 55971
Hi Leon, >> I have a 'getting started' page on using the 9536 on my web site. Just checked out your site, you've got some handy information up there! I was just wondering what U1 was on the schematic on your pld_starter page? Also, what size caps do you use there? Cheers, James FitzsimonsArticle: 55972
James Fitzsimons <jamesfit@nospam.paradise.net.nz> wrote: : Hi all, : This is my first post to this group. I am just starting out with : programable logic, and have chosen the Xilinx XC9500 range of CPLD's to : use. I have downloaded the datasheets for the 9536 and the 9572 and also : a couple of app notes from the Xilinx site. A hint: Consider using the XC95XL (3.3 Volt supply/ 5 Volt tolerance). They are cheaper and offer a wider input function. Bye -- Uwe Bonnes bon@elektron.ikp.physik.tu-darmstadt.de Institut fuer Kernphysik Schlossgartenstrasse 9 64289 Darmstadt --------- Tel. 06151 162516 -------- Fax. 06151 164321 ----------Article: 55973
"Ben Jackson" <ben@ben.com> wrote in message news:oG1Aa.262045$pa5.251561@rwcrnsc52.ops.asp.att.net... > > If you are so cheap that you would cut any corner and bear any burden > to avoid spending money, take a PC44 socket, turn it upside down, solder > wires to the various pins (solder your decoupling caps on directly and > only bring out one pair of power/ground). > > If you are slightly less cheap, buy a PC44-DIP adapter. Make sure you > have a pair of breadboards that will sit side by side and hold this > surprisingly wide card. one of the cheaper ones I've found for a decent adaptor(winslow brand) is from http://www.batronix.com/electronic/e-shop.shtml (scroll down to near the bottom) http://www.batronix.com/photos/WA044127.jpg I've got a couple that have lasted really well compared to some of the cheaper ones. Alex GibsonArticle: 55974
PawelT wrote: >> I've tried downloading the newer version off the net but it's a big >> file and I've got a 56k modem and my ISP cuts me off after 2 hours >> which makes it impossible to download it in time. :( > maybe some kind of dowload manager can help, if the connection is > beak. I use flashget, but (fortunately) i've got "permanent" > connection to the Internet. > >> >> I think I might ring up Altera in the UK to see if they'll send me a >> CD. > > Try to subscribe Digital Library from Altera - there is a Baseline, > and other digital data. > Or just call to lokal representative, or other firm with sell software > for digital circuits. I think I'll ring them up to see if they'll send me a CD to save me downloading it for hours and hours. BTW, I read this and it has a better description of distributed arithmetic than in the DSP with FPGAs book: http://www.xilinx.com/appnotes/dspguide.pdf Also there's loads of useful Application Notes for DSP with FPGAs here: http://www.xilinx.com/xlnx/xil_prodcat_product.jsp?title=literature_training -- DAB sounds worse than FM, Freeview, Digital Satellite and Cable -- http://www.digitalradiotech.co.uk/ Subscribe for free to the Digital Radio Listeners' Group Newsletter
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