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Hi - If some of the designs I've seen are any indication, I'd classify FPGA design as "be-ware." Bob Perlman Cambrian Design Works On 21 May 2003 12:26:38 -0700, joefrese@hotmail.com (Joe Frese) wrote: >I've got a question of terminology for the group: is FPGA design >generally classified as hardware, firmware, or neither? Most of the >designs I've worked on have served to interface firmware with >hardware. It seems that firmware engineers like to think of FPGA >designs as more firmware, and that hardware engineers like to think of >FPGA designs as more hardware. As an FPGA developer, though, I'm of >the mind that the unique design considerations of the technology >justify a new and separate category . . . > >A coworker suggested the term "coreware," but apparently that's a >registered trademark of LSI Logic. Is there another term with the >-ware suffix commonly used to refer to code (VHDL, Verilog, or >otherwise) intended to be implemented in an FPGA? > >JoeArticle: 55851
I'm looking for an fpga core that will emulate the TI tms34010 graphic processor. Has anyone heard of one available or know of design services that would create one? Thanks PaulArticle: 55852
"Joe Frese" <joefrese@hotmail.com> wrote in message news:c176b8c2.0305211126.6e642649@posting.google.com... > I've got a question of terminology for the group: is FPGA design > generally classified as hardware, firmware, or neither? Slushware.Article: 55853
I've called it 'gateware' many times in the past, and customers do seem to
understand and like the term.
Joe Frese wrote:
> I've got a question of terminology for the group: is FPGA design
> generally classified as hardware, firmware, or neither? Most of the
> designs I've worked on have served to interface firmware with
> hardware. It seems that firmware engineers like to think of FPGA
> designs as more firmware, and that hardware engineers like to think of
> FPGA designs as more hardware. As an FPGA developer, though, I'm of
> the mind that the unique design considerations of the technology
> justify a new and separate category . . .
>
> A coworker suggested the term "coreware," but apparently that's a
> registered trademark of LSI Logic. Is there another term with the
> -ware suffix commonly used to refer to code (VHDL, Verilog, or
> otherwise) intended to be implemented in an FPGA?
>
> Joe
--
--Ray Andraka, P.E.
President, the Andraka Consulting Group, Inc.
401/884-7930 Fax 401/884-7950
email ray@andraka.com
http://www.andraka.com
"They that give up essential liberty to obtain a little
temporary safety deserve neither liberty nor safety."
-Benjamin Franklin, 1759
Article: 55854Joe, Clearly we have many good choices: aware (.....company specific) beware (of imitators) nowhere (before its configured) somewhere (IP from public sources) what to wear? (what a FPGA says when it wakes up) forebear (me trying to resist replying) forswear (all future newsgroup posts ....) be fair! (our common plea) low fare (the Spartan product line) and my favorite: wash 'n wear (reprogrammable upgrades) But why to they call it "field" when no one programs them while on the farm? Austin Joe Frese wrote: > > I've got a question of terminology for the group: is FPGA design > generally classified as hardware, firmware, or neither? Most of the > designs I've worked on have served to interface firmware with > hardware. It seems that firmware engineers like to think of FPGA > designs as more firmware, and that hardware engineers like to think of > FPGA designs as more hardware. As an FPGA developer, though, I'm of > the mind that the unique design considerations of the technology > justify a new and separate category . . . > > A coworker suggested the term "coreware," but apparently that's a > registered trademark of LSI Logic. Is there another term with the > -ware suffix commonly used to refer to code (VHDL, Verilog, or > otherwise) intended to be implemented in an FPGA? > > JoeArticle: 55855
Dear Jens:
Just this morning I was studying the ethernet mac on the opencores web
site. In it you will find register.v and registers.v where registers.v
instantiates a series of registers for the ethernet mac using a number of
register.v modules. I suspect studying that code will help you.
http://www.opencores.org
"Jens Nowack" <its.me.hates-spam@uni.de> wrote in message
news:b9nljo$ksmca$1@ID-192450.news.dfncis.de...
> Hallo,
>
> I want to create a register in the fpga to store control settings. There
> should be e.g. 256 registers in it with a wide of e.g. 16 Bit.
> The selection of internal registers will be done using the adress bus of
the
> microcontroller. The external databus must be bi-directional and
tristate.
> The registers can be written from the microcontroller or the FPGA. And I
> must have a direct read access to the registers in the FPGA without
> adressing to controll the logical circuits. So a RAM is useless, i think.
>
>
> Now my question:
> whats the best way to realise this task? I use an Altera Cyclone FPGA with
> VHDL as programming language. Maybe, a little example would be usefull.
>
> Thanks a lot,
>
> regards
>
>
>
Article: 55856Austin Lesea wrote: > But why to they call it "field" when no one programs them while on the > farm? What about in the oil fields? Or does that count? -- Phil HaysArticle: 55859
I want to implement a state machine in a small PLD or FPGA using some sort of HDL like AHDL, WinCUPL, etc. However, I don't want to supply an external clock to the part. I'd like to know if it is possible to use an inverter inside the CPLD, feeding back the output of the inverter to the input of the inverter, thus creating a "clock". Then, I want to attach that "clock" to the part's global clock net and use that clock as the clock for my state machine. Is something like this possible? What I'm really trying to do is implement an asynchronous state machine that changes state only when its inputs change, without regard to clocks. I don't have a clock to supply to the system. What I'm finding, though, is most HDLs assume state machines are synchronous and expect a clock. (and reset, for that matter.) If I have to use a clock to implement the state machine, I would of course have to synchronise the asynchronous inputs with the state machine clock. Simple enough, but I'd really rather not have to supply an external clock to the system if at all possible. I'm not limiting myself to any particular part of language, but I'd like to try to keep to what I'm familiar with (AHDL, WinCUPL, etc.) Other parts and HDL suggestions are welcome, especially those that might have Async State Machine constructs. FYI, I expect the state machine to have 4 inputs, 4 outputs (the outputs are NOT the state bits but different), and 13 defined states (implying 4 state bits). (It seems that most HDLs default to D flipflops as the state bits, and D-flops need a clock. Is there anyway to default to, say, a JK flop and not require a clock, but derive next state equations for the J & K inputs? A compiler that does this would be great, as I expect the equations to be rather cumbersome for me to realize manually.) Thanks for any suggestions. Sincerely, Jim RanlettArticle: 55860
Hi, I'm designing a clock gen module with virtex-II DCMs. I can get the recommend timing parameters from datasheet, such as frequency, period jitter, phase skew, and lock time. For some parameters like frequency and lock time, it's easy to verify when I do post-PAR simulation. But for the others like jitter and skew, how can I simulate them to get the exactly value for my application? My work environment is ISE 5.1i + Modelsim SE. Thanks.Article: 55861
Classy reply.... "Austin Lesea" <Austin.Lesea@xilinx.com> wrote in message news:3E88D9AE.B377126C@xilinx.com... > Raymund, > > No, last I looked, I still had "engineer" in my title. Still have to run > simulations, do fourier transforms, examine pcb layouts, create circuits and > designs. > > Still have a job, too. How many positions are open for ASIC designers? Are you > one of the very lucky, very few, still employed? > > Austin > > raymund hofmann wrote: > > > "Austin Lesea" <Austin.Lesea@xilinx.com> wrote in message > > news:3E887532.31FE90B4@xilinx.com... > > > Nicholas, > > > > > > Now we are talking about even less money for 1M+ gates in 90 nm. > > > > > > ASICs are all but dead except for those really big jobs that can afford > > the > > > $80M++ price tag to develop them. Or those jobs where low current is > > required > > > (ie cell-phones). > > > > Or jobs that need more than 1000-10000 Parts ? > > Or jobs that need a unit price lower than 1/100 ? > > Or jobs that need some logic going fast ? > > > > > > > > Even televisions don't sell enough to afford some of the new ASIC > > pricetags. > > > Think about it. An "appliance" doesn't sell in large enough volume to > > have > > > its own ASIC. > > > > Or maybe they don't have engineers to handle a ASIC ? > > > > > So 'cheap' ASICs are stuck at 180nm (and above). But with 90nm FPGAs we > > are > > > three or more techology steps ahead (.15, .13, .09), and that makes us a > > > better deal. > > > > One should think about these things: > > > > Usually a FPGA needs around 15 times the transistors for implementing random > > logic compared to a standard cell ASIC. > > This means ~15 in Area. > > It looks similar for the delay to perform the same random logic. > > So one could say that 0.09 FPGA compares to a 0.35 STD Cell ASIC. > > One should also think about the process technology and NRE is getting more > > expensive the smaller it gets. > > But when going into details the things may look very different in favor of > > either ASIC or FPGA. > > > > The expensive FPGA's have no volume. > > > > The sweet spot for FPGA's is where the other costs for using it dominate the > > pure silicon area costs (which have some relation to the marketing price). > > > > Austin, > > > > Have you just recently joined the Marketing at Xilinx ? > > > > Raymund Hofmann >Article: 55862
Jim Ranlett wrote: > > I want to implement a state machine in a small PLD or FPGA using some > sort of HDL like AHDL, WinCUPL, etc. However, I don't want to supply > an external clock to the part. I'd like to know if it is possible to > use an inverter inside the CPLD, feeding back the output of the > inverter to the input of the inverter, thus creating a "clock". This makes a ring oscillator, and yes, that's doable. It is not very accurate, and consumes reasonable power ( as they tend to not be slow ). IIRC, we got ring-oscs built in ATF1502 foldback chains, down to 16MHz. Better may be to generate the clock, 'on demand' from the active IPs - much lower power, and in a simpler system like this, managable. > Then, > I want to attach that "clock" to the part's global clock net and use > that clock as the clock for my state machine. > > Is something like this possible? Yes, it is possible. > What I'm really trying to do is implement an asynchronous state > machine that changes state only when its inputs change, without regard > to clocks. I don't have a clock to supply to the system. What I'm > finding, though, is most HDLs assume state machines are synchronous > and expect a clock. (and reset, for that matter.) Creating an on-demand clock is reasonable, but doing without RESET is more risky - you could rely on the POR in the CPLD to default to a known state, but better is a RESET button, or similar, that ALWAYS take you to a known place. > If I have to use a clock to implement the state machine, I would of > course have to synchronise the asynchronous inputs with the state > machine clock. Simple enough, but I'd really rather not have to > supply an external clock to the system if at all possible. > > I'm not limiting myself to any particular part of language, but I'd > like to try to keep to what I'm familiar with (AHDL, WinCUPL, etc.) > Other parts and HDL suggestions are welcome, especially those that > might have Async State Machine constructs. > > FYI, I expect the state machine to have 4 inputs, 4 outputs (the > outputs are NOT the state bits but different), and 13 defined states > (implying 4 state bits). The outputs are derived from a simple 'rom-table' from the states ? Good candidate device would be a PEEL22LV10Z - that has hysteresis on the pins. > (It seems that most HDLs default to D flipflops as the state bits, and > D-flops need a clock. Is there anyway to default to, say, a JK flop > and not require a clock, but derive next state equations for the J & K > inputs? A compiler that does this would be great, as I expect the > equations to be rather cumbersome for me to realize manually.) JK still require a clock - you may mean Set/Reset ? D registers have an implicit illegal state coverage -> 0000, whilst toggle registers need all possible states defined. The best way to approach this, is to split it into 'two halves' - a fairly std, 4 register state engine, and a separate clock creation section, that takes current state, and enables active IP's to move to next state. The clock's generated are typically narrow ( a couple of Tpd's wide ). You need to watch Tsu.Th needs, and also may need external de-bounce if IPs are contact type. - jgArticle: 55863
I have always called it software. Since 1986. FPGAs are a kind of computer chip with a very strange programming model. The programming model was created by hardware engineers who were concerned about current spikes during programming. They were not concerned about reprogramming the device so much as just programming it the first time. They did not really care about programming parts of the device although that is starting to become more important as you get really large devices with embedded processors and internal programming ports. In the end it is software. It is based on sram it is updatable at any time. It can be stored on a disk or delievered over a network. It is software.. Steve "Joe Frese" <joefrese@hotmail.com> wrote in message news:c176b8c2.0305211126.6e642649@posting.google.com... > I've got a question of terminology for the group: is FPGA design > generally classified as hardware, firmware, or neither? Most of the > designs I've worked on have served to interface firmware with > hardware. It seems that firmware engineers like to think of FPGA > designs as more firmware, and that hardware engineers like to think of > FPGA designs as more hardware. As an FPGA developer, though, I'm of > the mind that the unique design considerations of the technology > justify a new and separate category . . . > > A coworker suggested the term "coreware," but apparently that's a > registered trademark of LSI Logic. Is there another term with the > -ware suffix commonly used to refer to code (VHDL, Verilog, or > otherwise) intended to be implemented in an FPGA? > > JoeArticle: 55864
ballsofsteel@rcsis.com (Jim Ranlett) wrote in message news:<53de32df.0305211648.7e8fcb54@posting.google.com>... > I want to implement a state machine in a small PLD or FPGA using some > sort of HDL like AHDL, WinCUPL, etc. ..... Is there a specific reason, why you mention AHDL? Nothing against Altera HDL, but if you'd choose a different HDL, e.g. VHDL, then the design would be more portable. ...just my 2c....Article: 55865
> > > Read the Xilinx website a bit more careful! > > > ... and find out that the Webpack is a free version of the > complete ISE, but it supports only the lower-end devices. > For me the biggest disadvantage in Webpack is that it lacks FPGA Editor. Also Core Generator is not included. The full comparison is here: http://www.xilinx.com/ise/devsys_feature_guide.pdf -- Robert PudlikArticle: 55866
Hi Johan I don't know if I have found your real problem but you can not connect the div output to the feadback input, only CLK0 and CLK2x can be. /Patrik Johan wrote: > Hi > I have a 50 MHz clock that I would like to run in 5 MHz. Thus making it > neccessary to use two clkdlls in serial. > > If I set the generic CLKDV_DIVIDE to 2 or use the default value, 2, the > lock signal appears. But if I use any other valid number than 2 the lock > signal does not appear even though the division of the clock seams ok in > the wavetrace. > > The same problem occurs both in ncsim and modelsim. > > My code and testbench can be found at http://bart.sm.luth.se/~johmat-8/ > > Regards > Johan >Article: 55867
"Charles Wagner" <Charles.Wagner@irisa.fr> wrote in message news:3ECB9C99.9090809@irisa.fr... > I use Cocentric SystemC Behavioral Compiler to synthesise a SystemC > specification implementing > a N stages pipelined datapath , with loops (for statement) and > pipeline_loop command. > Target technology is APEX20KE FPGA. > > This works fine with N<=4, but fails with N>4. > -- > -- schedule -io cycle_fixed -effort low > -- > -- Information: Mapping components to > FPGA........................................... > ............................................................ ..................................................... > > -- Error: Unable to communicate with FPGA Compiler II, launched from > /soft/synopsys_hd/2001.08/fpga_compiler2/bin/fc > -- 2_shell (HLS-608) > > Anybody has an idea why ? > I think you may have to contact Synopsys about this. However one thing is to see if you can check how long the command is that is being passed to fc2_shell, as perhaps it's becoming too long. Finally try finding out what HLS-608 means, on Unix you should be able to do man HLS-608 (apologies if you've done this already) regards Alan -- Alan Fitch HDL Consultant DOULOS - Developing Design Know-how VHDL * Verilog * SystemC * Perl * Tcl/Tk * Verification * Project Services Doulos Ltd. Church Hatch, 22 Market Place, Ringwood, Hampshire, BH24 1AW, UK Tel: +44 (0)1425 471223 mail: alan.fitch@doulos.com Fax: +44 (0)1425 471573 Web: http://www.doulos.com The contents of this message may contain personal views which are not the views of Doulos Ltd., unless specifically stated.Article: 55868
"ted" <edaudio2000@yahoo.co.uk> wrote in message news:c54bf83f.0305210741.e83c40e@posting.google.com... > How does one program the Altera configuration devices EPC1 and 1441? > > Can you use the standard parallel byteblaster cable, or do you need a > special programmer? if so, where cao I find some information? > > Can't seem to find any information on the Altera CD. You can use the ByteBlaster - just wire a socket up on a piece of prototyping board. I think you need a resistor or two but it's a long time since I did this with an EPC1. Leon -- Leon Heller, G1HSM leon_heller@hotmail.com http://www.geocities.com/leon_hellerArticle: 55869
Robert wrote: > For me the biggest disadvantage in Webpack is that it lacks FPGA Editor. > Also Core Generator is not included. > The full comparison is here: > > http://www.xilinx.com/ise/devsys_feature_guide.pdf And another disadvantage is that the big devices are not supported ;-) MarioArticle: 55870
PawelT wrote:
> Hello,
> I tried to implement fir using DA. I studied examples from book
> Uwe Meyer-Baese titled "Digital Signal Processing with FIeld
> Programmable Gate Arrays".
> I wrote fir in Matlab with coefficients h[] = {2 3 1} and for input
> x={1, 3, 7} i received y={2, 9, 24, 24, 7, 0, ...}.
> And my question is:
> Why is for DA_fir on output value y=18 (temporary acc p = {0, 24, 28,
> 18}) ? (Example 3.6 on pagee 98). Why is this different from "direct"
> response?
It helps to refer to Example 2.17 on page 63. If you look at the 2nd table
it has the input samples listed in a table as follows:
2 1 0 (sample number)
-----
1 1 1
1 1 0
1 0 0
then take the bit vectors row by row and cross-reference with the table
above on page 63:
1 1 1 = 6 (base 10)
1 1 0 = 4 (base 10)
1 0 0 = 1 (base 10)
then these base 10 numbers are assigned to table_out and used in the
statement:
p := p / 2 + table_out * 4;
So you have p as follows:
p = 0
p = 0 + 6 * 4 = 24
p = 24/2 + 4 * 4 = 28
p = 28/2 + 1 * 4 = 18
> How can i use da_fir instead of "direct" fir? And how i can receive
> the same output values like for "direc" fir?
> I would like to compare techiques such like CSD, RAG algorithm and
> distributed arithmetic, and i stopped on DA :(
You're doing better than me, it won't even allow me to compile the bloody
code....
Are you using XP? How did you get it working?
--
DAB sounds worse than FM, Freeview, Digital Satellite and Cable --
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Subscribe for free to the Digital Radio Listeners' Group Newsletter
Article: 55871
Perhaps, but it is different from the more traditional software in that there
are concurrency and timing issues that do not apply for traditional software.
The design flow is hardware, the result is perhaps software. For that reason,
it does make sense to differentiate it. I am constantly fighting the problems
introduced by people treating the FPGA contents as software when they do their
designs, and we see a fair amount of the results of that mentality here too. If
for no other reason than to avoid that leap, I think it is prudent to call it
something other than software.
Steve Casselman wrote:
> I have always called it software. Since 1986. FPGAs are a kind of computer
> chip with a very strange programming model. The programming model was
> created by hardware engineers who were concerned about current spikes during
> programming. They were not concerned about reprogramming the device so much
> as just programming it the first time. They did not really care about
> programming parts of the device although that is starting to become more
> important as you get really large devices with embedded processors and
> internal programming ports.
>
> In the end it is software. It is based on sram it is updatable at any time.
> It can be stored on a disk or delievered over a network.
>
> It is software..
>
> Steve
>
> "Joe Frese" <joefrese@hotmail.com> wrote in message
> news:c176b8c2.0305211126.6e642649@posting.google.com...
> > I've got a question of terminology for the group: is FPGA design
> > generally classified as hardware, firmware, or neither? Most of the
> > designs I've worked on have served to interface firmware with
> > hardware. It seems that firmware engineers like to think of FPGA
> > designs as more firmware, and that hardware engineers like to think of
> > FPGA designs as more hardware. As an FPGA developer, though, I'm of
> > the mind that the unique design considerations of the technology
> > justify a new and separate category . . .
> >
> > A coworker suggested the term "coreware," but apparently that's a
> > registered trademark of LSI Logic. Is there another term with the
> > -ware suffix commonly used to refer to code (VHDL, Verilog, or
> > otherwise) intended to be implemented in an FPGA?
> >
> > Joe
--
--Ray Andraka, P.E.
President, the Andraka Consulting Group, Inc.
401/884-7930 Fax 401/884-7950
email ray@andraka.com
http://www.andraka.com
"They that give up essential liberty to obtain a little
temporary safety deserve neither liberty nor safety."
-Benjamin Franklin, 1759
Article: 55872Ray Andraka <ray@andraka.com> writes: > VNC is fine for text stuff. It leaves quite a bit to be desired > for looking at simulation traces though. For pure text stuff, nothing beats screen (http://www.math.fu-berlin.de/~guckes/screen/). On a slow link, one might try TightVNC (http://www.tightvnc.com/). Supposedly, NX from http://www.nomachine.com/ is also good, you can get the non-GUI stuff under the GPL license (it's not very obvious from their website). HTH, ColinArticle: 55873
Hi Jim, > I want to implement a state machine in a small PLD or FPGA using some > sort of HDL like AHDL, WinCUPL, etc. However, I don't want to supply > an external clock to the part. I'd like to know if it is possible to > use an inverter inside the CPLD, feeding back the output of the > inverter to the input of the inverter, thus creating a "clock". Then, > I want to attach that "clock" to the part's global clock net and use > that clock as the clock for my state machine. > > Is something like this possible? Dangerous, but possible. If you do it, you should do it by a hard macro and use multiple logic stages in order to reduce the frequency. > What I'm really trying to do is implement an asynchronous state > machine that changes state only when its inputs change, without regard > to clocks. I don't have a clock to supply to the system. What I'm > finding, though, is most HDLs assume state machines are synchronous > and expect a clock. (and reset, for that matter.) If you do so, then you also need an asyncronous storage for your state. Something like RS-FlipFlops, for instance. These FlipFlops you have to create by your own, i.e. by logic equations. Sometimes it is also possible to "rape" existing D-Flipflops for this purpose. > If I have to use a clock to implement the state machine, I would of > course have to synchronise the asynchronous inputs with the state > machine clock. Simple enough, but I'd really rather not have to > supply an external clock to the system if at all possible. There's just one simple rule here: Do never ever feed an asynchronous input to more than one D-FlipFlop. Regards, MarioArticle: 55874
Hello all, I have an already implemnted design and I want just to make a copy of it. The only change I want is the value of some register (constant value), I am thinking to change these values in my code and select an exact guided PAR using the old ncd file. Is this the way to work or must I take further actions? The problem is that there is a lot of floorplanning done and I don't want to start over again doing that (keep the same PAR). Thanks a lot, Harris
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