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> Rick Filipkiewicz wrote: > >> I read on this NG that from 5.x onwards Win-NT is no longer `supported' >> by Xilinx. Since I'm loathe to change O/S for no very good reason and >> AFAIC, Win-NT 4.0 SP6A is as close to bomb-proof as any 'doze O/S has >> ever got I'd like to at least try installing 5.1 under NT. Russell wrote: > > Win2k is as bomb-proof as anything, and does all the usb and plug/pray > stuff. > ISE 5.X and Win2000 are probably OK, but if they say "not NT" then they may have a good reason for saying so. There are sometimes drivers involved, so Rick is asking a perfectly reasonable question. Getting an install without destroying the O/S may involve turning some stuff off at install time. Foundation 4.2i (ISE 4) and Win2K can make a real mess if you are not careful. Rick is right to be cautious on this score as well. -- Steve Williams "The woods are lovely, dark and deep. steve at icarus.com But I have promises to keep, steve at picturel.com and lines to code before I sleep, http://www.picturel.com And lines to code before I sleep." abuse@xo.com uce@ftc.govArticle: 49251
Hi all I am trying to understand a problem with one of my output in my design. I am currently using a PASIC 1 device with 84 pins. When I probed one of the pins which is normally high it gave a 50 ns low pulse. I have tried simulating the condition in Modelsim but I don't seem to be able to get the similar result. The signal is produced by small combinatorial and sequential logic and then before the output port, the result from the logic have to be inverted. I have removed the inverter and change some of the logic and this seem to have remove the 50 ns pulse. Could someone please explain this condition. Regards PaulArticle: 49252
You could try the following: 1.de-select "Push Tristates across Process/Block boundaries" which can be found in the Implementation Options, VHDL or Verilog tab. 2. Increase the default value for register fanout from 100 to maybe 500 (for non critical parts of the design). 3. Route the reset signals through dedicated clock nets (Instantiate BUFG) on reset nets. 4. Check if you might have overconstrained your design. 5. try gray encoding / binary encoding for state machines 6. Check if you have free blockram which maybe could be used for logic implementation. There usually is some space for area reduction when using Synplify.Article: 49253
Has anyone got experiance in using Nios 1.1 together with Quartus II 2.11. My Nios processor designs are not completely compiled. Half of the NIOS processor is missing on the FPGA (no internal memory..). Has anyone had problems like that or know what might be the reason (forgotten Options in Quartus...)? Thanks for any answers!Article: 49254
Hi, Thank you for the reply. Currently I am trying out a simple 2-processor configuration where each processor in addition to some local ram, has access to some global memory. I am trying to sort out some bugs in my design. Did you encounter any problems while trying to simultaneously access global memory? thank you once again. regards, Satchit kempaj@yahoo.com (Jesse Kempa) wrote in message news:<95776079.0211041534.11880063@posting.google.com>... > Hi, > > I've done several experimental designs with multiple CPUs without any > problems. > > One hint, though, in case you use custom instructions: each custom > instruction is defined and synthesized as its own design entity > (whether that is .v, .vhd, .edf, etc). If you have two CPUs and each > has a custom instruction, there can be some tool confusion if both > CPUs use a custom instruction of the same name (as all SOPC Builder > HDL code is generated in a common project directory). You can easily > safeguard this by ensuring each processor's custom instructions (if > any) have unique names inside the SOPC Builder GUI. > > Have fun with this - I'd be happy to hear about the progress of your > project! > > Regards, > > Jesse Kempa > > > satchit_h@hotmail.com (satchit) wrote in message news:<ddf018f6.0210300811.32d31548@posting.google.com>... > > Hi, > > > > has anybody tried a 2-nios parallel design using SOPC builder? I am > > trying to build one which can run separate pieces of code > > concurrently. Any comments would be helpful. thanks, > > > > regards, > > SatchitArticle: 49255
To help those trying to download 5.1SP2: I had similar problems, but clearing the web cache (e.g. deleting temporary files using the disk cleanup wizard in windows) is one way to correct the problem, allowing all 45 MB to be downloaded. Web server bug? Regards, Hans Holten-Lund IMM, Technical University of DenmarkArticle: 49256
Well, I am used to design in this way, using Synplify to synthesize and then bring up Xilinx DesignManager to place and route. With ISE 5.1, I can not find DesignManager anymore. Instead, I have to setup everything in ISE. I have a few questions about some problems I have. 1. How do I open the design projects created by DesignManager in previous Xilinx releases? 2. It seems I can not even bring up Synplify window in ISE 5.1. All I can do is something like blind or background synthesis. Is it a new FEATURE or just because of Window NT I am using ? 3. Can I just do place and route only (backend only, with external edif netlists) in ISE 5.1 ? 4. The latest Synplify 7.20 eliminates the link with Xilinx Design Manager. What you can do is to bring up ISE Navigator. But it can't setup Xilinx project (.npl). Do I have to setup again ? Thanks for any helps. qlyusArticle: 49257
In article <aq5di8$me2$1@mail.cn99.com>, pc_dragon@sohu.com says... > Hello, every one. > I'm working on a FPGA design project, it includes many module. > It'll take so long a time to run full implement one time when I only > make a little change in one module. > So I wonder how I can do incremental implement. I use Synplify Pro > and ISE 5.1i. > I've read the Xilinx document on how to do Incremental designing, but > not really understand, it seems that I need do it in Synplify Pro GUI mode. > Is it impossible to do it in ISE? And where can I find any example code? > > Thanks for any advence > That was my biggest complaint back when I used to use FPGAs. One change and it was another 12 plus hour respin. I likened it to building a multi-story building and then realizing you installed the wrong lightbulbs in the hallways and then tearing down the whole building including the foundation and starting over, but this time putting the right bulbs in when you get to that point. -- Rich Iachetta iachetta@us.ibm.com I do not speak for IBM.Article: 49258
hello, i often go through this expression, but never see what it means any explanations thanksArticle: 49259
hristo wrote: > > hello, > i often go through this expression, but never see what it means > any explanations > thanks More or less it's a jargon to indicate a device that does not perform any central function, but simply is a bridge to interface between more powerful subsystems (CPU, DSP, ASIC, etc). In the old days this was one of the main use of FPGAs. -- Tullio Grassi ====================================== Univ. of Maryland - Dept. of Physics College Park, MD 20742 - US Tel +1 301 405 5970 Fax +1 301 699 9195 ======================================Article: 49260
Hi, I am considering a project to implement a real-time adaptive filter algorithm (which is based on least square method) in an FPGA. My director tells me he wants the data rate is about 20 Mbits/s. After reading some articles, I think using FPGA is the only appropriate method for us. We cannot design an ASIC. I have read some articles on Andraka's website and one of his article about soft radio on Xilinx website. They are very useful to my work. Still I have many problems unresolved. The first one is like this. If the input data rate is about 20 Mbits/s, normally I had to sample it at about 80 MSPS in order to using a practical antialiase filter. Such high sample data rate can impose a lot of resource requirements even on the biggest and fastest FPGA. Can the data rate be decimated down to 40 MSPS just after digitizing? ThanksArticle: 49262
Hi, We are using Virtex-2 device for one of the applications and We have observed that the LUT utilization for a 16 + 16 bit adder is 16LUTs and also 16 + 1bit adder is also 16LUTs. The above is because the Carry chains are routed through LUTs. Is there any possibility of reducing the LUTs in case where unequal number of bits are added to less than the Max number of input vector. i.e. if say 24bits are added with 1bit, then can the logic can be such that it utilizes less than 24 LUTs Can anyne help me. Regards, SanjayArticle: 49263
I wrote:
> When last compiled to an XC4005E a couple of years back, my
> homebrew 16/32 bit RISC weighed in at 335 LUTs in 16 bit
Oops, those numbers I'd linked to were for a later
XC2S100 version of the processor, not the original
XC4005E/4010E targets, which were considerably smaller:
the earlier designs had been tweaked to synthesize well
for the 4K series parts, and omitted some of the frills
(RSUB, skip-on-bit, offset indirect addressing for LD/ST)
that were added later on.
From the map file for one of these early incarnations
of the processor, including the 16 bit core, 64 x 16 ROM,
32 x 16 RAM, and 8 bit I/O port:
Target Device : x4005e
Number of CLBs: 173 out of 196 88%
CLB Flip Flops: 48
4 input LUTs: 198
3 input LUTs: 12 (6 used as route-throughs)
Dual Port RAMs: 16
32X1 RAMs: 16
32X1 ROMs: 32
16X1 RAMs: 6
Number of bonded IOBs: 51 out of 61 83%
IOB Flops: 14
IOB Latches: 0
Number of clock IOB pads: 1 out of 8 12%
Number of primary CLKs: 1 out of 4 25%
Number of TBUFs: 177 out of 448 39%
Number of startup: 1 out of 1 100%
An annotated screenshot of the associated floorplan is at:
ftp://members.aol.com/fpgastuff/early_y1.tif
Just the core would weigh in at ~200 LUTs; without
the 2^N-1 immediate constants, ~150 LUTs.
Brian
Article: 49264Does anyone know of any documents that talk about processor microcode - (an instruction set that implements an instruction set) Thanks for any links RalphArticle: 49265
AMD put out a series of applications notes 20 years ago that made up a pretty good review of developing ISAs using microprogramming and bbit slice techniques. HenryArticle: 49267
>I am considering a project to implement a real-time adaptive filter >algorithm (which is based on least square method) in an FPGA. My director >tells me he wants the data rate is about 20 Mbits/s. 20 Mbits/s or 20 M Hz? You can get more than one bit per Hz if you have a good signal/noise ratio. Assuming that you mean 20 MHz bandwidth... >The first one is like this. If the input data rate is about 20 Mbits/s, >normally I had to sample it at about 80 MSPS in order to using a practical >antialiase filter. Such high sample data rate can impose a lot of resource >requirements even on the biggest and fastest FPGA. Can the data rate be >decimated down to 40 MSPS just after digitizing? Not "just" after. If your input signal has 20 MHz of bandwidth, you only need to sample at 40 megasamples/second in order to get all the information. But that assumes that you have filtered out everything above 20 MHz before your signal got to the A/D. Such filters are very hard to implement in the analog world. The trick you want is to use a rough analog filter, say one that kills everything above 40 MHz, sample fast enough to get everything that gets through the filter (80 megasamples/sec in this example), and then implement a good filter in the digital side. After that filter you don't have any signal (or noise) above 20 MHz so you can decimate your data stream down to 40 megasamples/sec. -- The suespammers.org mail server is located in California. So are all my other mailboxes. Please do not send unsolicited bulk e-mail or unsolicited commercial e-mail to my suespammers.org address or any of my other addresses. These are my opinions, not necessarily my employer's. I hate spam.Article: 49268
>We are using Virtex-2 device for one of the applications and We have >observed that the LUT utilization for a 16 + 16 bit adder is 16LUTs and also >16 + 1bit adder is also 16LUTs. The above is because the Carry chains are >routed through LUTs. Is there any possibility of reducing the LUTs in case >where unequal number of bits are added to less than the Max number of input >vector. i.e. if say 24bits are added with 1bit, then can the logic can be >such that it utilizes less than 24 LUTs In the dark ages of Xilinx 3000s it took 2 LUTs per bit. Draw the circuit/schematic for 1 bit. You have to compute two things. One is the bit. The other is the carry out to the next stage. Now get out your data sheet and look at the fine print for the CLB/slice. You want to find a way to implement that schematic or something logically equivalent using the pieces you find in the CLB/slice. There is special logic for doing the carry. See anything similar that computes the next bit? If so, then you can probably do it without a LUT. -- The suespammers.org mail server is located in California. So are all my other mailboxes. Please do not send unsolicited bulk e-mail or unsolicited commercial e-mail to my suespammers.org address or any of my other addresses. These are my opinions, not necessarily my employer's. I hate spam.Article: 49269
Hi Friend, Thank for your reply, But I don't think you can do it, because the Fast Carry Logic Mux has to be selected from LUT output. So I don't think we can reduce the LUTs, Can anybody comment on this. Thanks!!! --Sanjay "Hal Murray" <hmurray@suespammers.org> wrote in message news:usk2ocivlm0633@corp.supernews.com... > >We are using Virtex-2 device for one of the applications and We have > >observed that the LUT utilization for a 16 + 16 bit adder is 16LUTs and also > >16 + 1bit adder is also 16LUTs. The above is because the Carry chains are > >routed through LUTs. Is there any possibility of reducing the LUTs in case > >where unequal number of bits are added to less than the Max number of input > >vector. i.e. if say 24bits are added with 1bit, then can the logic can be > >such that it utilizes less than 24 LUTs > > In the dark ages of Xilinx 3000s it took 2 LUTs per bit. > > Draw the circuit/schematic for 1 bit. You have to compute two > things. One is the bit. The other is the carry out to the > next stage. > > Now get out your data sheet and look at the fine print for the CLB/slice. > You want to find a way to implement that schematic or something logically > equivalent using the pieces you find in the CLB/slice. > > There is special logic for doing the carry. See anything similar that > computes the next bit? If so, then you can probably do it without > a LUT. > > -- > The suespammers.org mail server is located in California. So are all my > other mailboxes. Please do not send unsolicited bulk e-mail or unsolicited > commercial e-mail to my suespammers.org address or any of my other addresses. > These are my opinions, not necessarily my employer's. I hate spam. >Article: 49270
Hi - my AEs installed 5.1i on WinNT without problems. However, when they tried installing service packs (sp-3 is available now), it gave hell lot of installation problems. I would not recommend using WinNT from 5.1i onwards. --Neeraj "Stephen Williams" <icarus-hates-spam@icarus.com> wrote in message news:3DC94F41.5020000@icarus.com... > > > Rick Filipkiewicz wrote: > > > >> I read on this NG that from 5.x onwards Win-NT is no longer `supported' > >> by Xilinx. Since I'm loathe to change O/S for no very good reason and > >> AFAIC, Win-NT 4.0 SP6A is as close to bomb-proof as any 'doze O/S has > >> ever got I'd like to at least try installing 5.1 under NT. > > > Russell wrote: > > > > Win2k is as bomb-proof as anything, and does all the usb and plug/pray > > stuff. > > > > ISE 5.X and Win2000 are probably OK, but if they say "not NT" then > they may have a good reason for saying so. There are sometimes drivers > involved, so Rick is asking a perfectly reasonable question. Getting > an install without destroying the O/S may involve turning some stuff > off at install time. > > Foundation 4.2i (ISE 4) and Win2K can make a real mess if you are > not careful. Rick is right to be cautious on this score as well. > -- > Steve Williams "The woods are lovely, dark and deep. > steve at icarus.com But I have promises to keep, > steve at picturel.com and lines to code before I sleep, > http://www.picturel.com And lines to code before I sleep." > > abuse@xo.com > uce@ftc.gov >Article: 49271
qlyus@yahoo.com (qlyus) wrote in message news:<da71446f.0211061423.50b7716b@posting.google.com>... > Well, I am used to design in this way, using Synplify to synthesize > and then bring up Xilinx DesignManager to place and route. With ISE > 5.1, I can not find DesignManager anymore. Instead, I have to setup > everything in ISE. I have a few questions about some problems I have. > > 1. How do I open the design projects created by DesignManager in > previous Xilinx releases? DesignManager has disappear but 'Project Navigator' is useful too. (I don't know how to answer to your question). > > 2. It seems I can not even bring up Synplify window in ISE 5.1. All I > can do is something like blind or background synthesis. Is it a new > FEATURE or just because of Window NT I am using ? > > 3. Can I just do place and route only (backend only, with external > edif netlists) in ISE 5.1 ? You can have an edif input for source file. That's what I use with FPGA Express. > > 4. The latest Synplify 7.20 eliminates the link with Xilinx Design > Manager. What you can do is to bring up ISE Navigator. But it can't > setup Xilinx project (.npl). Do I have to setup again ? > > Thanks for any helps. > > qlyusArticle: 49272
Austin Lesea <austin.lesea@xilinx.com> wrote in message news:<3DC7E7E5.A129CB7A@xilinx.com>... > Bernhard, > > LVDS in Virtex II and Virtex II Pro is current sourced, and is inherently > safe for a short circuit to each other, to ground, or to Vcco. > > In fact, given the size of our IOB transistors to meet all of the > standards, any IO standard is safe for any short circuit condition for > quite awhile (we have seen them go for months without a failure being > shorted). Momentary connector shorts are just fine. I would not > recommend shorting an output forever. > > Austin Thanks Austin, that was really helpful for me. And no, I do not plan to shorten them for THAT long (at least not on purpose :-). Thanks again BernhardArticle: 49273
Hi, just to let you know that the Xilinx Core Generator provides for each block a Data sheet, so you can find answers for your questions in the FIR filter Data sheet. All the best Rudolf Usselmann wrote: > 2comander2@gmx.de (Johannes) wrote in message news:<966f8080.0211060259.22a3b095@posting.google.com>... > > ich habe ein fir filter mit dem xilinx corgen gerneriert. jetzt meine > > frage welches signal braucht der filer auf dem ND-pin ? ist das clk > > signal des filters auch meine abtastfrequenz ? liest der filter die > > digitalen daten parallel ein und gibt sie parallel wieder aus ? > > > > bye Johannes > > Perhaps you might get more help trying in English: > > "I generated a FIR filter using Xilinx Coregen. Now I'm trying > to determine how to drive the ND pin of the filter. Is the > clock signal of the FIR filter also my sample rate ? Does the > filter read the digital data in, in parallel and output them > in parallel out again ?" > > Sorry, the translation isn't very good. I personally have never > used Coregens FIR filters so don't really know what Johannes > is talking about ... > > rudi > ------------------------------------------------ > www.asics.ws - Solutions for your ASIC needs - > FREE IP Cores: http://www.asics.ws/free_ip.shtml -- -Article: 49274
Hello, I'm looking for some advice concerning Altera's EPC16 device. The problem is that I'd like to programm it in circuit via JTAG, but it just doesn't work. The JTAG chain is o.k., I can successfully scan the chain read the ID code, perform a device blank check. Also the programming procedure does not lead to an error. But when I try to verify the data it fails at once. I've tried with Quartus II V1.1 and Altera's jam-player, both with the same result. As download cable I'm using a standard Altera ByteBlasterMV. Has anybody an idea, what could be wrong or what I could try to get more information about the situation? Any advice is very wellcome - Thanks in advance! Markus Fras
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