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Hi all, I'm new to this list and have a question about configuring a Virtex-II FPGA. In the design I'm working on, we use a second FPGA to configure a larger Virtex-II FPGA using the SelectMAP mode. The second, smaller FPGA loads the data from a connected memory chip. Now, I'm not sure when to pull down #CS and #WRITE. Can I do this right from the beginning (together with #PROGRAM), or do I have to wait until #INIT='1' (or are these signals ignored until #INIT='1'?) Thank you for your help, AndyArticle: 49376
Hello all, in xilinx's website it is mentioned that you cant use chipscope 3.3 on a PC based on Pentium 4 processor. Has anybody managed to install it on P4 machine? I dont care for the Chipscope core inserter but only for generator and analyzer. Also what version must I purchase in case I can't solve the problem mentioned above? I use Xilinx ISE 4.1 sp3 so probably I can't upgrade to the newest version (Chipscope PRO).. Ôhanks in advance for your help Best Regards, HarrisArticle: 49377
Hi, Xilinx also has a very low cost RS encoder IP. http://www.xilinx.com/ipcenter/catalog/search/logicore/reed_solomon_encoder. htm Your local Xilinx sales office should be able to help. --Neeraj "Kevin Neilson" <kevin_neilson@removethistextattbi.com> wrote in message news:VPFz9.3208$_P1.31699@rwcrnsc52.ops.asp.att.net... > Memec Design Services: > www.memecdesign.com > > "Zhenglin" <zdzlin@163.com> wrote in message > news:ee7a44f.-1@WebX.sUN8CHnE... > > Who has the RS encode core, I want to buy one for my friends? > >Article: 49378
Hi, What is the initialisation value of your timers? is it all 0's? Because if it's something different than all 0's and you still have problems you might have a problem with your reset line. As Dali said make sure your reset line gets through all your FFs. If you have an asynchronous external reset it should be easy to prove, if not (just for testing) you could give some dummy values to some registered Output signals and check if they get their reset values. I hope it helps. -- Ulises Hernandez ECS Technology Ltd. "golchehreh sohrab" <gsohrab@nri.ac.ir> wrote in message news:b1ccc6da.0211092256.4b8ad01f@posting.google.com... > Hello every body > I'm in an odd problem.I've a design that contains a timer that is > initialized at the reset time. I simulate in with Modelsim5.6a and > there is no problem. But after I synthesize it and Implememnt with > ISE4.2i and then I simulate its SDF file with modelsim I receive > awfull results. The oddest point is that my timers are not > initialized!I've checked it with the FPGA and in the FPGA they are > initailized! I don't know if it's the problem with my softwares or not > and if there is any solutions for it. > Thanks for any help > G.SohrabArticle: 49379
Hi, I'm working on FC2 compiler for the first time. My rtl is getting synthesised and I can see the design in the schematic with the intended logic .But the optimized output shows FPGA PADMAP2 error and I am unable to find where exactly the problem is. Any help will be highly appreciated. Thanks, Ashwini.Article: 49380
Hi, I have some problems with the bus macros that are used for 'intermodule communication'. On my test-board is a virtex xcv800 FPGA and for my diploma thesis I have to partially reconfigure this device. If I follow the modular design flow for partial reconfiguration (xapp290), 'ngdbuild' shows the following error: can not merge 'bm_4m' into block 'the_name_of_my_block' (TYPE=bm_4b) because one or more pins on the block, including pin "li<3>", were not found in the file. Please make sure that all the pins on the instantiated component match pins in the lower-level design block. If there are bussed pins on this block, make sure that the upper-level and lower-level netlists use the same naming convention. bm_4b.nmc is the macro provided by Xilinx. When I open it with the FPGA-Editor, the port names are exactly the same I use in my VHDL code (LI, LT, RI, RT, O), but it doesn't work. Why? Has someone some experience with this design flow? Thanks, MichaelArticle: 49381
Hi,
I use the rocbuf module with my spartan fpga like this:
entity(...
simGSR: in std_logic;
...
);
...
component rocbuf
port(i: in std_logic;
o: out std_logic;
);
end component rocbuf;
...
architecture ...
rocbuf_inst : rocbuf
port map (
i => simGSR,
o => GSRNet
);
...
But simGSR is always routed to a pin ... ??!! I need it only for
simulation else GSRNet should connect to the internal global reset of
the chip.
Is there something wrong?
Andreas
Article: 49382> I instanciate some components, such as OPNDRN, TRI, LCELL ...etc > (defined in MAXPLUS II) in my vhdl code. The VHDL declaration of > these component is build in Altera library and package. When I > use these component in VHDL, it need the follow two lines in code I would NOT recommand to use these constructs. (Almost) erverything can be expressed in VHDL and makes it device independent: e.g: TRI: pin_dout <= dout when ena='1' else "ZZZZZZZZ"; OPNDRN: pin_out <= '0' when dout='0' else 'Z'; LCELL: you don't need it. Martin -- JOP - a Java Optimized Processor for FPGAs. http://www.jopdesign.comArticle: 49383
Andreas, INIT going high tells you that the device is ready to be configured. If you attempt to configure before it is ready, you will not succeed. Austin Andreas Schweizer wrote: > Hi all, > > I'm new to this list and have a question about > configuring a Virtex-II FPGA. > > In the design I'm working on, we use a second FPGA to > configure a larger Virtex-II FPGA using the SelectMAP mode. > The second, smaller FPGA loads the data from a connected > memory chip. > > Now, I'm not sure when to pull down #CS and #WRITE. Can I do > this right from the beginning (together with #PROGRAM), or do > I have to wait until #INIT='1' (or are these signals ignored > until #INIT='1'?) > > Thank you for your help, > AndyArticle: 49384
Michael,
"University Newsgroup
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unmediated forum where you
can exchange curriculum and project ideas with your
peers around the world as
well as find solutions to problems. To subscribe send
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hosting this newsgroup."
(from the website: http://www.xilinx.com/univ/xup/course.htm#ug )
The above forum may be better for questions such as yours.
Austin
Ruppen Michael wrote:
> Hi,
>
> I have some problems with the bus macros that are used for 'intermodule
> communication'. On my test-board is a virtex xcv800 FPGA and for my
> diploma thesis I have to partially reconfigure this device. If I follow
> the modular design flow for partial reconfiguration (xapp290),
> 'ngdbuild' shows the following error:
>
> can not merge 'bm_4m' into block 'the_name_of_my_block' (TYPE=bm_4b)
> because one or more pins on the block, including pin "li<3>", were not
> found in the file. Please make sure that all the pins on the
> instantiated component match pins in the lower-level design block. If
> there are bussed pins on this block, make sure that the upper-level and
> lower-level netlists use the same naming convention.
>
> bm_4b.nmc is the macro provided by Xilinx. When I open it with the
> FPGA-Editor, the port names are exactly the same I use in my VHDL code
> (LI, LT, RI, RT, O), but it doesn't work. Why?
> Has someone some experience with this design flow?
>
> Thanks,
>
> Michael
Article: 49385
Max,
One thought: you are apparently going through all this trouble for some specific application. How about using a standard ASIC methodology for your desing: scan chains, ATPG, etc. You'll then be able to fully exercise every bit of logic you actually care about, under any conditions that suit you. Unused logic won't get tested, but who cares.
The downside is, of course, the 20% or so logic overhead. (Off-the-shelf scan and ATPG tools are expensive, but scan isn't too hard to manually code into a design, and ATPG can be contracted out).
ken
Article: 49386fireball <sensen@swirvemail.com> wrote in message news:<ee7a3b8.6@WebX.sUN8CHnE>... > Basically i'm doing a per pixel calculation for the whole panel. Each pixel > will a 3x3 matrix coefficient whereby i'll need to solve for let's say > variable x,y,z. I do not think that you need fancy algorithms for solving a 3x3 matrix. But the problem is, that you need divisions for solving the system. If you want to do this with small integer coefficients - which is advisable for fpgas - you will have difficulties controlling your rounding errors. Try a couple of matric multiplication algorithms (start with Gauss) and write out the resultin equations for x, y and z in closed form. Than try to rearrange the quations in a way that you get few division, small intermediate results and division as close to the output as possible. You can than just write it down in you favorite HDL and see how large it gets, using the standard synthesis. After this you can ask Ray Andraka how to do it in 1% of the area. Have fun, Kolja SulimmaArticle: 49387
To answer your question directly... Verliog. VHDL is needlessly complex for FPGA design. C is not a hardware language. Scott M.Article: 49388
Martin Schoeberl <martin.schoeberl@chello.at> wrote: >> I instanciate some components, such as OPNDRN, TRI, LCELL ...etc >> (defined in MAXPLUS II) in my vhdl code. The VHDL declaration of >> these component is build in Altera library and package. When I >> use these component in VHDL, it need the follow two lines in code > I would NOT recommand to use these constructs. (Almost) erverything can be > expressed in VHDL and makes it device independent: ACK > e.g: TRI: > pin_dout <= dout when ena='1' else "ZZZZZZZZ"; > OPNDRN: > pin_out <= '0' when dout='0' else 'Z'; ACK > LCELL: > you don't need it. Unfortunately, sometimes you DO need it. But I would place these things in Quartus, since it is really dependent on the actual device, and it is only relevant for place&route, so I would not include it in my VHDL- code Roman > Martin > -- > JOP - a Java Optimized Processor for FPGAs. > http://www.jopdesign.comArticle: 49389
Phil Hays <SpamPostmaster@attbi.com> wrote in message news:<3DCC717F.E6813572@attbi.com>... > lpm wrote: > > > I'm graduate student (and a FPGA newbie) designing a image processing > > system using a Spartan-II FPGA and have a question regarding where I > > should store the images that I'll be processing. Should I use an off > > board memory chip, and if so what's the best way to interface to it? > > Or, should I just store the image on the FPGA? Thanks for any > > assistance. > > How big is your image? If it fits into the FPGA memory (read the data > sheet), and you have no other uses for that memory, use the FPGA memory > as it will be faster and easier. If it doesn't, synchronous static RAM > (SSRAM) is fast and fairly easy to interface to, but is limited in > size. SDRAM is larger, has higher latency and is much more complex. > DDR SDRAM and Disks and flash memories are probably not of interest. > > Did this help? Thanks Phil, that does give me some options to think about.Article: 49390
Hello,
we are doing some work on the hardware acceleration of classical
high-performance computing applications. It is early days and we dont
have results yet but it is possible to do dense matrix applications on
an FPGA. We are using HandelC (and maybe SystemC behavioural once we
have done some more experiments with it) ... this enables one to focus
on specifying the algorithm rather than the structure of a system
capable of performing the algorithm as is the case with VHDL/Verilog.
It is kind of a similar argument as to why people code in C/C++ rather
than assembler. If you want pure performance then do it in
VHDL/Verilog, if you want to focus on algorithmics and trying stuff
out then do it in HandelC or SystemC behavioural.
If you do a search on hardware compilation you will find quite a few
research groups working on this area ... some are developing their own
language/compilers ... The options are to use a floating-point
library, fixed point (integer + scaling), plain big integers or
something more exotic like logarithmic arithmetic. Obviously you need
to determine the numerical accuracy that you require for your
application, then you can start to think about what type of arithmetic
to (efficiently) implement the LU decomposition. If you are doing
anything which requires floating-point/log arithmetic then I think you
will need a big virtexII chip if you want to exploit the parallelism
in the LU decomposition. As many people have already said, floating
point requires/consumes large amounts of FPGA resources.
Cheers,
Andy
fireball <sensen@swirvemail.com> wrote in message news:<ee7a3b8.6@WebX.sUN8CHnE>...
> Basically i'm doing a per pixel calculation for the whole panel. Each pixel will a 3x3 matrix coefficient whereby i'll need to solve for let's say variable x,y,z.
>
> DSP could be an alternative but the processing cannot be done in parallel with localized memory for each pixel.
>
> fixed point is fine with me as long as i know how to scale an offset to it.
>
> For start, i don't need to do it really fast but if i have a dynamic data being fed to the system, then panel will need to be refresh quickly.
>
> I'm a newbie using xilinx so i don't know what is nios about. i've ordered a normal virtex-II dev board. i didn't use a normal uC as there is not enought I/Os available.
>
> i guess if LU-decomposition is that hard then i'll do it the long way of solving inverse matrix A by calculating the cofactors..etc. Is this advisable?
>
> Right now i'm figuring how to use the block selectRAM to store the coef. Anybody has experience or simple example of doing this?
>
> Any other suggestions is most welcomed. Thanks.
Article: 49391I know it is probably a bad idea (more interconnect capacitence), but has anyone done an FPGA where the SRAM storage cells have the interconnect able to act as the bitlines, for fast parallel configuration loading/storing? -- Nicholas C. Weaver nweaver@cs.berkeley.eduArticle: 49392
Nicholas C. Weaver wrote: > > I know it is probably a bad idea (more interconnect capacitence), but > has anyone done an FPGA where the SRAM storage cells have the > interconnect able to act as the bitlines, for fast parallel > configuration loading/storing? Actel's ProASIC, Lattices latest XPGA, & Xilinx Coolrunner must have wide parallel loading, but in all cases, this is from on-chip NV storage. Did you want faster _re_configuration ? - there has to be scope in the SRAM based FPGA for faster config clocks. -jgArticle: 49393
Martin Thompson wrote: > "Philip Pemberton" <philpem@btinternet.com> writes: > >> Hi, >> I've just bought an Altera EPM7128ELC84-10 EPLD for the knock >> down price of £5 at a radio rally (hamfest). Does anyone know of a >> suitable programmer for this thing? Altera's datasheet says it can't >> be programmed in-system - does this mean I can't program it with a >> Byteblaster? > > I believe that in-situ programming started with the 7000S series, so > unfortunately you can't. It hasn't got the right pins for a > ByteBlaster :-( What type of programmer do I need to program this cursed thing then? Are the programming specs or schematics for any suitable programmers available anywhere? If not, anyone know of any suppliers that sell MAX7000S series EPLDs? Tried Farnell, £15 excluding VAT. Are there any other suppliers in the UK that will supply MAX7000S-es in one to five-off quantities at a more reasonable price? BTW, I'm a hobbyist - so please don't suggest any suppliers that only sell to trade customers :-) Thanks. -- Phil. philpem@despammed.com <<-- Yes, this address is real... http://www.philpem.dsl.pipex.com/Article: 49394
In article <3DD0196D.1D5F@designtools.co.nz>, Jim Granville <jim.granville@designtools.co.nz> wrote: >Nicholas C. Weaver wrote: >> >> I know it is probably a bad idea (more interconnect capacitence), but >> has anyone done an FPGA where the SRAM storage cells have the >> interconnect able to act as the bitlines, for fast parallel >> configuration loading/storing? > > Actel's ProASIC, Lattices latest XPGA, & Xilinx Coolrunner >must have wide parallel loading, but in all cases, this is >from on-chip NV storage. > Did you want faster _re_configuration ? - there has to be >scope in the SRAM based FPGA for faster config clocks. Yes, faster reconfiguration through a combination of parallel loading (the interconnect is a LOT of wires) and faster clocking. Also, for the design I'm doing, it saves transistors, a good 20-30% of the transistors in my switchpoints. I'm wondering if anyone has done that before, before I try the tradeoffs for myself. -- Nicholas C. Weaver nweaver@cs.berkeley.eduArticle: 49395
Hello, Basic Question i know but confused on: what is the difference between Hardware Description Language (HDL) and Register Transfer Logic(RTL) ThanksArticle: 49396
I'm a complete newbie to FPGA design. I've got a Matlab routine that I'd like to port to an FPGA. It does some array operations and makes use of an FFT. How do I ballpark the size of FPGA I'll need to do this? I don't even know where to start, so any pointers would be helpful. Thanks!Article: 49397
This is tough. I think HDLs can be either behavioral, in which the behavior but not the architecture of the circuit is described; RTL, which explicitly identifies all registers; or architectual, which is a netlist of primitives. Often code is written as a combination of these. Back in the day, HDLs were really only for modeling, and if you actually wanted to synthesize you had to write the code architecturally, which was about the same as drawing a schematic. Now you can write RTL code and it can synthesize. Even some behavioral code like loops will synthesize now, so the definitions of these terms are less meaningful. I guess it's best to say that RTL is one of a few styles of writing code in an HDL. -Kevin "Anonymous4" <nicemanYep@yahoo.co.uk> wrote in message news:f9028e31.0211111347.2bc4c99c@posting.google.com... > Hello, > Basic Question i know but confused on: > what is the difference between Hardware Description Language (HDL) and Register > Transfer Logic(RTL) > ThanksArticle: 49398
If you want to learn to be good with FPGA design, I'm with Phil et al. You
need to understand the underlying architecture in detail in order to design
efficiently to it. That said, if you are looking at the big green push button
design flow, and you are not aggressive with your targets, then you can get
away with direct from HDL. Please at least learn logic design before trying to
learn an HDL though.
I disagree with Scott's sentiment that VHDL is too complicated for FPGAs.
FPGAs are usually harder to design to than ASICs (more restrictions on the
design imposed by the architecture) as far as the digital logic part of the
design goes (ASICs can carry with them clock balancing, signal integrity,
loading and other phsyical issues that are usually pretty well hidden to the
FPGA designer). VHDL provides many of the hooks to make detailed design
(including physical) design that are either missing entirely (generates in pre
verilog 2000 verilog) or awkward (comment style for attributes). VHDL is more
verbose and is strongly typed, which can make the learning curve perhaps more
difficult. Personally, I find the stong typing helps guide the learning
process so you learn decent coding style too. Although I am not a fan of it, C
is being treated by several startups as a hardware description language. Some
have extensions to better describe hardware, making the learning curve not all
that different than verilog.
Scott Munroe wrote:
> To answer your question directly... Verliog. VHDL is needlessly complex for
> FPGA design. C is not a hardware language.
>
> Scott M.
--
--Ray Andraka, P.E.
President, the Andraka Consulting Group, Inc.
401/884-7930 Fax 401/884-7950
email ray@andraka.com
http://www.andraka.com
"They that give up essential liberty to obtain a little
temporary safety deserve neither liberty nor safety."
-Benjamin Franklin, 1759
Article: 49399Does anyone have a pointer to a canonical list of things to do and avoid doing when you want to write VHDL that has a good chance of actually synthesizing correctly in Leonardo? I only know that what I do tends to work better than what my students do (I have the unfortunate task of TAing a class in embedded systems and reprogrammable logic), but I admit that I don't have such a list of rules that will guarantee that VHDL works when it is synthesized, even if it works in simulation. Certainly someone out there must have a list... and I don't mean the "Synthesizable VHDL" subset, because even if the synthesis tools gives no warnings or anything, things can break horribly when additional processes are added, it seems.
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