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Messages from 49200

Article: 49200
Subject: Re: 16-bit FGPA CPU core (commercial)
From: Roger Larsson <roger.larsson@norran.net>
Date: Mon, 04 Nov 2002 23:59:36 GMT
Links: << >>  << T >>  << A >>
lenman wrote:

> I am looking for a small (and fast) CPU core optimized for FPGA (Actel or
> Altera). I have found the xr16 and gr0040 at www.fpgacpu.org (but it is
> not licensed for commercial use).
> 
> Know of any good ones?  Especially with development tools (e.g. gcc/gdb,
> etc).
> 
> Thanks,
> Lennie Araki

There are several CPU cores that can be found on:

http://www.opencores.org/projects?category=microprocessor

There are generally no mention of size and you have to check the
license before use. Some seem to have commercial support.

/RogerL

-- 
Roger Larsson
Skellefteå
Sweden

Article: 49201
Subject: Re: Excessive heating on Xilinx XC9500XL
From: Peter Alfke <peter@xilinx.com>
Date: Mon, 04 Nov 2002 17:14:04 -0800
Links: << >>  << T >>  << A >>
"untouchable" seems to mean "too hot to touch". That occurs at a
temperature significantly above 60 degrees C.
At 25 degree ambient, this means about 40 to 45 degrees
over-temperature. Look that up in the thermal impedance table...

Peter Alfke

Lorenzo Lutti wrote:

> "Andreas Kugel" <kugel@ti.uni-mannheim.de> ha scritto nel messaggio
> news:3DC656A3.3080005@ti.uni-mannheim.de...
>
> > One of our XC95288XL exhibits ecessive heating
> > (untouchable!).
>
> What do you mean with "untouchable"? It could be 50-60 C, which is
> completely safe.
>
> --
> Lorenzo


Article: 49202
Subject: Re: C\C++ to VHDL Converter
From: Phil Hays <SpamPostmaster@attbi.com>
Date: Tue, 05 Nov 2002 01:33:04 GMT
Links: << >>  << T >>  << A >>
Austin Franklin wrote:

> > We bang on about QoR, size, area performance...why don't we use
> > schematic capture and layout, this will give us serious efficiency?
> > Probably because multi-million gate designs, or even multi-hundred
> > thousand gate designs would take an eternity to complete and the
> > product would be defunct before it got anywhere near the market.
> 
> That's simply not true.  The Alpha CPUs were designed using schematic
> capture

... by a large building full of designers.


-- 
Phil Hays

Article: 49203
Subject: Re: C\C++ to VHDL Converter
From: Ray Andraka <ray@andraka.com>
Date: Tue, 05 Nov 2002 02:22:19 GMT
Links: << >>  << T >>  << A >>
With a good library and strong hierarchical design discipline, schematic
entry can be as fast as an HDL.  That said, I have seen very few (read
count on one hand) places that have the necessary library and discipline.
The library takes time to develop, so it not likely to be done by someone
doing just one or two designs.  HDLs do provide a few real benefits:

    readable/editable without special tools.
    parameterizable, means smaller libraries.
    elaborate testbenches.  HDL can be treated like a programming language
for simulation only stuff.
    ability to simulate parts of design with behavioral models to allow
full simulation before design is done.
    portable across tools, at least to some degree.

I do find that it takes longer to grok a design, especially one that
someone else did if it is presented in an HDL than in a well organized
schematic, but that's just because I work better with visuals than with
text.   I've seen some really good HDL and schematics, and some gawdawful
examples of both as well.  If good discipline is followed, I still believe
that a schematic design can be completed in the same time frame as an HDL
design, especially if you've already amassed a decent library of commonly
used pieces.  Heck, we do that with the HDLs now for much of the high
performance stuff...basically using generates to create a textual netlist.
Many times, it is less work to do that than to do the push on a rope trick
to get the synthesizer to produce what you want from an RTL description.
In those cases, the main advantage of the HDL is the parameterization
afforded.




Phil Hays wrote:

> Austin Franklin wrote:
>
> > > We bang on about QoR, size, area performance...why don't we use
> > > schematic capture and layout, this will give us serious efficiency?
> > > Probably because multi-million gate designs, or even multi-hundred
> > > thousand gate designs would take an eternity to complete and the
> > > product would be defunct before it got anywhere near the market.
> >
> > That's simply not true.  The Alpha CPUs were designed using schematic
> > capture
>
> ... by a large building full of designers.
>
> --
> Phil Hays

--
--Ray Andraka, P.E.
President, the Andraka Consulting Group, Inc.
401/884-7930     Fax 401/884-7950
email ray@andraka.com
http://www.andraka.com

 "They that give up essential liberty to obtain a little
  temporary safety deserve neither liberty nor safety."
                                          -Benjamin Franklin, 1759



Article: 49204
Subject: Re: new to fpga, what language is better to start with
From: Spam Hater <spam_hater_7@email.com>
Date: Tue, 05 Nov 2002 05:24:47 GMT
Links: << >>  << T >>  << A >>

You're new to FPGA's, but what are you -old- to?  And more important,
where do you want to go?

VHDL and Verilog both have their strengths, and weaknesses.

Which would be easier to learn depends on where you're starting from.

Which is more important to learn depends on, well, for example, who's
going to pay you money to use one of them.  (And to be 100% honest,
that's how I decide to use VHDL or Verilog on a project.)

SH7

On Mon, 4 Nov 2002 21:51:07 +0100, "Klemen" <nec4b@email.si> wrote:

>Hi!
>
>I'm new to FPGAs and i don't know in which language should i begin to
>design( vhdl, verilog, c). I currently have Webpack 4.1.
>
>regards
>


Article: 49205
(removed)


Article: 49206
Subject: Re: C\C++ to VHDL Converter
From: "Austin Franklin" <austin@da98rkroom.com>
Date: Tue, 5 Nov 2002 01:42:51 -0500
Links: << >>  << T >>  << A >>
Hi Ray,

>     elaborate testbenches.  HDL can be treated like a programming language
> for simulation only stuff.

Why is this precluded for schematics?

>     ability to simulate parts of design with behavioral models to allow
> full simulation before design is done.

Again, why is this precluded for schematics?

> I do find that it takes longer to grok a design, especially one that
> someone else did if it is presented in an HDL than in a well organized
> schematic, but that's just because I work better with visuals than with
> text.

It's because you can't see data flow in text.  Most everyone simply draws
out the data path via a block diagram, even if it's your own HDL or someone
else's.

And of course the MAJOR benefit of schematics (or netlisting using HDLs), is
you KNOW what the tools are going to give you for output, and you don't have
to fight with them NEAR as much to make things fit, and make timing.

The ideal methodology, IMO, is mixed schematic (for data path) and HDL for
control logic...but I've seen some very good schematic state machine designs
(and libraries can be used here as well) that no HDL could come close to.

Austin



Article: 49207
Subject: Re: tips for cutting down on slice usage in a VirtexII
From: Rick Filipkiewicz <rick@algor.co.uk>
Date: Tue, 05 Nov 2002 08:55:21 +0000
Links: << >>  << T >>  << A >>


Amy Mitby wrote:

> My design is using too many slices for the device
> I am targetting (XCV2000), although my LUT and slice
> flip flop count is under 100%. Any suggestions for logic
> and / or slice reduction?
>
> Number of slices: 5,246 out of 5,120
> Number of slice flip flops: 6,175 out of 10,240   60%
> Number of 4 input LUTs: 8,516 out of 10,240   83%

One thing that causes MAP to allocate more slices than the device holds
is `register alignment' or some such. I think you turn it off with a -r
flag.



Article: 49208
Subject: WebPACK 5.1 SP2
From: "Jan Pech" <j.pech@noSPAMieee.org>
Date: Tue, 5 Nov 2002 10:48:08 +0100
Links: << >>  << T >>  << A >>
I can't install the Service Pack 2 for my WebPACK. When I run the file
"5_1_02i_pc.exe", it just tells me that file cannot be unpacked and that
executable has been corrupted. I tried to download this file many times but
the result was every time the same:(
Is the file at Xilinx' web site really corrupted or is the problem somewhere
else?
Does anyone succeeded in installing SP2?
By the way, is it finally possible to use iMPACT with parallel cable as a
normal user under W2k after installing SP2?

Thanks,
Jan




Article: 49209
Subject: Re: C\C++ to HDL Converter, why not HDL -> C instead
From: Andrew MacCormack <andrewm@cadence.com>
Date: Tue, 05 Nov 2002 09:51:04 +0000
Links: << >>  << T >>  << A >>
Jim Granville wrote:
> 
> Interesting post.
> 
> What's the status of Transputer tools ?

The toolset was adapted in to the ST20 toolset, but I don't think anyone
at ST supports Occam anymore. The transputers have been end-of-lifed.

> 
> Don't STm still have some flavour of the Transputer targeting
> the set-top-box market ?
> 
The ST20 (formerly the T450) is in a number of chips serving the STB and
DVD markets. However, it doesn't really have any of the things that made
it a Transputer anymore (i.e. links and channels), although it has a
similar instruction set and register archiecture.

At least, that's where things were in 2000 when I left ST.

-- Andrew MacCormack                            andrewm@cadence.com
-- Senior Design Engineer                    Phone: +44 1506 595360
-- Cadence Design Foundry      http://www.cadence.com/designfoundry
-- Alba Campus, Livingston EH54 7HH, UK        Fax: +44 1506 595959

Article: 49210
Subject: Re: C\C++ to HDL Converter, why not HDL -> C instead
From: johnjakson@yahoo.com (john jakson)
Date: 5 Nov 2002 02:27:37 -0800
Links: << >>  << T >>  << A >>
Jim Granville <jim.granville@designtools.co.nz> wrote in message news:<3DC6DD1F.2957@designtools.co.nz>...
> john jakson wrote:
> > 
>  <snip good stuff >
> > I have now come to the conclusion that Transputing is the soft side of
> > RC & FPGAs are the hard side, both complimentary and somewhat
> > interchangeable. Now if you put a Transputer or 2 (or more) in FPGA,
> > it is not only the ideal embedded cpu, but it makes it easy to divy up
> > the project into HW (FPGA) & SW (T/Occam/.. code).
> > 
> > my 2c
> 
> Interesting post.
> 
> What's the status of Transputer tools ? 
> 
> Don't STm still have some flavour of the Transputer targeting 
> the set-top-box market ?
> 
> - jg



Rams site and Wotug have archives of the original Transputer tools
IIRC, I don't know what ST uses for current ST cores. The Transputer
cores are now embedded cores, the ISA is still the same but all the
Inmos technical talk of processes, Occam is all gone. ST only
describes the ISA in the blandest way. Only one link is left which
almost defeats the idea of multiple cpus, they did add lots of more
generic serial ports instead. It was morphed down into a dumb ass C
style cpu.

IIRC ST does use it in in 70% of set tops boxes.

Article: 49211
Subject: Re: C\C++ to HDL Converter, why not HDL -> C instead
From: "Tim" <tim@rockylogic.com.nooospam.com>
Date: Tue, 5 Nov 2002 10:32:04 -0000
Links: << >>  << T >>  << A >>
Andrew MacCormack wrote
> The ST20 (formerly the T450) is in a number of chips serving the STB and
> DVD markets. However, it doesn't really have any of the things that made
> it a Transputer anymore (i.e. links and channels), although it has a
> similar instruction set and register archiecture.

No on-chip channels!  They must have changed the instruction set.

And do they still have the ROM kernel?





Article: 49212
Subject: Re: FPGA convert to ASIC
From: johnjakson@yahoo.com (john jakson)
Date: 5 Nov 2002 03:04:17 -0800
Links: << >>  << T >>  << A >>
I would tend to aggree with Jay, but with the caveats,

If the design is hardly pipelined at all, you are replacing every LUT
with an actual std cell gate, the speed difference is easily 10x since
ASICs use small srams too & they are generally 10x slower than gates.

If the design is super pipelined, then the flops are the same and only
the switched wires remain. I would hazard a 2x speed difference.

So top of the line FPGA design with real logic in the paths may go
from 100-200MHz but most ASICs can be designed upto say 400-500MHz
depending on tools, manpower & budget. Now any ASIC running at at say
400MHz could likely run at 2GHz if you have a couple of hundred EEs
and use schematic entry & spice for everything, but those projects are
few & far between (AMD/Intel).

I had the reverse project, a mixed signal ASIC easily ran at 30MHz
limited by analog blocks. The digital probably could have run 50MHz no
sweat (AMI 0.6u mixed cmos). When the digital was extracted and dumped
into a X4085 it ran barely 1MHz. The digital design was trashed and a
more pipelined design eventually was able to get back to the system
clock. The ASIC had some paths that might have been 100 levels of
logic.

BTW AMI is in the FPGA to ASIC conversion business, but our project
never reached escape velocity.

Article: 49213
Subject: Re: Anyone has VHDL code for decimator and interpolater?
From: "Caillet" <regis.caillet@dspfactory.ch>
Date: Tue, 5 Nov 2002 12:04:44 +0100
Links: << >>  << T >>  << A >>

"chankc" <chankwanchien@yahoo.com> wrote in message
news:954ab655.0210302354.2aedc62a@posting.google.com...
> I am currently working on this two multirate signal processing. Anyone
> has VHDL code for decimator and interpolater for my reference?
that depend of which method is use to interpolate or decimate ?!



Article: 49214
Subject: Re: read and write same address of the ESB memory in the same cycle
From: "Wolfgang Loewer" <wolfgang.loewer@elca.de>
Date: Tue, 5 Nov 2002 12:21:40 +0100
Links: << >>  << T >>  << A >>
Assuming you're using the same, synchronous clock for reading and writing it
is possible. The overall maximum clock rate for access to the ESB will just
be slower. In Quartus you can specify whether the timing analyzer should
take simultaneous writes and reads from the same address into account. This
is some excerpt from the Quartus on-line help regarding this timing analyzer
option:

Cut Off Read During Write Signal Paths
Cuts off the delay from the write enable register through the Embedded
System Block (ESB) to any destination register during timing analysis. When
you turn Cut off read during write signal paths on, the Timing Analyzer does
not consider the delay along these paths during timing analysis.
If your design reads the data from the ESB as it is written, you may want to
turn off Cut off read during write signal paths. However, if your design
does not read the data from the ESB as it is written, the delay from these
paths can cause misleading results in your timing analysis unless you turn
on Cut off read during write signal paths.

Regards
Wolfgang
http://www.elca.de

"ssy" <shengyu_shen@hotmail.com> schrieb im Newsbeitrag
news:f4a5f64f.0211032303.26e343ab@posting.google.com...
> Hi all
>
> I use APEX20k400E, and I use the lpm_ram_dp in quartus II to construct
> my register file, all input signal is registered , so read and write
> are all sync
>
> so if I read and write the same address of this memory at the same
> clock edge, can I get the just writen value?
>
> Thanx



Article: 49215
Subject: Re: WebPACK 5.1 SP2
From: Uwe Bonnes <bon@elektron.ikp.physik.tu-darmstadt.de>
Date: Tue, 5 Nov 2002 11:38:34 +0000 (UTC)
Links: << >>  << T >>  << A >>
Jan Pech <j.pech@nospamieee.org> wrote:
: I can't install the Service Pack 2 for my WebPACK. When I run the file
: "5_1_02i_pc.exe", it just tells me that file cannot be unpacked and that
: executable has been corrupted. I tried to download this file many times but
: the result was every time the same:(
: Is the file at Xilinx' web site really corrupted or is the problem somewhere
: else?
: Does anyone succeeded in installing SP2?
: By the way, is it finally possible to use iMPACT with parallel cable as a
: normal user under W2k after installing SP2?

I downloaded it yesterday morning, and the file was about 48 MByte in
size. Trying to download yesterday evening resulted in a file with about 5
MByte size and the error you got.

Bye
-- 
Uwe Bonnes                bon@elektron.ikp.physik.tu-darmstadt.de

Institut fuer Kernphysik  Schlossgartenstrasse 9  64289 Darmstadt
--------- Tel. 06151 162516 -------- Fax. 06151 164321 ----------

Article: 49216
Subject: Decoupling requirements on VREF pins (Xilinx)
From: Uwe Bonnes <bon@elektron.ikp.physik.tu-darmstadt.de>
Date: Tue, 5 Nov 2002 12:08:38 +0000 (UTC)
Links: << >>  << T >>  << A >>
Hallo,

to implement a GTL+ interface with a Spartan II, I need four banks where I
will use the VREF pins.  With th PQ208 packages, this boils down to 16 pins
that need to get connected to the GTL+ reference voltage. 

What are the decoupling requirements for these Pins. Should every VREF pin
have it's own decoupling capacitor, may I group close VREF pins and use one
capacitor ofr that group or is the VREF decoupling on the VREF pin
uncritical? There will be no other consumer of the GTL VREF voltage on my
board.

Thanks

-- 
Uwe Bonnes                bon@elektron.ikp.physik.tu-darmstadt.de

Institut fuer Kernphysik  Schlossgartenstrasse 9  64289 Darmstadt
--------- Tel. 06151 162516 -------- Fax. 06151 164321 ----------

Article: 49217
Subject: Re: WebPACK 5.1 SP2
From: "Jan Pech" <j.pech@NOSPAMieee.org>
Date: Tue, 5 Nov 2002 13:22:15 +0100
Links: << >>  << T >>  << A >>
>
> I downloaded it yesterday morning, and the file was about 48 MByte in
> size. Trying to download yesterday evening resulted in a file with about 5
> MByte size and the error you got.
>

"My" size is 3.1 MB:)



Article: 49218
Subject: Re: WebPACK 5.1 SP2
From: "Leon Heller" <leon@heller123.freeserve.co.uk>
Date: Tue, 5 Nov 2002 12:35:39 -0000
Links: << >>  << T >>  << A >>

"Jan Pech" <j.pech@noSPAMieee.org> wrote in message
news:aq843a$2tgc$1@ns.felk.cvut.cz...
> I can't install the Service Pack 2 for my WebPACK. When I run the file
> "5_1_02i_pc.exe", it just tells me that file cannot be unpacked and that
> executable has been corrupted. I tried to download this file many times
but
> the result was every time the same:(
> Is the file at Xilinx' web site really corrupted or is the problem
somewhere
> else?

I had similar problems with the main Webpack file. Xilinx UK sent me a
CD-ROM with it, and the Service Pack.

Leon
--
Leon Heller, G1HSM
leon_heller@hotmail.com
http://www.geocities.com/leon_heller



Article: 49219
Subject: LVDS I/Os on Virtex-II Devices: Short circuit safety?
From: nonuschk@gmx.net (=?ISO-8859-1?Q?Bernhard_M=E4der?=)
Date: 5 Nov 2002 04:52:29 -0800
Links: << >>  << T >>  << A >>
Hi people

I'm working on a thesis project for which we'd like to use the
Virtex-II I/Os to connect to an external device via LVDS signals. The
question is: how safe are they concerning short circuits and the like?
Can I just route them to my connector? I can't risk to damage the
FPGA...

An option would be to use a dedicated LVDS chip (National Semi).

Thanks for any suggestions
Bernhard Mäder

Article: 49220
Subject: Re: WebPACK 5.1 SP2
From: Petter Gustad <newsmailcomp3@gustad.com>
Date: 05 Nov 2002 14:35:54 +0100
Links: << >>  << T >>  << A >>
"Jan Pech" <j.pech@noSPAMieee.org> writes:

> I can't install the Service Pack 2 for my WebPACK. When I run the file

Does anybody know if 5.1 is shipped to all Xilinx customers by now? I
haven't received mine yet...

Petter
-- 
________________________________________________________________________
Petter Gustad         8'h2B | ~8'h2B        http://www.gustad.com/petter

Article: 49221
Subject: multi-channel filters - how many channels?
From: "Ken Mac" <aeu96186@yahoo.co.uk>
Date: Tue, 5 Nov 2002 14:04:52 -0000
Links: << >>  << T >>  << A >>

Hello folks,

Xilinx coregens DA filter supports up to 8 channels for some of the FIR
filter types.

Could you please let me know what is the largest number of channels you have
used/seen used through a single FIR filter of any type (including
rate-changing) on an FPGA?

Thanks for your time,

Ken



Article: 49222
Subject: Re: C\C++ to VHDL Converter
From: Ray Andraka <ray@andraka.com>
Date: Tue, 05 Nov 2002 14:45:24 GMT
Links: << >>  << T >>  << A >>


Austin Franklin wrote:

> Hi Ray,
>
> >     elaborate testbenches.  HDL can be treated like a programming language
> > for simulation only stuff.
>
> Why is this precluded for schematics?

Schematics require you to come up with a circuit for the test bench.  If the
testbench is done as a programming language you have considerably more
flexibility.  When I was doing schematics, we often did testbenches in VHDL, but
it required additional tools to do it, and was at times awkward.

>
>
> >     ability to simulate parts of design with behavioral models to allow
> > full simulation before design is done.
>
> Again, why is this precluded for schematics?
>
> > I do find that it takes longer to grok a design, especially one that
> > someone else did if it is presented in an HDL than in a well organized
> > schematic, but that's just because I work better with visuals than with
> > text.
>
> It's because you can't see data flow in text.  Most everyone simply draws
> out the data path via a block diagram, even if it's your own HDL or someone
> else's.
>
> And of course the MAJOR benefit of schematics (or netlisting using HDLs), is
> you KNOW what the tools are going to give you for output, and you don't have
> to fight with them NEAR as much to make things fit, and make timing.

I do this for critical and placed stuff in HDLs using a library of generated
instances.  As you know, I had fine tuned my schematic entry to be able to turn
around designs quickly using a rather extensive library.  The same common
components written with generate statements encapsulating primitives works fine
in VHDL and gives the same degree of control as I had with schematics.  The big
win with VHDL is I have written those components so that they are parameterized
to generate exactly what is needed for each instance from a single library
design.  The advantage is if I make a change to the macro, it only gets changed
in one place, which is not necessarily true with schematics (using 2 bit slices
for arithmetic, it is almost true, but you still have the special cases at the
start and end of a carry chain).  The parameterization includes options for
layout, assignment to different device families (RLOC format for example),
automatic signed/unsigned extension, automatic selection of reset vector values
with the proper FDRE/FDSE etc.  These are things that were a little awkward with
schematics, and are very easy to do with the HDL generates.

>
>
> The ideal methodology, IMO, is mixed schematic (for data path) and HDL for
> control logic...but I've seen some very good schematic state machine designs
> (and libraries can be used here as well) that no HDL could come close to.

Yes, you've probably seen my schematic flow chart state machines too.  They are
very readable compared with HDL, and just as easy to edit.

The main reason for going to HDL, however (at least in my mind) is to maintain a
more or less mainstream tools flow, which seems to be pretty important to my
customers.  Schematic entry is considered by most to be an archaic design entry
method (not that I agree, but the fact is that is the prevailing attitude).  By
moving to HDLs a few years ago, I kept from locking myself out of many
customers.

So will I be seeing you in San Jose tomorrow?  If so, we can discuss this in
person.

>
>
> Austin

--
--Ray Andraka, P.E.
President, the Andraka Consulting Group, Inc.
401/884-7930     Fax 401/884-7950
email ray@andraka.com
http://www.andraka.com

 "They that give up essential liberty to obtain a little
  temporary safety deserve neither liberty nor safety."
                                          -Benjamin Franklin, 1759



Article: 49223
Subject: Re: WebPACK 5.1 SP2
From: Peter Wallace <pcw@karpy.com>
Date: Tue, 05 Nov 2002 07:28:10 -0800
Links: << >>  << T >>  << A >>
On Tue, 05 Nov 2002 05:35:54 -0800, Petter Gustad wrote:

> "Jan Pech" <j.pech@noSPAMieee.org> writes:
> 
>> I can't install the Service Pack 2 for my WebPACK. When I run the file
> 
> Does anybody know if 5.1 is shipped to all Xilinx customers by now? I
> haven't received mine yet...
> 
> Petter
 
I got mine a couple of weeks ago. It sits idle on my desk since I am
still running NT4 sp6a and have vowed to let no more Redmond Devils Spawn thru
our portals...

PCW

Article: 49224
Subject: How to approch timing constraints...
From: "Timing Newb" <>
Date: Tue, 5 Nov 2002 07:36:41 -0800
Links: << >>  << T >>  << A >>
Hello all<br>
<br>
I am running into problems with a VHDL based design with regards to designing timing constraints.  I have put together a couple VHDL projects in the past, but they were simple enough as well as slow and small enough with respect to the chip that timing was not a big issue... basically a matter of throwing down a single clock period constraint and pad delays.  I knew I was overconstraining the design, but since the rigorouse timing was met there seemed to be no need to go back and work on a set of appropriate loose constraints.<br>
<br>
I am now dealing with an upgrade to a design in which timing is not met nor was it met in the old design.  I am going by the logic that if the old design works and it did not meet timing that it is the case that:<br>
<br>
1) the original timing constraints were incorrect - they were too tight
2) the old design has glitches we haven't found yet due to timing errors
3) a combination of 1) and 2)
<br>
I am pursuing the first case and want to correct the original constraints.<br>
<br>
What I am unsure of is how to approach constraint selection for things like the pads to pads time, timing between logic running at different clocks, and in/out before/after constraints.  I have gone back and thoroughly mapped out the design into block diagrams so I know what clocks drive which modules (there is one clock input and one derived in the design) and am familiar with the information flow throughout the entire design.  I simply don't know of any kind of methodology.  Do I need to put together a diagram of when I expect signals to arrive and specify individual timing between each path or is there a faster way to apply general constraints?  Etc ad confusium...<br>
<br>
Thanks for any suggestions!



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