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On 18 Nov 2002 03:26:49 -0800, mohamed.shiha@link.net (Mohamed Shiha) wrote: >On 18 Nov 2002 03:26:49 -0800, in comp.arch.fpga you wrote: >Dear all, > >I would like to understand XC5204 bitstream format and be able to >design a program that takes bitstream (*.bit) file as input and gives >*.ncd file (place and route result file) or structural VHDL code file >as output ... There are no tools to do this. While not impossible, it would be extremely hard to do. i.e. multiple man-years effort. >I know that it has been made succesfuly by NeoCAd before and some fans >are working around with Virtex family .... Even Neocad did not achieve this. They reverse engineered the forward path (equiv to ncd-to-bits.) >Actually, I found a lot of useful information in the XC5200 datasheet >from Xilinx .. but something that I don't understand is the following >... > >"Bits per Frame = (34 x number of Rows) + 28 for the top + 28 for >the bottom + 4 splitter bits + 8 start bits + 4 error check bits + 4 >fill >bits + 24 extended write bits >= (34 x number of Rows) + 100" > >is the part that I don't understand ... > I can see more than 4 splitter bits ... Actually, I see 8 bits and >divided on two bytes .. something like that FC 7F so, C& are the >splitter .. they are exactly at the mid of the frame .... sometimes , >I see something like 04 also divided on two bytes ... But I never >found the splitting bits constant ... their values depend onm the >frame position and contents .... Some fields are encoded some aren't. 28+28+4+8+4+4+24 = 100 >Another remark ... How does Xilinx calculate the checksum bits ... I >figured out that the checksum of two identical frames is not the same >... Also, if i have changed something in the ncd file , the checksum >values of so many frames are changed ... sometimes, i see the checksum >changes before the frame of the data changes .. !!!!! The checksum is actually a running CRC, (not reset after each frame), so a change early in the bitstream affects all subsequent CRC fields. Look at patent 5,598,424 for more details than you could possibly want. at http://patft.uspto.gov/netahtml/srchnum.htm >The last comic is , what are the 28 bits for the top and the 28 bits >for the bottom .. ??? what does it mean ... ???? These are the I/O rows. 34 bits for CLB rows, 28 for I/O rows >Could anyone help with these things .. ??? > >With regards >Mohamed Shiha I know you don't want to hear this, but, I recommend you spend your time on something more useful than trying to reverse engineer the bit stream of a discontinued FPGA product family. Philip Freidin Philip Freidin FliptronicsArticle: 50076
> > > > That's exactly what I'm doing. The trickier thing is to convert those > > gray-coded values back in order to calculate the actual fill level of the > > fifo. There isn't any quick-and-dirty trick for doing this, is it? My method > > just converts them back (by a XOR chain) and subtracts the read pointer from > > the write pointer. > > Watch out! > Converting the Grey counter back to binary is counterproductive and a > waste of logic, for you again get multiple bits changing. You are back > where you started, and might as well use the original binary counter. > Binary subtraction of two counters in different clock domains > inevitably generates glitches and momentary errors. You can low-pass > filter them ( interrogate them several times in a row, then throw out > the strange value...) I only use the subtraction to determine how full the fifo is. I don't derive the full and empty signals (and thus the write and read allow signals) from that, those are generated directly by comparing the gray counters. The fifo's fill level is important to determine whether a new block transfer out of the fifo can be initiated. > > I am a hardware guy, and of no help with your Handel-C problem. > Viel Glück ! > Peter Alfke Thanks! Bernhard MäderArticle: 50077
"Bernhard Mäder" wrote: > I only use the subtraction to determine how full the fifo is. I don't derive > the full and empty signals (and thus the write and read allow signals) from > that, those are generated directly by comparing the gray counters. > > The fifo's fill level is important to determine whether a new block transfer > out of the fifo can be initiated. > Sounds to me like you do not really need the exact EMPTY signal, since you are reading blocks. Even if you do not need precision, you still have to watch out for garbage output from the binary subtractor. That's why I suggest the low-pass filtering. Most of the time the difference will be correct, but at transitions of either clock you can get these strange and weird errors... Gruß Peter AlfkeArticle: 50078
Am curious to know if anyone has had any experience interfacing an Analog SHARC DSP to a PCI-PCI bridge controller using a FPGA. One application note from Analog, and a proposed bi-directional design from the ADSP-21161 technical reference were all that I could find, and would welcome more specific details regarding the state diagrams, and buffers used. Thanks in anticipation of your response.Article: 50079
Hello, I am using ModelSim XE vcom 5.6a with the Trenz Electronic Spartan II development kit. It contains a "TE-BL.VHD" module to interface with a "test buttons and lights" board supplied with. Once synthetised and implemented on the FPGA board, it works perfectly. Yet, no way to simulate it: I always get the undocumented error: # ERROR: te-bl.vhd(389): Cannot read output: ion_b4. # ERROR: te-bl.vhd(417): Cannot read output: iop_b4. # ERROR: te-bl.vhd(423): VHDL Compiler exiting # ERROR: D:/Xilinx/modelsim/win32xoem/vcom failed. Has anybody an idea of what it means and could be wrong? Thank you for you help to a newbie, FB ps: the file can be downloaded on: http://www.trenz-electronic.de/down/downen.htm as "Application Note: Game of Life"Article: 50080
John Jacob wrote: > > Am curious to know if anyone has had any experience interfacing an Analog > SHARC DSP to a PCI-PCI bridge controller using a FPGA. One application note > from Analog, and a proposed bi-directional design from the ADSP-21161 > technical reference were all that I could find, and would welcome more > specific details regarding the state diagrams, and buffers used. > > Thanks in anticipation of your response. Maybe I don't understand the question, what good will it do to use a PCI to PCI bridge? The FPGA will have to implement a DSP to PCI interface which could be used without the PCI to PCI bridge. If your PCI chip has a local bus interface, you won't necessarily need the FPGA since it can likely be used directly on the DSP bus. -- Rick "rickman" Collins rick.collins@XYarius.com Ignore the reply address. To email me use the above address with the XY removed. Arius - A Signal Processing Solutions Company Specializing in DSP and FPGA design URL http://www.arius.com 4 King Ave 301-682-7772 Voice Frederick, MD 21701-3110 301-682-7666 FAXArticle: 50081
Take a look at the Bittware SharcFin ASIC. It was designed exactly for what you seem to be asking for: http://www.bittware.com/products/app-specific/ic.stm /Mikhail "John Jacob" <jjacob@graphite.com> wrote in message news:asb90q$v39$1@iruka.swcp.com... > Am curious to know if anyone has had any experience interfacing an Analog > SHARC DSP to a PCI-PCI bridge controller using a FPGA. One application note > from Analog, and a proposed bi-directional design from the ADSP-21161 > technical reference were all that I could find, and would welcome more > specific details regarding the state diagrams, and buffers used. > > Thanks in anticipation of your response. > > --- Outgoing mail is certified Virus Free. Checked by AVG anti-virus system (http://www.grisoft.com). Version: 6.0.422 / Virus Database: 237 - Release Date: 20/11/2002Article: 50082
>So the question should be re-phrased: Any hints on how to get the best >carry performance out of an Altera 10k (-4). You are just adding a number (from a register) into an accumulator. Right? You don't care about a delay (pipeline) as long as you can keep adding that number in on each clock cycle. I think it will be easy once you understand how to do it. The trick is to put a FF along the carry chain after N steps. Make N small enough to go at your target clock speed. Try google-ing for carry-save-adder. Assume you have one FF in the carry chain. Now the top half of your accumulator will be out of step with the bottom half whenever the FF has a one in it. If that's a problem, you can add a pipeline stage. That is do the add in two steps. The saved carry is the carry-in to the bottom of the top half. The add takes two cycles to complete, but you can start an add on each cycle. There are lots of special cases where you can convince yourself that it's not a problem and/or simplify parts of the fully pipelined system. -- The suespammers.org mail server is located in California. So are all my other mailboxes. Please do not send unsolicited bulk e-mail or unsolicited commercial e-mail to my suespammers.org address or any of my other addresses. These are my opinions, not necessarily my employer's. I hate spam.Article: 50083
> I am looking for a programmable oscillator for a XCV2000E board . >i.e the VIRTEX-E 2000 part. This FPGA has 3.3 volt I/O's. >I need it to be programmable between say, 1Mhz to 120 Mhz. >Moreover I need to be able to program it "after" it has been installed >on the board. There is a class of PLL chips that take a reference clock and multiply by N and divide by M. I've seen one that was programmed with a bit serial interface. Maybe they make them with a pin-per-bit so you can control them with switches or GPIO pins. Unfortunately, I don't have any part numbers to suggest and I couldn't find what I was looking for with a bit of google-ing. Maybe they don't make them any more? You might try google-ing for frequency-synthesis or frequency-synthesizer. You might be able to build your own using an external PLL chip with the division and phase detector inside the FPGA. The Motorola MC14515x (x=1,2,7,8) are close to what I was looking for, but they don't include the VCO. http://e-www.motorola.com/brdata/PDFDB/docs/MC145151-2.pdf Altera's Stratix may have everythying you need. Xilinx has an article on this area http://www.xilinx.com/xcell/xl31/xl31_32.pdf ICS has some chips that are close. www.icst.com The ones I saw only had one divider. -- The suespammers.org mail server is located in California. So are all my other mailboxes. Please do not send unsolicited bulk e-mail or unsolicited commercial e-mail to my suespammers.org address or any of my other addresses. These are my opinions, not necessarily my employer's. I hate spam.Article: 50084
> > > > Am curious to know if anyone has had any experience interfacing an Analog > > SHARC DSP to a PCI-PCI bridge controller using a FPGA. One application note > > from Analog, and a proposed bi-directional design from the ADSP-21161 > > technical reference were all that I could find, and would welcome more > > specific details regarding the state diagrams, and buffers used. > > > > Thanks in anticipation of your response. > > Maybe I don't understand the question, what good will it do to use a PCI > to PCI bridge? The FPGA will have to implement a DSP to PCI interface > which could be used without the PCI to PCI bridge. > > If your PCI chip has a local bus interface, you won't necessarily need > the FPGA since it can likely be used directly on the DSP bus. > The final system is being developed for a multi-process DSP board. Each board will consist of (6) DSP chips muxed together, and will occupy (1) PCI slot. Multiple boards will then be installed on a secondary bus behind the PCI-PCI bridge chip. According to the Analog engineering notes, a FPGA is used to convert the PCI signals into DSP format, and vice-versa. Their notes were pretty sketchy as to what buffers were required, and what the state diagrams were to look like for the interface. As it is now, the ADSP-21161 requires glue logic to seam the two together.Article: 50085
> Take a look at the Bittware SharcFin ASIC. It was designed exactly for what > you seem to be asking for: > http://www.bittware.com/products/app-specific/ic.stm > A quad DSP board for a PCI slot runs ~5K, with another 3K for the Visual DSP and 2K for their API - ~10K total. That seems expensive considering the chips are only ~30, PCB manufactures are at 1/2 capacity for lack of work, and shareware compilers are readily available. Their TigerSHARC board is likewise expensive - ~13K for (4) 1500 MFLOP DSP chips that list for ~200 each.Article: 50086
simply means you have an output port on your entity which you are also using as an
input to an equation in your architecture. Outputs can't be read back in. To get
around that, use an internal signal then drive that out
Frederic Bastenaire wrote:
> Hello,
>
> I am using ModelSim XE vcom 5.6a with the Trenz Electronic Spartan II
> development kit. It contains a "TE-BL.VHD" module to interface with
> a "test buttons and lights" board supplied with. Once synthetised and
> implemented on the FPGA board, it works perfectly. Yet, no way to simulate it:
> I always get the undocumented error:
>
> # ERROR: te-bl.vhd(389): Cannot read output: ion_b4.
> # ERROR: te-bl.vhd(417): Cannot read output: iop_b4.
> # ERROR: te-bl.vhd(423): VHDL Compiler exiting
> # ERROR: D:/Xilinx/modelsim/win32xoem/vcom failed.
>
> Has anybody an idea of what it means and could be wrong?
>
> Thank you for you help to a newbie,
>
> FB
>
> ps: the file can be downloaded on:
> http://www.trenz-electronic.de/down/downen.htm
> as "Application Note: Game of Life"
--
--Ray Andraka, P.E.
President, the Andraka Consulting Group, Inc.
401/884-7930 Fax 401/884-7950
email ray@andraka.com
http://www.andraka.com
"They that give up essential liberty to obtain a little
temporary safety deserve neither liberty nor safety."
-Benjamin Franklin, 1759
Article: 50087
Two part numbers I have used in the past...not sure if they are still around for
this. The first was a National Semi chip, CGS-410 which was designed for video
but worked well for other apps. IIRC it was N/M and also had a separate /P
output. I think you could get 3 somewhat unrelated frequencies out of it. It
uses a 47 bit serial program, easy to do with an FPGA in about a half dozen
slices.
The second, whic gave me more flexibility, was one of the ubiquitous motorola
88915(?), which doesn't have the dividers for M/N multiply, however it comes up
with I think a 2x clock on start up, so you can use in conjuction with dividers
in a cpld or FPGA to generate a programmable clock (used this solution on the
board described in my 1998 Radar environment simulator paper). There are more
recent parts which are probably better, just haven't been in the clock
specification end of things lately.
Hal Murray wrote:
> > I am looking for a programmable oscillator for a XCV2000E board .
> >i.e the VIRTEX-E 2000 part. This FPGA has 3.3 volt I/O's.
>
> >I need it to be programmable between say, 1Mhz to 120 Mhz.
> >Moreover I need to be able to program it "after" it has been installed
> >on the board.
>
> There is a class of PLL chips that take a reference clock and
> multiply by N and divide by M. I've seen one that was programmed
> with a bit serial interface. Maybe they make them with a pin-per-bit
> so you can control them with switches or GPIO pins. Unfortunately,
> I don't have any part numbers to suggest and I couldn't find what
> I was looking for with a bit of google-ing. Maybe they don't make
> them any more?
>
> You might try google-ing for frequency-synthesis or frequency-synthesizer.
>
> You might be able to build your own using an external PLL chip with
> the division and phase detector inside the FPGA.
>
> The Motorola MC14515x (x=1,2,7,8) are close to what I was looking for,
> but they don't include the VCO.
> http://e-www.motorola.com/brdata/PDFDB/docs/MC145151-2.pdf
>
> Altera's Stratix may have everythying you need.
>
> Xilinx has an article on this area
> http://www.xilinx.com/xcell/xl31/xl31_32.pdf
>
> ICS has some chips that are close. www.icst.com
> The ones I saw only had one divider.
>
> --
> The suespammers.org mail server is located in California. So are all my
> other mailboxes. Please do not send unsolicited bulk e-mail or unsolicited
> commercial e-mail to my suespammers.org address or any of my other addresses.
> These are my opinions, not necessarily my employer's. I hate spam.
--
--Ray Andraka, P.E.
President, the Andraka Consulting Group, Inc.
401/884-7930 Fax 401/884-7950
email ray@andraka.com
http://www.andraka.com
"They that give up essential liberty to obtain a little
temporary safety deserve neither liberty nor safety."
-Benjamin Franklin, 1759
Article: 50088John Jacob wrote: > > > > > > > Am curious to know if anyone has had any experience interfacing an > Analog > > > SHARC DSP to a PCI-PCI bridge controller using a FPGA. One application > note > > > from Analog, and a proposed bi-directional design from the ADSP-21161 > > > technical reference were all that I could find, and would welcome more > > > specific details regarding the state diagrams, and buffers used. > > > > > > Thanks in anticipation of your response. > > > > Maybe I don't understand the question, what good will it do to use a PCI > > to PCI bridge? The FPGA will have to implement a DSP to PCI interface > > which could be used without the PCI to PCI bridge. > > > > If your PCI chip has a local bus interface, you won't necessarily need > > the FPGA since it can likely be used directly on the DSP bus. > > > > The final system is being developed for a multi-process DSP board. Each > board will consist of (6) DSP chips muxed together, and will occupy (1) PCI > slot. Multiple boards will then be installed on a secondary bus behind the > PCI-PCI bridge chip. According to the Analog engineering notes, a FPGA is > used to convert the PCI signals into DSP format, and vice-versa. Their notes > were pretty sketchy as to what buffers were required, and what the state > diagrams were to look like for the interface. > > As it is now, the ADSP-21161 requires glue logic to seam the two together. Yes, I should have realized that you were using the PCI-PCI bridge with multiple devices. I assume that you are going to use one FPGA to interface several DSPs and so it is worth designing your own PCI FPGA rather than using an available chip. Be aware that there are cores available that have done most of the work for you. There are even some public domain cores. I can't remember the URL, but you might start looking at http://www.opencores.com/ -- Rick "rickman" Collins rick.collins@XYarius.com Ignore the reply address. To email me use the above address with the XY removed. Arius - A Signal Processing Solutions Company Specializing in DSP and FPGA design URL http://www.arius.com 4 King Ave 301-682-7772 Voice Frederick, MD 21701-3110 301-682-7666 FAXArticle: 50089
Try http://www.xilinx.com/xlnx/xil_prodcat_product.jsp?title=protoboards_protoboards_page for 30 or so companies, Also DMOZ http://dmoz.org/Computers/Hardware/Programmable_Logic/FPGA/Boards/ Also Optimagic, but quite dated http://www.optimagic.com/Article: 50090
I am looking for C behavior model for Content addressable memory. Also does anyone have links to tutorials of CAM?Article: 50091
does anyone have any idea on the complexity of implementing a string to integer conversion is hardware? It's got to be quite complicated. JimmyArticle: 50092
"John Jacob" <jjacob@graphite.com> wrote in message news:asbpov$1f5$2@iruka.swcp.com... > > Take a look at the Bittware SharcFin ASIC. It was designed exactly for > what > > you seem to be asking for: > > http://www.bittware.com/products/app-specific/ic.stm > > > > A quad DSP board for a PCI slot runs ~5K, with another 3K for the Visual DSP > and 2K for their API - ~10K total. That seems expensive considering the > chips are only ~30, PCB manufactures are at 1/2 capacity for lack of work, > and shareware compilers are readily available. > > Their TigerSHARC board is likewise expensive - ~13K for (4) 1500 MFLOP DSP > chips that list for ~200 each. > So, why exactly are you telling me this? You asked a technical question, I recommended you to take a look at their ASIC, not their boards. What all of this board/development tools cost math has to do with the original question? /Mikhail --- Outgoing mail is certified Virus Free. Checked by AVG anti-virus system (http://www.grisoft.com). Version: 6.0.422 / Virus Database: 237 - Release Date: 20/11/2002Article: 50093
> > The final system is being developed for a multi-process DSP board. Each > > board will consist of (6) DSP chips muxed together, and will occupy (1) PCI > > slot. Multiple boards will then be installed on a secondary bus behind the > > PCI-PCI bridge chip. According to the Analog engineering notes, a FPGA is > > used to convert the PCI signals into DSP format, and vice-versa. Their notes > > were pretty sketchy as to what buffers were required, and what the state > > diagrams were to look like for the interface. > > > > As it is now, the ADSP-21161 requires glue logic to seam the two together. > > Yes, I should have realized that you were using the PCI-PCI bridge with > multiple devices. I assume that you are going to use one FPGA to > interface several DSPs and so it is worth designing your own PCI FPGA > rather than using an available chip. Be aware that there are cores > available that have done most of the work for you. There are even some > public domain cores. I can't remember the URL, but you might start > looking at http://www.opencores.com/ > Interesting. I had not considered using a FPGA for the bridge itself, but there are many advantages in doing so. Found one PCI implementation at the site you referenced, and will study it in the days to come. Thanks for the valuable input!Article: 50094
Hi there.. This also applies to gnd and several other signals. The point is that I haven't even defined vcc and gnd as a pin or node or anything like that. It doesn't 'exists' in my project (ABEL). So what conclusion so I make of that? But a particular signal (WARNING:Xst:646 - Signal <ou> is assigned but never used.) bugs me a lot, because I have several state_diagrams where this OU is being outputted (also defined as OU NODE istype 'reg'). So what conclusion should I make about this (other that my HDL won't work..?)? Is it because it only exists as a NODE - if so, why does it not applies to other NODEs I have defined (though those two are being used in combinatorial logic)? Here is the complete list of 'warnings' (I want green arrows damnit! :) WARNING:Xst:646 - Signal <vcc> is assigned but never used. WARNING:Xst:646 - Signal <gnd> is assigned but never used. WARNING:Xst:646 - Signal <d4_xcbuf> is assigned but never used. WARNING:Xst:646 - Signal <d5_xcbuf> is assigned but never used. WARNING:Xst:646 - Signal <d6_xcbuf> is assigned but never used. WARNING:Xst:646 - Signal <d7_xcbuf> is assigned but never used. WARNING:Xst:646 - Signal <ou> is assigned but never used. WARNING:Xst:646 - Signal <addressing_xcd> is assigned but never used. I use d4-d7 several places in my state_diagrams. d7 is used, d6-d4 isn't. Addresssing is one of my state_diagrams, so this one confuses me much. PS. What does xcbuf and xcd mean? -- I doubt, therefore I might be.Article: 50095
"zhengyu" <zhengyu@attbi.com> wrote in message news:F_uG9.201727$QZ.29995@sccrnsc02... > does anyone have any idea on the complexity of implementing a string to > integer conversion is hardware? > It's got to be quite complicated. The IBM/360 could do it in two instructions. PACK and CVB. PACK converts characters to BCD by taking only the low nybble, except for the last byte, and CVB does the conversion from packed decimal to binary. Floating point is harder, and not usually implemented in hardware. If an iterative algorithm is fine, it isn't hard at all. A combinatorial algorithm will take more hardware, but not so much. Less than divide, for example. -- glenArticle: 50096
Kim -
There is a Xilinx note SOMEWHERE in their vast deposit of FAQs,
problems, etc.,
that addresses exactly this same issue. Declaring vectors wider than
needed - eg: defining something
like "d" to be 8 bits wide but only using 4 of the bits - could be the issue
if I remember correctly. I
think the unused parts get optimized out, and that's why you are getting
warned. These aren't errors...
BT
"Kim Noer" <kn@nospam.dk> wrote in message
news:asedgu$qj9ld$1@ID-151686.news.dfncis.de...
> Hi there..
>
> This also applies to gnd and several other signals. The point is that I
> haven't even defined vcc and gnd as a pin or node or anything like that.
It
> doesn't 'exists' in my project (ABEL). So what conclusion so I make of
that?
>
> But a particular signal (WARNING:Xst:646 - Signal <ou> is assigned but
never
> used.) bugs me a lot, because I have several state_diagrams where this OU
is
> being outputted (also defined as OU NODE istype 'reg'). So what conclusion
> should I make about this (other that my HDL won't work..?)?
>
> Is it because it only exists as a NODE - if so, why does it not applies
to
> other NODEs I have defined (though those two are being used in
combinatorial
> logic)?
>
> Here is the complete list of 'warnings' (I want green arrows damnit! :)
>
> WARNING:Xst:646 - Signal <vcc> is assigned but never used.
> WARNING:Xst:646 - Signal <gnd> is assigned but never used.
> WARNING:Xst:646 - Signal <d4_xcbuf> is assigned but never used.
> WARNING:Xst:646 - Signal <d5_xcbuf> is assigned but never used.
> WARNING:Xst:646 - Signal <d6_xcbuf> is assigned but never used.
> WARNING:Xst:646 - Signal <d7_xcbuf> is assigned but never used.
> WARNING:Xst:646 - Signal <ou> is assigned but never used.
> WARNING:Xst:646 - Signal <addressing_xcd> is assigned but never used.
>
> I use d4-d7 several places in my state_diagrams. d7 is used, d6-d4 isn't.
> Addresssing is one of my state_diagrams, so this one confuses me much.
>
> PS. What does xcbuf and xcd mean?
> --
> I doubt, therefore I might be.
>
>
Article: 50097Dear all, I need your help. The problem is pathmill again. I used it for my Wallace tree schematic. But I got warning information: WARNING:PathMill:0x20514003:Side branch device number is greater than 20 in stage of transistor (XI145.XI2.XI1.XI0.XI1.XI0.M7), node (XI145.XI2.XI1.XI0.XI1.NP), side branch is disabled. And in the resultant report, I got max path delay to be around 35ns. What can be wrong? Can you point out for me? thanks alot, -WalalaArticle: 50098
"Bill Turnip" <BTurnip@acm.org> wrote in message news:KZBG9.76678$GR5.16149@rwcrnsc51.ops.asp.att.net > There is a Xilinx note SOMEWHERE in their vast deposit of FAQs, > problems, etc., I actually managed to search this newsgroup before I asked :) and the result was what you said, it simply removed the unused signals. But that's not really the case in my questions. Here it actually does remove used signals (it claims so), and it has included two signals that I don't have in my project. -- I doubt, therefore I might be.Article: 50099
Ray Andraka <ray@andraka.com> wrote in message news:<3DE998F0.3E0E5352@andraka.com>... > simply means you have an output port on your entity which you are also using as an > input to an equation in your architecture. Outputs can't be read back in. To get > around that, use an internal signal then drive that out > Thank you for your help Mr Andraka. Once explained it seems so obvious: in the VHDL code from Trenz Electronic, the code does something like if signal = 'U' then signal<=1; end if; where signal is an output... I redefined as INOUT and everything works fine. Indeed your suggestion to define an intermediate signal is even better as it will not change interface definitions. Thank you again, FB
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