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Hi
You can program through the Altera Programming Unit (USB
support)/use's Data IO,don't buy old devices,chances getting bad
devices is also be there.
-Satya
"Philip Pemberton" <philpem@btinternet.com> wrote in message news:<aqp71t$c1020$1@ID-122086.news.dfncis.de>...
> Martin Thompson wrote:
> > "Philip Pemberton" <philpem@btinternet.com> writes:
> >
> >> Hi,
> >> I've just bought an Altera EPM7128ELC84-10 EPLD for the knock
> >> down price of £5 at a radio rally (hamfest). Does anyone know of a
> >> suitable programmer for this thing? Altera's datasheet says it can't
> >> be programmed in-system - does this mean I can't program it with a
> >> Byteblaster?
> >
> > I believe that in-situ programming started with the 7000S series, so
> > unfortunately you can't. It hasn't got the right pins for a
> > ByteBlaster :-(
> What type of programmer do I need to program this cursed thing then? Are the
> programming specs or schematics for any suitable programmers available
> anywhere?
> If not, anyone know of any suppliers that sell MAX7000S series EPLDs? Tried
> Farnell, £15 excluding VAT. Are there any other suppliers in the UK that
> will supply MAX7000S-es in one to five-off quantities at a more reasonable
> price? BTW, I'm a hobbyist - so please don't suggest any suppliers that only
> sell to trade customers :-)
>
> Thanks.
Article: 49426"Caillet" <regis.caillet@dspfactory.ch> wrote in message news:<aq88k1$258$1@rex.ip-plus.net>... > "chankc" <chankwanchien@yahoo.com> wrote in message > news:954ab655.0210302354.2aedc62a@posting.google.com... > > I am currently working on this two multirate signal processing. Anyone > > has VHDL code for decimator and interpolater for my reference? > that depend of which method is use to interpolate or decimate ?! Would you give me some example using two stages... CIC follow by FIR...Article: 49427
> Does anyone have a pointer to a canonical list of things to do and avoid > doing when you want to write VHDL that has a good chance of actually > synthesizing correctly in Leonardo? The general rule is to write code that you know is possible using logic gates. When you want to write something in VHDL just try and think how it would look as a block diagram, then how each block may look as a logical expression. Build designs from basic blocks such as counters, comparators, registers etc. Don't attempt to write a short complex algorithm that you may write in C, the synthesis tool will not break down complex operations into digital logic very consistently. I tend to go with the attitude that if I can't see how to implement it in logic then the synthesis tool can't either. Some people say that a HDL is designed to allow faster design times of digital logic circuits, it is not there to design circuits for you. MattArticle: 49428
"Philip Pemberton" <philpem@btinternet.com> writes: > Martin Thompson wrote: > > "Philip Pemberton" <philpem@btinternet.com> writes: > > > >> Hi, > >> I've just bought an Altera EPM7128ELC84-10 EPLD for the knock > >> down price of £5 at a radio rally (hamfest). Does anyone know of a > >> suitable programmer for this thing? Altera's datasheet says it can't > >> be programmed in-system - does this mean I can't program it with a > >> Byteblaster? > > > > I believe that in-situ programming started with the 7000S series, so > > unfortunately you can't. It hasn't got the right pins for a > > ByteBlaster :-( > What type of programmer do I need to program this cursed thing then? Are the > programming specs or schematics for any suitable programmers available > anywhere? We have an Altera programmer from years gone by, it has a big ISA card IIRC. No idea where you could get one from though... > If not, anyone know of any suppliers that sell MAX7000S series EPLDs? Tried > Farnell, £15 excluding VAT. Are there any other suppliers in the UK that > will supply MAX7000S-es in one to five-off quantities at a more reasonable > price? BTW, I'm a hobbyist - so please don't suggest any suppliers that only > sell to trade customers :-) > Are the MAX3000 devices any use to you - they are cheaper and also ISP-able. Not sure if you can buy them in hobby wuantities either - sorry, not much help am I?! Cheers, Martin -- martin.j.thompson@trw.com TRW Conekt, Solihull, UK http://www.trw.com/conektArticle: 49429
Hello folks, Xilinx coregens DA filter supports up to 8 channels for some of the FIR filter types. Could you please let me know what is the largest number of channels you have used/seen used through a single parallel FIR filter of any type (including rate-changing) on an FPGA? Thanks for your time, KenArticle: 49430
Hi, It will generate .xnf file which is same as EDIF. Only thing is it is Xilinx Proprietary. It will also give .edn file at the project directory location. Regards, Sanjay "Young-Su Kwon" <yskwon@vslab.kaist.ac.kr> wrote in message news:aqnceu$ll2$1@news.kreonet.re.kr... > > Is there anyone who have used ISE 5.1i? > I have used ISE 4.2i previosly and succeeded to generate EDIF from XST, > but XST of ISE 5.1i does not generate EDIF file. > Does anyone know how to generate EDIF from XST of ISE 5.1i? > > > -- > > *-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-* > Young-Su Kwon, > E-mail : yskwon@vslab.kaist.ac.kr > *-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-* > > >Article: 49431
> I can't understand the meanning of inserting LCELL buffer. Could > someone tell me when we insert LCELL in design? LCELL buffer allocates a logic cell for your project. (Logic Cell is a Macrocell, combinatorial logic and register, for Altera Classic PLD and a LUT, i.e. function generator, for FPGA). This sometimes provides control in logic synthesis: the Logic Synthesizer minimizes all logic that drives an LCELL primitive so that the logic fits into a single logic cell. LCELL primitives are always implemented in a logic cell, and they are never removed from the project even if they are fed by a single input. In logic synthesis you can also make the Synthesizer insert logic cells for routing purposes. But you have not to use LCELL primitive to create an intentional delay. :-) MarcoArticle: 49432
hi all, can you recommend an FPGA card in PCMCIA format? The only one I found was the Wildcard from Annapolis Micro Systems. Has anyone of you used it? Actually, we want to use it in an iPaq, which makes it a bit more tricky since AnnapMicro don't provide a driver for the iPaq. Any suggestions? Thanks a lot, ChristianArticle: 49433
In comp.lang.vhdl M Pedley <Pedley@talk21.com> wrote: I liked those last 2 paragraphs. If I were to teach HDL I would you those in the beginning of every lecture :) I think they nicely puts down the idea of what HDL design for synthesis is all about. regards, juza : I tend to go with the attitude that if I can't see how to implement it : in logic then the synthesis tool can't either. : Some people say that a HDL is designed to allow faster design times of : digital logic circuits, it is not there to design circuits for you. : Matt -- JuzaArticle: 49434
Phil Hays <SpamPostmaster@attbi.com> wrote:
>Then there is a pointer to an academic paper that compares different
>implementations of a 74181 ALU.
>
>http://www.sussex.ac.uk/Users/tapu9/publications/uk_acm_sigda_02.pdf
Very interesting. I haven't tested, but I made two versions of
the 74181 ALU using schematic entry, differing only in carry
lookup connections (synthesis wouldn't allow unused nets/pins).
The "no carry out" version (for low/middle slices) used 23 lookup
tables, the "no propagate" version (for the high slice) used 24.
A '182 CLG took only 7 LUT's. These "parts" were entered directly
from data sheet logic diagrams into WebPack 4.2 targeted for a
Spartan II ('50), only one 4-in gate was omitted in the nco
version so a full 181 should consume 25 LUT's.
The VHDL structural description in the article required 46 CLB's,
which for the 4004 I'm assuming contains 1 LUT. This seems to
imply that schematic entry is almost twice as efficient as
structured VHDL! So why even bother with language at all?
why not simply draw the gates and wires and be done with it?
Terry Newton (FPGA NuBe but trying to figure it out...)
Article: 49435Hi Stan, You can do IEEE 754 but the efficient will be low. A fully compliant single precision add/subtract unit would require around 800 LUTs and take 6 clock cycles to perform running around 100 MHz How efficient is that when you compare against 32-bit integer operations which takes 32 LUTS and 1 clock cycle at 250 MHz? Quantitative (Number of operations per seconds/ needed area) Floating point : (100_000_000/6)/800 = 20833 Integer : (250_000_000/1)/32 = 7812500 Integer operations are roughly 400 times more efficient than floating point. However floating point has some benefits of larger ranges and easier handling of different sizes of values. But if you know the exact algorithm and can translate it to integer operations, you will gain 400 times more efficiency. Not bad. Göran Stan wrote: > The more appropriate question is, can YOU do floating point? No but > seriously, it's not hard, do it the same way you do it on paper. -Stan > > "fireball" <sensen@swirvemail.com> wrote in message > news:ee7a3b8.3@WebX.sUN8CHnE... > > I'm trying to solve a 3 variable linear equation using matrix > (LU-decomposition method). Anybody can shed light on how to do this in FPGA > hardware? > > > > Can FPGA do floating point?Article: 49436
You do not need the FPGA in hand to synthesize, so just pick one, run the synth & compile, and see if it fits. You can download the software for most devices and it is free for the smaller (relatively speaking) ones. Scott M.Article: 49437
Hi, I'm a newbie at VHDL and want to implement a block with bi-directional data pins. The data pins will interface with a DPRAM that has one set of data lines and a single R/W_n line. Any pointers or info on how to use the bi-dir port in VHDL? -altgpagArticle: 49438
Hi all,
I'm trying to disable IOB register packing but am having trouble with
the UCF syntax. I know I want to put IOB=FALSE; in there somewhere but
how do I do it? I need to add the constraint to a number of top level
registers that are already grouped by a TIMEGRP constraint. I tried
using the following but it didn't like it:
TIMEGRP "SRAMData" = FFS("*WDATABuf*");
INST "SRAMData" IOB=FALSE;
Any ideas guys? Thanks for your help, Shareef.
Article: 49439Hi Justin! > Does anyone have a pointer to a canonical list of things to do and avoid > doing when you want to write VHDL that has a good chance of actually > synthesizing correctly in Leonardo? Well .. the first rule is: There are rules, how to code flipflops, latches and combinational logic. If you follow these rules, the code will by synthesizeable. With this follows, that every code, that can be broken down to parts, that fit the first rule, must be synthesizeable. RalfArticle: 49440
I'm taking 16384 samples that are 16bits each from an ADC, running an FFT on them, then doing various calculations based on the FFT (e.g. calculating bandwidths, determining amplitude ripple of the signal, etc.) It is floating point. Array processing can be done one element at a time, as speed is not critical for this application. The data is getting captured from an external ADC and stored in block RAM. It does fit as that part is being done already. We're also storing another waveform of the same size in RAM that could be wiped out to accomodate the FFT once the data is captured. I'm trying to determine if it's feasible to add this new functionality to the existing FPGA. We're using a Xilinx Virtex-II 1000... "Hal Murray" <hmurray@suespammers.org> wrote in message news:ut198e4fhol2ba@corp.supernews.com... > >I'm a complete newbie to FPGA design. I've got a Matlab routine that I'd > >like to port to an FPGA. It does some array operations and makes use of an > >FFT. How do I ballpark the size of FPGA I'll need to do this? > > You basically have to do a rough design in order to make an estimate. > > Do you have time to do your array processing one element at a time > (loop) or do you have to do things in parallel? > > Do you need floating point? That makes things much bigger, and much > more complicated. > > How big are your numbers? How many bits? Each bit takes a filp-flop > (or a slot in a RAM) so your design will get bigger if you need > more bits per word (more accuracy) in each number/register. > > What are you doing with the array? How big is it? Some FPGAs have > blocks of RAM. Will it fit? How is the data getting into > the array? > > Vendors usually have FFT cores that you can purchase. The documentation > probably gives you some sample space/speed numbers. > > Might be worth hiring a consultant for an afternoon or taking a class. > > -- > The suespammers.org mail server is located in California. So are all my > other mailboxes. Please do not send unsolicited bulk e-mail or unsolicited > commercial e-mail to my suespammers.org address or any of my other addresses. > These are my opinions, not necessarily my employer's. I hate spam. >Article: 49441
Hi Phil;
I agree with many of the comments previously expressed. In light of
Ray's comments, I would strongly agree. I would add some additional
comments, though. Namely, I find VHDL good for data path intensive
designs. This means digital signal processing and digital control
systems inside of an FPGA. For example, Xilinx's system generator tool
is written in VHDL, and is geared towards DSP. Verilog is just a less
verbose, and hence more compact language than VHDL. However, when you
are performing signed operations, even with Verilog 2001, you best be
damn careful of how you handle sign bits, etc. and this can burn you
if you're not careful. I really don't agree with the initiative by
some startups to try to bring C to the forefront as an HDL. I don't
see the detailed resolution or explanation by these companies on how
to handle the parallel synthesis issues. Sometimes, I get the feeling
that trying to design hardware with the C language is almost
equivalent to trying to solve every embedded application with an 8051
uC, it's just not wise to force a familiar tool to become a panacea to
solve all problems. Overall, I would suggest learning both languages,
and try to extract what is best for your given design in terms of
using VHDL or Verilog. For me, I've been implementing digital controls
in FPGA for about 4 years now, first with VHDL, now with Verilog, all
in the pretense that ASIC libraries are more established for Verilog.
My preference would be to code arithmetic operations and filters in
VHDL and things like state machines in Verilog.
Cheers,
James
Phil Hays <SpamPostmaster@attbi.com> wrote in message news:<3DD072CE.AE62F61A@attbi.com>...
> Ray Andraka wrote:
>
> <Lots of good stuff snipped>
>
> In levels of abstraction, think a range. Start with FPGAEditor. At
> this end, every detail must be specified by the designer. A fair amount
> of effort to do a simple design. But if the designer is careful, a very
> good answer, in terms of minimum FPGA resources and highest clock rate
> can be the reward for the effort. Personal opinions noted in {}; IMNHO
> YMMV SRA SDD PDCC. I'm not sure how Jbits would play into this, so I'll
> suggest that anyone interested can tell us if they want.
>
>
> Every detail must be specified by the designer.
>
> FPGAEditor, also XDL {XDL isn't very "novice friendly"}.
>
> Move to schematic/netlist(draw program/VHDL) with full placement
> information. (XDL?)
>
> Next is schematic/netlist(draw program/VHDL/Verilog).
>
> Next is RTL (VHDL/Verilog) {The place were Verilog is slightly
> better.}
>
> Next is behavioral (VHDL/Verilog/HandelC/SystemC) {Verilog is weak
> here} {HandelC is slightly better as a language than the alternatives
> here, however VHDL/Verilog tools are more mature.}
>
> Next is algorithmic or HLL level (C or Java or ??).
>
> At this end, almost every detail is generated by a program. If that
> program isn't too dumb, then the results will also not be too dumb.
> {I'm not convinced that any of these tools is worth using yet.}
>
> At this end of the range, results will be not as good. That's a given.
> However the design effort should be rather less, {key point} as long as
> the required level of performance isn't pushing the technology. If it
> is, the best way to proceed is often to move up the list, to lower
> levels of abstraction. This is one of the strong points of VHDL, by the
> way, one can rewrite the code into a different level of abstraction
> (usually lower) and {key point} not need to change languages.
>
> If you were to learn a single language, VHDL would be a good choice. If
> I was teaching a class in FPGA design, and didn't have access to
> something like FPGAEditor, I would start with netlist level VHDL, move
> to RTL level and then to behavioral level.
>
>
> (Almost a different subject)
> --------------------------------
>
> I went to Xilinx's web page to find more about Xilinx's "Forge" product,
> when the C language support is added, and the web site doesn't give a
> schedule, as this product might be interesting. However, the
> information given to support performance claims is very lame:
>
> http://www.xilinx.com/ise/advanced/forge_results.htm
>
> The triple DES. This is perhaps a best case, and it shows up ok when
> compared with a student project. {I don't think that's a very strong
> case.}
>
>
> Then there is a pointer to an academic paper that compares different
> implementations of a 74181 ALU.
>
> http://www.sussex.ac.uk/Users/tapu9/publications/uk_acm_sigda_02.pdf
>
> Different implementations, very different implementations, for among
> other differences the HandelC produces 7-segment outputs, and the other
> implementations don't. {I wonder why HandelC "lost" the comparison? If
> nothing else the review of examples was weak.} And this: "the logic
> synthesis tools are not able to detect the purely combinational
> implementation of the ALU 74181," maybe that's true for Forge Java, but
> is not true for HandelC or for VHDL{!!!} And HandelC isn't a pure
> software HLL, as it has an implied clock, and in HandelC all operations
> will be scheduled to occur in specific clock cycles, unless you
> specifically code them so as to be purely combinational. But enough of
> that.
>
> The conclusion of the paper is that VHDL is best, which might be true,
> and that Forge Java might be useful, which again might be true. But the
> real point of the paper is:
>
> {READ THIS}
>
> "An interesting conclusion of this study on description languages is
> that even when using a high-level language, the developer needs to have
> a good background in hardware design, in order to help the compiler to
> infer proper and efficient hardware constructors. Using general-purpose
> programming techniques in a hardware-based application will certainly
> result in too many gates and a highly inefficient circuit."
>
> This is a good statement to explain why the "dusty deck" dream is and
> will stay a dream for quite a while at least. But that doesn't mean
> that HLLs are not potentially very useful.
Article: 49442Justin A. Kolodziej wrote: > Does anyone have a pointer to a canonical list of things to do and avoid > doing when you want to write VHDL that has a good chance of actually > synthesizing correctly in Leonardo? 1. Use the synchronous template for all processes. 2. Simulate before you synthesize. -- Mike TreselerArticle: 49443
In article <3DCD423F.FEDF2184@attbi.com>, Phil Hays <SpamPostmaster@attbi.com> wrote: >I'd suggest: > >FPGAEditor. > >To be fairly good designing FPGAs requires understanding them at several >different levels of abstraction. The minimum lowest level is the >LUT/FF/PIP/IOB/clocktree/Carrychain/etc level. The correct tool in the >Xilinx world is FPGAEditor, and it's not in Webpack, but if I was >teaching a class in design using FPGAs the first lab assignment would be >to design and verify some simple logic using FPGAEditor or similar. >Without using autoroute. These days, I think you can largely get away with ignoring PIPs and Clock Tree, beyond the basics of "Routed interconnect, X clock trees", as the interconnects are SOOO rich. However, the CLB/IOB/BlockRAMs really should be understood in detail. I personally find that keeping a copy of the Jbits slice diagram above my desk is very nice (its slightly more detailed than the one in the datasheet). Placement IS key, so its not just the CLBs, but the grid, thats critical. Perosnally, probably the best thing which happened to me was the old CS150 project: A midi synthesizer in a 4005 (mine ALMOST fit in a 4003). It is when one has resource constraints that one really understands how to design for the part. >The reason is you need to learn what's in the FPGA first. > >I don't think you can get good with FPGA design without a good >understanding of the internals of the parts. > >Understanding a bit about transisitor design, device physics, layout, IC >fab, semiconductor test, etc would be useful, but I don't think it is >required. >Schematic level, done with pictures or text, would be next. And if you want performance, this is where you stay. "*HDL is a textual, placed schematic". -- Nicholas C. Weaver nweaver@cs.berkeley.eduArticle: 49444
atlgpag wrote: > I'm a newbie at VHDL and want to implement a block with bi-directional data > pins. The data pins will interface with a DPRAM that has one set of data lines > and a single R/W_n line. http://www.vhdl.org/comp.lang.vhdl/FAQ1.html#drivers -- Mike TreselerArticle: 49445
nicemanYep@yahoo.co.uk (Anonymous4) wrote in message news:<f9028e31.0211111347.2bc4c99c@posting.google.com>...
> Hello,
> Basic Question i know but confused on:
> what is the difference between Hardware Description Language (HDL) and Register
> Transfer Logic(RTL)
> Thanks
Those two terms are from different domains:
1. HDL (and schematic, etc.) is one of the means of describing circuits.
2. RTL is _abstraction_level_ of circuit description which assumes that
your circuit can be divided in two parts:
- Registers representing storage ('R' in RTL)
- Transfer function(s) representing combinatorial logic ('T' in RTL)
Depending on the nature of your design and available resources you can mix
and match various means and abstraction levels in your description.
Jerry
Article: 49446I'm designing an I/O device that must have ~70 32-bit memory-mapped registers. Some are written by software access, some are written by internal logic as status, and all must be readable by software. The way I've done this in the past with fewer MMRs is to just use the CLB registers. But with 70x32 bits, that burns a lot of flops. Granted, there are a lot of flops in the device (virtex2), but I wanted to see if anyone had come across this problem as well and solved it in a more area efficient manner.Article: 49447
Are there any major benefits or disadvantages to optimization with a synthesis design flow where module boundaries are registered either at inputs or outputs? In other words, do the tools' optimizations across module boundaries sometimes work better than self-imposed sequential boundaries for reaching better performance, or is it best to put those register boundaries in yourself and floorplan the location of those registers?Article: 49448
You might want to "test the waters" by downloading Xilinx's free Webpack and trying to run the flow in multiple FPGA choices, and then look at resource usage from the reports. Webpack is available off of a link from: http://support.xilinx.com/support/software.htm Altera might have something too, but I don't really know. <mr_donk@hotmail.com> wrote in message news:<jYVz9.800005$Ag2.27162437@news2.calgary.shaw.ca>... > I'm a complete newbie to FPGA design. I've got a Matlab routine that I'd > like to port to an FPGA. It does some array operations and makes use of an > FFT. How do I ballpark the size of FPGA I'll need to do this? > > I don't even know where to start, so any pointers would be helpful. > > Thanks!Article: 49449
Apart from DOS based PALASM does anyone know of any freeware which can generate a JEDEC file from Boolean equations or other descriptor ?
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